US7514779B2 - Multilayer build-up wiring board - Google Patents
Multilayer build-up wiring board Download PDFInfo
- Publication number
- US7514779B2 US7514779B2 US10/334,062 US33406202A US7514779B2 US 7514779 B2 US7514779 B2 US 7514779B2 US 33406202 A US33406202 A US 33406202A US 7514779 B2 US7514779 B2 US 7514779B2
- Authority
- US
- United States
- Prior art keywords
- metal film
- layer
- wiring board
- resin insulating
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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- 239000011780 sodium chloride Substances 0.000 description 1
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- 229910052719 titanium Inorganic materials 0.000 description 1
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- 229910052905 tridymite Inorganic materials 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
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- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/062—Means for thermal insulation, e.g. for protection of parts
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09645—Patterning on via walls; Plural lands around one hole
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09681—Mesh conductors, e.g. as a ground plane
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1178—Means for venting or for letting gases escape
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
Definitions
- the present invention relates to a multilayer build-up wiring board having build-up wiring layers each consisting of interlayer resin insulating layers and conductor layers provided alternately on both sides of a core substrate.
- the present invention relates to, in particular, a multilayer build-up wiring board provided with plane layer formed as a power conductor layer (power layer) or as a ground conductor layer (ground layer).
- one layer of a conductor circuit is used as a ground layer or a power layer in a multilayer build-up wiring board having a plurality of conductor layers (conductor circuits) isolated by interlayer resin insulating layers, respectively.
- a plain layer 559 forming a ground conductor layer (ground layer) or a power conductor layer (power layer) is often formed into a mesh pattern having mesh holes 559 a .
- the reason for providing the mesh holes 559 a is as follows.
- the plain layer 559 is formed of copper having a low connection property for connecting with resin, the connection between an upper layer or an interlayer resin insulating layer (not shown) and a lower layer ora resin core substrate (not shown) is improved by directly connecting the interlayer resin insulating layer to the core substrate with the mesh holes 559 a .
- it is intended to make it easy for gas containing moisture and the like absorbed by the interlayer resin insulating layer to exhale through the mesh holes 559 a.
- Japanese Patent Unexamined Application Publication No. 1-163634 proposes, as shown in FIG. 9B , a technique for providing the penetrating holes 559 a of an upper plain layer 559 and mesh holes 559 a of a lower plain layer 559 B so as not to overlap one another by shifting the positions of the penetrating holes 559 a of the upper plain layer 559 and those of the mesh holes 559 a of the lower plain layer 559 B from one another to thereby prevent recessed portions from being formed on the surface of a board.
- An interlayer resin insulating layer separating conductor layers is required to have high insulating property.
- the inventor of the present invention discovered that the insulating property of the interlayer resin insulating layer correlates to the relative positional relationship between the penetrating holes formed on the upper and lower plain layers. Then, a multilayer build-up wiring board is formed while the positions of the penetrating holes are adjusted, and the insulating property of the interlayer resin insulating layer is measured. As a result, the present inventor reached a conclusion that if the penetrating holes 559 a of the upper plain layer 559 are shifted from the mesh holes 559 a of the lower plain layer 559 B as shown in FIG. 9B , the insulating property of the interlayer resin insulating layer greatly deteriorates.
- One object of the present invention is to provide a multilayer build-up wiring board provided with a plain layer and having the less deterioration of the insulating property of the interlayer resin insulating layer.
- Japanese Patent Unexamined Application Publication No. 10-200271 proposes a technique, as shown in FIG. 23 , that mesh holes are not provided in a region of a plain layer 559 facing a chip mount region indicated by C and only provided in a region outside the chip mount region, thereby preventing irregular portions from being provided in the chip mounting region to thereby make the chip mount region flat on a multilayer printed circuit board.
- gas contained in the interlayer resin insulating layer is exhaled through the mesh holes. If no mesh hole is provided in the chip mount region as in the above technique, moisture does not exhale from an interlayer resin insulating layer below the chip mount region. Then, the interlayer resin insulating layer is peeled off or the insulation resistance of the interlayer resin insulating layer deteriorates.
- the present invention has been made to solve the above disadvantage and its still further object is to provide a multilayer build-up wiring board having less insulation deterioration of the interlayer resin insulating layer and capable of forming a flat chip mount region.
- a multilayer build-up wiring board forming a package board for mounting an IC chip and the like is formed by alternately building up interlayer resin insulating layers and conductor layers on a core board provided with through holes and by providing connection bumps for connecting to the IC chip on the upper surface side and bumps for connecting to a mother board on the lower surface side. Then, the upper and lower conductor layers are connected by forming via holes and the via holes on the upper layer of the core board and those on the lower layer thereof are connected to one another by a through hole.
- the via holes are formed by providing non-penetrating holes in the interlayer resin insulating layers. Due to this, the number of via holes of a fixed size to be formed in the multilayer build-up wiring board is physically limited, which is one of the factors disadvantageously preventing high concentration of the via holes in the multilayer build-up wiring board.
- the present invention has been made to solve the above disadvantage and its still further object is to provide a multilayer build-up wiring board capable of providing wirings with high concentration.
- Japanese Patent Examined Application Publication No. 4-55555 proposes a method of forming epoxy acrylate on a glass epoxy board, on which circuits are mounted, as interlayer resin insulating layers, providing opening portions for via holes using photolithography, roughening the surface, providing a plating resist and thereby forming conductor circuits and via holes by plating.
- a roughened layer made of Cu—Ni—P alloy for coating the conductor circuits and the like is formed by electroless plating and an interlayer resin insulating layer is formed thereon.
- the present invention has been made to solve the above disadvantage of the conventional technique and a still further object is to provide a wiring board and a multilayer build-up wiring board capable of preventing the concentration of stress derived from the change of temperature of the corners of the formed conductor circuit and preventing the resin insulating layer from cracking.
- a multilayer build-up wiring board recited in claim 1 is a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, technically characterized in that
- a multilayer build-up wiring board recited in claim 2 is a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, technically characterized in that
- the multilayer build-up wiring board according to claim 1 or 2 is characterized in that
- the mesh holes of the upper and lower plain layers are formed such that at least part of them overlay one another, thereby preventing the insulating properties of the interlayer resin insulating layers from greatly deteriorating.
- the diameter of each mesh hole is preferably 75 to 300 ⁇ m. The reason is as follows. If the diameter is less than 75 ⁇ m, it is difficult to overlay upper and lower mesh holes on one another. If it exceeds 300 ⁇ m, the conductor layers do not function as power conductor layers (power layers) or ground conductor layers (ground layers).
- the distance between the mesh holes is preferably 100 to 1500 ⁇ m. The reason is as follows. If the distance is less than 100 ⁇ m, the area of the plain layer becomes small and the plain layer cannot function. If the distance exceeds 1500 ⁇ m, the degree of deterioration of insulating properties of the interlayer resin insulating layers becomes considerably high.
- an adhesive for electroless plating as the above interlayer resin insulating layer.
- this adhesive for electroless plating it is optimal that heat resisting resin particles soluble to a hardened acid or oxidizing agent are dispersed into unhardened heat resisting resin which has difficult solubility to an acid or an oxidizing agent.
- the heat resisting resin particles are dissolved and removed by processing these resin particles using an acid or an oxidizing agent, and a coarsened face constructed by an anchor formed in the shape of an octopus trap can be formed on a layer surface.
- the above heat resisting resin particles particularly hardened are desirably constructed by using ⁇ circle around (1) ⁇ heat resisting resin powder having an average particle diameter equal to or smaller than 10 ⁇ m, ⁇ circle around (2) ⁇ cohesive particles formed by aggregating heat resisting resin powder having an average particle diameter equal to or smaller than 2 ⁇ m, ⁇ circle around (3) ⁇ a mixture of heat resisting powder resin powder having an average particle diameter from 2 to 10 ⁇ m and heat resisting resin powder having an average particle diameter equal to or smaller than 2 ⁇ m, ⁇ circle around (4) ⁇ pseudo-particles in which at least one kind of heat resisting resin powder or inorganic powder having an average particle diameter equal to or smaller than 2 ⁇ m is attached to the surface of heat resisting resin powder having an average particle diameter from 2 to 10 ⁇ m, ⁇ circle around (5) ⁇ a mixture of heat resisting powder resin powder having an average particle diameter from 0.1 to 0.8 ⁇ m and heat resisting resin powder having an average particle diameter greater than 0.8
- Rmax preferably ranges from 0.1 to 5 ⁇ m in the semi-additive method since an electroless plating film can be removed while the close attaching property is secured.
- the heat resisting resin which has difficult solubility to an acid or an oxidizing agent mentioned above is desirably constructed by “a resin complex constructed by thermosetting resin and thermoplastic resin”, or “a resin complex constructed by photosensitive resin and thermoplastic resin”.
- the former has a high heat resisting property. The latter is desirable since the opening for the via hole can be formed by photolithography.
- thermosetting resin can be constructed by using epoxy resin, phenol resin, polyimide resin, etc.
- thermosetting resin is photosensitized, a thermosetting group acrylic-reacts on methacrylic acid, acrylic acid, etc. Acrylate of the epoxy resin is particularly optimal.
- the epoxy resin can be constructed by using epoxy resin of novolak type such as phenol novolak type, cresol novolak type, etc., dicyclopentadiene-modified alicyclic epoxy resin, etc.
- the thermoplastic resin can be constructed by using polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyether imide (PI), etc.
- PES polyether sulfone
- PPS polysulfone
- PES polyphenylene sulfide
- PPE polyphenyl ether
- PI polyether imide
- a mixing weight ratio of the above heat resisting resin particles is preferably set to range from 5 to 50 weight % and desirably range from 10 to 40 weight % with respect to the solid content of a heat resisting resin matrix.
- the heat resisting resin particles are preferably constructed by amino resin (melamine resin, urea resin, guanamine resin), epoxy resin, etc.
- the adhesive may be constructed by two layers having different compositions.
- Various kinds of resins can be used as a solder resist layer added to a surface of the multilayer build-up wiring board.
- resins can be used as a solder resist layer added to a surface of the multilayer build-up wiring board.
- bisphenol A-type epoxy resin acrylate of bisphenol A-type epoxy resin, novolak type epoxy resin, resin formed by hardening acrylate of novolak type epoxy resin by an amine-systemhardening agent, an imidazole hardening agent, etc.
- solder resist layer is separated since the solder resist layer is constructed by resin having a stiff skeleton. Therefore, the separation of the solder resist layer can be also prevented by arranging a reinforcing layer.
- the above acrylate of the novolak type epoxy resin can be constructed by using epoxy resin in which glycidyl ether of phenol novolak and cresol novolak reacts with acrylic acid, methacrylic acid, etc.
- the above imidazole hardening agent is desirably formed in a liquid state at 25° C. since the imidazole hardening agent can be uniformly mixed in the liquid state.
- Such a liquid state imidazole hardening agent can be constructed by using 1-benzyl-2-methylimidazole (product name: 1B2MZ), 1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (product name: 2E4MZ).
- An adding amount of this imidazole hardening agent is desirably set to range from 1 to 10 weight % with respect to a total solid content of the above solder resist composition substance. This is because the imidazole hardening agent is easily uniformed and mixed if the adding amount lies within this range.
- a composition substance prior to the hardening of the above solder resist is desirably constructed by using a solvent of a glycol ether system as a solvent.
- This solvent of the glycol ether system preferably has 10 to 70 wt % with respect to a total weight amount of the solder resist composition substance.
- thermosetting resin for improving a heat resisting property and an antibasic property and giving a flexible property thermosetting resin for improving a heat resisting property and an antibasic property and giving a flexible property
- a photosensitive monomer for improving resolution, etc. can be further added to the solder resist composition substance.
- the leveling agent is preferably constructed by monomer of acrylic ester.
- a starting agent is preferably constructed by Irugacure 1907 manufactured by CHIBAGAIGI.
- a photosensitizer is preferably constructed by DETX-S manufactured by NIHON KAYAKU.
- a coloring matter and a pigment may be added to the solder resist composition substance since a wiring pattern can be hidden.
- This coloring matter is desirably constructed by using phthalocyaline green.
- Bisphenol type epoxy resin can be used as the above thermosetting resin as an adding component.
- this bisphenol type epoxy resin there are bisphenol A-type epoxy resin and bisphenol F-type epoxy resin.
- the former is preferable when an antibasic property is earnestly considered.
- the latter is preferable when low viscosity is required (when a coating property is earnestly considered).
- a polyhydric acrylic-system monomer can be used as the above photosensitive monomer as an adding component since the polyhydric acrylic-system monomer can improve resolution.
- DPE-6A manufactured by NIHON KAYAKU and R-604. manufactured by KYOEISYA KAGAKU can be used as the polyhydric acrylic-system monomer.
- solder resist composition substances preferably have 0.5 to 10 Pa ⁇ s in viscosity at 25° C. and more desirably have 1 to 10 Pa ⁇ s in viscosity since these solder resist composition substances are easily coated by a roll coater in these cases.
- a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, provided with a chip mount region on which a chip is mounted on an outermost layer and having the conductor layers connected to each other by via holes, respectively characterized in that
- mesh holes are formed in a region in the plain layers facing the chip mount region of the outermost layer through the interlayer resin insulating layers and the land of a through hole or via hole and a pad to which a via hole is connected are provided in at least part of the mesh holes with a distance kept between the land and pad and the peripheral edge of the mesh hole. Due to this, the interlayer resin insulating layer provided above the plain layer and the interlayer resin insulating layer (or a resin core substrate) provided below the plain layer can be directly connected with each other through the mesh holes provided on the outer periphery of the land, thereby making it possible to increase bonding property.
- gas containing moisture and the like absorbed by the interlayer resin insulating layers can be exhaled through the mesh holes provided on the outer peripheries of the land, so that the insulating properties of the interlayer resin insulating layers can be improved. Further, since the land and via hole are provided in each of the mesh holes in the chip mount region, no irregular portions are formed and the chip mount region can be made flat.
- a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, provided with a chip mount region on an outermost layer and having the conductor layers connected to each other by via holes, respectively, is characterized in that
- mesh holes are formed in a region in the plain layers facing the chip mount region of the outermost layer through the interlayer resin insulating layers and the land of a via hole is provided in each of at least part of the mesh holes with a distance kept between the land of the via hole and the peripheral edge of the mesh hole. Due to this, the interlayer resin insulating layer provided above the plain layer and the interlayer resin insulating layer (or a resin core substrate) provided below the plain layer can be directly connected with each other through the mesh holes provided on the outer periphery of the land of the via hole, thereby making it possible to increase bonding property.
- gas containing moisture and the like absorbed by the interlayer resininsulating layers can be exhaled through the mesh holes provided on the outer peripheries of the lands, so that the insulating properties of the interlayer resin insulating layers can be improved. Further, since a via hole is provided in each of the mesh holes in the chip mount region, no irregular portions are formed and the chip mount region can be made flat.
- a multilayer build-up wiring board obtained by alternately providing interlayer resin insulating layers and conductor layers, provided with a chip mount region on an outermost layer is characterized in that
- mesh holes are formed in a region in the plain layers facing the chip mount region of the outermost layer through the interlayer resin insulating layers and a solid conductor layer is provided in each of at least part of the mesh holes with a distance kept between the solid conductor layer and the peripheral edge of the mesh hole. Due to this, the interlayer resin insulating layer provided above the plain layer and the interlayer resin insulating layer (or a resin core substrate) provided below the plain layer can be directly connected with each other through the meshes provided on the outer periphery of the solid conductor layer, thereby making it possible to increase bonding property.
- gas containing moisture and the like absorbed by the interlayer resin insulating layers can be exhaled through the mesh holes provided on the outer peripheries of the solid conductor layers, so that the insulating properties of the interlayer resin insulating layers can be increased. Further, since the solid conductor layer is provided in each of the mesh holes in the chip mount region, no irregular portions are formed and the chip mount region can be made flat.
- a multilayer build-up wiring board wherein interlayer resin insulating layers and conductor layers are alternately provided on a substrate having through holes and a chip mount region for mounting a chip is provided on an outermost layer, is characterized in that
- mesh holes are formed in a region in the plain layers facing the chip mount region of the outermost layer through the interlayer resin insulating layers and the land of a the through hole is provided in each of at least part of the mesh holes with a distance kept between the through hole and the peripheral edge of the mesh hole. Due to this, the interlayer resin insulating layer provided above the plain layer and the interlayer resin insulating layer (or a resin core substrate) provided below the plain layer can be directly connected with each other through the meshes provided on the outer periphery of the lands, thereby making it possible to increase bonding property.
- gas containing moisture and the like absorbed by the interlayer resin insulating layers can be exhaled through the mesh holes provided on the outer peripheries of the lands, so that the insulating properties of the interlayer resin insulating layers can be increased. Further, since the land is provided in each of the mesh holes in the chip mount region, no irregular portions are formed and the chip mount region can be made flat.
- the plain layer may face the chip mount region through at least one of the interlayer resin insulating layers according to the present invention.
- a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, respectively, the multilayer wiring layer formed on a core substrate, is characterized in that
- a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, respectively, the multilayer wiring layer formed on a core substrate, characterized in that
- a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, respectively, the multilayer wiring layer formed on a core substrate, said conductor layers electrically connected to conductor layers on back side of the core substrate by through holes formed in the core substrate, respectively, is characterized in that
- the multilayer build-up wiring board recited in claim 10 since a plurality of wiring paths are arranged in one through hole, several times as many the wiring paths as the through holes can be passed through the core substrate. Also, since the via hole provided right on the through hole consists of a plurality of wring paths, several times as many the wiring paths as the via holes can be passed through the interlayer resin insulating layers. This makes it possible to provide wirings on the multilayer build-up wiring board with high concentration. Besides, due to the fact that via holes are formed right on the through holes, the wiring length becomes shortened and it is possible to deal with the demand of providing a high-speed multilayer build-up wiring board.
- a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, the multilayer wiring layer formed on both sides of a core substrate, conductor layers of the both sides of said core substrate electrically connected to one another by through holes formed in the core substrate, is characterized in that
- the multilayer build-up wiring board recited in claim 11 since a plurality of wiring paths are arranged in one through hole, several times as many the wiring paths as the through holes can be passed through the core substrate. Also, since the via hole provided right on the through hole consists of a plurality of wiring paths, several times as many the wiring paths as the via holes can be passed through the interlayer resin insulating layers. This makes it possible to provide wirings on the multilayer build-up wiring board with high concentration. Besides, due to the fact that via holes are formed right on the through holes, the wiring length becomes shortened and it is possible to deal with the demand of providing a high-speed multilayer build-up wiring board.
- a multilayer build-up wiring board having a multilayer wiring layer, wherein interlayer resin insulating layers and conductor layers are alternately provided and the conductor layers are connected to each other by via holes, the multilayer wiring layer formed on both sides of a core substrate, conductor layers of the both sides of said core substrate electrically connected to one another by through holes formed in the core substrate, is characterized in that
- the multilayer build-up wiring board recited in claim 12 is characterized in that filler is filled in the through holes provided in the core substrate, the conductor layer for covering the exposed surface of the filler from the through holes is formed and the via hole is connected to the conductor layer, thereby ensuring the connection between the build-up wiring layers and the through holes.
- the regions right on the through holes function as inner layer pads, thereby eliminating a dead space.
- the land of the through hole can be formed into a complete round.
- the arrangement concentration of the through holes provided in the multilayer core substrate can enhance, the number of through holes can be increased, and the signal lines of the build-up wiring layers at the back side can be connected to the build-up layers on the front side through the through holes.
- the high concentration of the multilayer build-up wiring boards can be attained by arranging a plurality of wiring paths in each of the increased number of through via holes and by arranging a plurality of the wiring paths in each of the via holes.
- the filler filled into the through holes preferably consists of metal particles and thermosetting or thermoplastic resin.
- the filler preferably consists of metal particles, thermosetting resin and a hardening agent, or consists of metal particles and thermoplastic resin. Solvent may be added thereto if required. Since the filler contain metal particles, the metal particles are exposed by sanding the surface thereof and the plated film of a conductor layer formed on the filler is integrated with the filler through the metal particles. Thus, even under strict conditions of high temperature and high humidity such as a PCT (pressure cooker test), the filler is peeled off less frequently at the interface with the conductor layer. In addition, the filler of this type is filled in the through holes each having a metal film formed on a wall surface thereof, so that the migration of metal ions does not occur.
- metal particles copper, gold, silver, aluminum, nickel, titanium, chromium, tin/lead, palladium, platinum and the like may be used.
- the diameter of a metal particle is preferably 0.1 to 50 ⁇ m. The reason is as follows. If the diameter is less than 0.1 ⁇ m, the copper surface is oxidized and with wetness resin deteriorates. If the diameter exceeds 50 ⁇ m, printing property deteriorates.
- the compounding quantity of the metal particles is preferably 30 to 90 wt %. If it is less than 30 wt %, the adhesion of the cover plating deteriorates and if it exceeds 90 wt %, printing property deteriorates.
- epoxy resin such as bisphenol A resin and bisphenol F resin, phenol resin, polyimide resin, fluorine-contained resin such as polytetrafluoroethylene (PTFE), bismaleimide/triazine (BT) resin, FEP, PFA, PPS, PEN, PES, nylon, aramid, PEEK, PEKK, PET and the like can be used.
- PTFE polytetrafluoroethylene
- BT bismaleimide/triazine
- an imidazole hardening agent As for the hardening agent, an imidazole hardening agent, a phenol hardening agent, an amine hardening agent and the like can be used.
- NMP normal methyl pyrrolidone
- DMDG diethylene glycol dimethyl ether
- glycerol water, 1-, 2- or 3-cyclohexanol, cyclohexanone, methyl cellosolve, methyl cellosolve acetate, methanol, ethanol, butanol, propanol, and the like
- solvent normal methyl pyrrolidone
- DMDG diethylene glycol dimethyl ether
- glycerol water
- 1-, 2- or 3-cyclohexanol cyclohexanone
- methyl cellosolve methyl cellosolve acetate
- methanol ethanol
- butanol propanol
- the filler is preferably non-conductive. This is because non-conductor filler has low hardening/contraction rate and the filler is peeled off less frequently from the conductor layer or via hole.
- a wiring board recited in claim 13 having a conductor circuit including a conductor layer of two-layer structure in which a second metal film, thinner than a first metal film is provided on said first metal film, is characterized in that
- a multilayer build-up wiring board recited in claim 14 having a structure in which at least one resin insulating layer and at least one conductor circuit are formed on a resin substrate, characterized in that
- the sides of the second metal film formed on the first metal film protrude outside compared with those of the first metal. Owing to this, if a resin insulating layer is formed on these conductor layers and temperature change and the like occurs due to this protruding structure, stress does not concentrate on the corners of the conductor layer, with the result that it is possible to prevent cracks from occurring to the resin insulating layer.
- FIGS. 1A , 1 B, 1 C and 1 D show manufacturing steps of a multilayer build-up wiring board in the first embodiment according to the present invention
- FIGS. 2E , 2 F, 2 G and 2 H show manufacturing steps of the multilayer build-up wiring board in the first embodiment according to the present invention
- FIGS. 3I , 3 J, 3 K and 3 L show manufacturing steps of the multilayer build-up wiring board in the first embodiment according to the present invention
- FIGS. 4M , 4 N and 4 O show manufacturing steps of the multilayer build-up wiring board in the first embodiment according to the present invention
- FIGS. 5P and 5Q show manufacturing steps of the multilayer build-up wiring board in the first embodiment according to the present invention
- FIG. 6 is a cross-sectional view of the multilayer build-up wiring board in the first embodiment according to the present invention.
- FIG. 7A is a cross-sectional view taken along line A-A of FIG. 6
- FIG. 7B is a cross-sectional view taken along line B-B;
- FIG. 8A is a cross-sectional view of a multilayer build-up wiring board in an experimental example according to the present invention
- FIGS. 8B and 8C are explanatory views for describing the arrangement of mesh holes
- FIG. 9A is a cross-sectional view of a multilayer build-up wiring board in the first comparison example
- FIG. 9B is an explanatory view showing the arrangement of mesh holes in the comparison example
- FIG. 9C is a plan view of a plain layer of a conventional technique
- FIG. 10 is a graph showing insulation tests for the interlayer resin insulating films of the multilayer build-up wiring boards in the experimental example and the first comparison example;
- FIGS. 11A , 11 B, 11 C and 11 D show manufacturing steps of a multilayer build-up wiring board in the second embodiment according to the present invention
- FIGS. 12E , 12 F, 12 G and 12 H show manufacturing steps of the multilayer build-up wiring board in the second embodiment according to the present invention
- FIGS. 13I , 13 J, 13 K and 13 L show manufacturing steps of the multilayer build-up wiring board in the second embodiment according to the present invention
- FIGS. 14M , 14 N, 14 O and 14 P show manufacturing steps of the multilayer build-up wiring board in the second embodiment according to the present invention
- FIGS. 15Q , 15 R and 15 S show manufacturing steps of the multilayer build-up wiring board in the second embodiment according to the present invention
- FIG. 16 is a cross-sectional view of the multilayer build-up wiring board in the second embodiment according to the present invention.
- FIG. 17 is a cross-sectional view of the multilayer build-up wiring board in the second embodiment according to the present invention.
- FIG. 18A is a cross-sectional view taken along line D-D of FIG. 17
- FIG. 18B is an enlarged view of the mesh hole shown in FIG. 18A
- FIG. 18C is an enlarged view of a mesh hole in a modified example
- FIG. 19 is a cross-sectional view of a multilayer build-up wiring board in the first modified example of the second embodiment
- FIG. 20A is a cross-sectional view taken along line F-F of FIG. 19
- FIG. 20B is an enlarged view of the mesh hole shown in FIG. 20A
- FIG. 20C is an enlarged view of a mesh hole in a modified example
- FIG. 21A is a plan view of a plain layer of a multilayer build-up wiring board in the second modified example of the second embodiment and FIG. 21B is an enlarged view of a modified example of a mesh hole shown in FIG. 21A ;
- FIG. 22A is a plan view of a plain layer of a multilayer build-up wiring board in the third modified example of the second embodiment
- FIG. 22B is a cross-sectional view of the multilayer build-up wiring board
- FIG. 22C is a cross-sectional view of a multilayer build-up wiring board in a modified example
- FIG. 23 is a plan view of the plain layer of a multilayer build-up wiring board in a conventional technique
- FIGS. 24A , 24 B, 24 C, 24 D and 24 E show manufacturing steps of a multilayer build-up wiring board in the third embodiment according to the present invention
- FIGS. 25F , 25 G, 25 H, 25 I and 25 J show manufacturing steps of the multilayer build-up wiring board in the third embodiment according to the present invention.
- FIGS. 26K , 26 L, 26 M, 26 N and 26 O show manufacturing steps of the multilayer build-up wiring board in the third embodiment according to the present invention
- FIGS. 27P , 27 Q, 27 R and 27 S show manufacturing steps of the multilayer build-up wiring board in the third embodiment according to the present invention
- FIGS. 28T , 28 U and 28 V show manufacturing steps of the multilayer build-up wiring board in the third embodiment according to the present invention.
- FIGS. 29W , 29 X and 29 Y show manufacturing steps of the multilayer build-up wiring board in the third embodiment according to the present invention.
- FIGS. 30 ZA, 30 ZB and 30 ZC show manufacturing steps of the multilayer build-up wiring board in the third embodiment according to the present invention.
- FIG. 31 is a cross-sectional view of the multilayer build-up wiring board in the third embodiment according to the present invention.
- FIG. 32 is a cross-sectional view showing a state in which an IC chip is mounted on the multilayer build-up wiring board in the third embodiment according to the present invention.
- FIG. 33A is a cross-sectional view taken along line A-A of FIG. 31
- FIG. 33B is an explanatory view of the multilayer build-up wiring board in the third embodiment
- FIG. 33C is a cross-sectional view taken along line C-C of FIG. 31
- FIG. 33D is an explanatory view of a through hole of the multilayer build-up wiring board in the third embodiment
- FIGS. 34A and 34B are cross-sectional views of a multilayer build-up wiring board in the first modified example of the third embodiment
- FIG. 35A is a cross-sectional view of the multilayer build-up wiring board in the first modified example of the third embodiment and FIG. 35B is a plan view of through holes and lands in the first modified example of the third embodiment;
- FIG. 36 is a cross-sectional view typically showing a wiring board in the fourth embodiment according to the present invention
- FIG. 36A is a cross sectional view showing a wiring board having top roughened surface
- FIGS. 37A , 37 B, 37 C, 37 D and 37 E are cross-sectional views showing an example of manufacturing steps of the wiring board in the fourth embodiment
- FIGS. 38A , 38 B, 38 C and 38 D are cross-sectional views showing part of manufacturing steps of the multilayer build-up wiring board in the fourth embodiment
- FIGS. 39A , 39 B, 39 C and 39 D are cross-sectional views showing part of manufacturing steps of the multilayer build-up wiring board in the fourth embodiment
- FIGS. 40A , 40 B, 40 C and 40 D are cross-sectional views showing part of manufacturing steps of the multilayer build-up wiring board in the fourth embodiment
- FIGS. 41A , 41 B, 41 C and 41 D are cross-sectional views showing part of manufacturing steps of the multilayer build-up wiring board in the fourth embodiment
- FIGS. 42A , 42 B and 42 C are cross-sectional view showing part of manufacturing steps of the multilayer build-up wiring board in the fourth embodiment.
- FIGS. 43A and 43B show microphotographs of an optical microscope showing the cross section of the multilayer build-up wiring board obtained in the fourth embodiment.
- a plain layer 35 for forming a ground layer is formed on each of the front and back sides of a core substrate 30 .
- Build-up wiring layers 80 A and 80 B are formed on the front-side plain layer 35 and the back-side plain layer 35 , respectively.
- the build-up layer 80 A consists of an interlayer resin insulating layer 50 which includes a via hole 60 , a conductor layer 58 and a plain layer 59 serving as a power layer and an interlayer resin insulating layer 150 which includes a via hole 160 and a conductor circuit 158 .
- the build-up wiring layer 80 B consists of an interlayer resin insulating layer 50 which includes a via hole 60 and a conductor circuit 58 and an interlayer insulating layer 150 which includes a via hole 160 and a conductor circuit 158 .
- solder bump 76 U for connecting to a land of an integrated circuit chip (not shown) is provided.
- the solder bump 76 U is connected to a through hole 36 through the via holes 160 and 60 .
- a solder bump 76 D for connecting to a land of a daughter board (not shown) is provided.
- the solder bump 76 D is connected to the through hole 36 through the via holes 160 and 60 .
- FIG. 7A is a cross-sectional view taken along line A-A of FIG. 6 , showing the plane of the plain layer 59 formed on the surface of the interlayer resin insulating layer 50 .
- FIG. 7B is a cross-sectional view taken along line B-B of FIG. 6 , showing the plane of the plain layer 35 formed on the surface of the core substrate 30 .
- mesh holes 59 a of 20 ⁇ m in diameter are formed at every pitch P (500 ⁇ m) in the plain layer 59 on the surface of the interlayer resin insulating layer 50 .
- P 500 ⁇ m
- mesh holes 35 a of 200 ⁇ m in diameter are formed at every pitch P (500 ⁇ m) in the plain layer 35 on the surface of the core substrate 30 .
- Mesh holes 35 a are also formed on the back side of the core substrate 30 although not shown.
- the mesh holes 35 a and 35 b in the plain layers 35 , 35 on both sides of the core substrate 30 are arranged to completely overlay on the mesh holes 59 a in the plain layer 59 of the interlayer resin insulating layer 50 as shown in FIG. 6 . This can prevent the insulating property of the interlayer resin insulating layer 50 from lowering.
- a resin composition substance is obtained by stirring and mixing 35 weight parts of a resin liquid, 3.15 weight parts of a photosensitive monomer (manufactured by TO-A GOSEI, Alonix M315), 0.5 weight part of an antifoaming agent (manufactured by SAN-NOPUKO, S-65) and 3.6 weight parts of NMP.
- a resin liquid 25% of a cresol novolak type epoxy resin (manufactured by NIHON KAYAKU, molecular weight 2500) and 80 wt % of an acrylic substance in concentration are dissolved to DMDG.
- a resin composition substance is obtained by mixing 12 weight parts of polyether sulfone (PES), 7.2 weight parts of epoxy resin particles (manufactured by SANYOKASEI, polymer pole) having an average particle diameter of 1.0 ⁇ m, and 3.09 weight parts of epoxy resin particles having an average particle diameter of 0.5 ⁇ m, and then adding 30 weight parts of NMP to the mixed material and stirring and mixing these materials by a beads mill.
- PES polyether sulfone
- epoxy resin particles manufactured by SANYOKASEI, polymer pole
- a hardening agent composition substance is obtained by stirring and mixing 2 weight parts of an imidazole hardening agent (manufactured by SHIKOKU KASEI, 2E4MZ-CN), 2 weight parts of an optical starting agent (manufactured by CHIBAGAIGI, Irugacure I-907), 0.2 weight part of a photosensitizer (manufactured by NIHON KAYAKU, DETX-S), and 1.5 weight parts of NMP.
- an imidazole hardening agent manufactured by SHIKOKU KASEI, 2E4MZ-CN
- an optical starting agent manufactured by CHIBAGAIGI, Irugacure I-907
- a photosensitizer manufactured by NIHON KAYAKU, DETX-S
- a resin composition substance is obtained by stirring and mixing 35 weight parts of a resin liquid, 4 weight parts of a photosensitive monomer (manufactured by TO-AGOSEI, Alonix M315), 0.5 weight part of an antifoaming agent (manufactured by SAN-NOPUKO, S-65) and 3.6 weight parts of NMP.
- a resin liquid 25% of a cresol novolak type epoxy resin (manufactured by NIHON KAYAKU, molecular weight 2500) and 80 wt % of an acrylic substance in concentration are dissolved to DMDG.
- a resin composition substance is obtained by mixing 12 weight parts of polyether sulfone (PES) and 14.49 weight parts of epoxy resin particles (manufactured by SANYO KASEI, polymer pole) having an average particle diameter of 0.5 ⁇ m, and then adding 30 weight parts of NMP to the mixed material and stirring and mixing these materials by a beads mill.
- PES polyether sulfone
- epoxy resin particles manufactured by SANYO KASEI, polymer pole
- a hardening agent composition substance is obtained by stirring and mixing 2 weight parts of an imidazole hardening agent (manufactured by SHIKOKU KASEI, 2E4MZ-CN), 2 weight parts of an optical starting agent (manufactured by CHIBAGAIGI, Irugacure I-907), 0.2 weight part of a photosensitizer (manufactured by NIHON KAYAKU, DETX-S), and 1.5 weight parts of NMP.
- an imidazole hardening agent manufactured by SHIKOKU KASEI, 2E4MZ-CN
- an optical starting agent manufactured by CHIBAGAIGI, Irugacure I-907
- a photosensitizer manufactured by NIHON KAYAKU, DETX-S
- Solder resist composition is obtained by mixing 46.67 g of photosensitive oligomer (molecular weight 4000) obtained by acrylic-modifying 50% of epoxy groups of 60 percentage by weight of cresol novolac dissolved into DMDG of 50% epoxy resin (Nippon Kayaku); 15.0 g of 80 percentage by weight of bisphenol A type epoxy resin (Yuka Shell, Epikote 1001) dissolved into methyl ethyl ketone; 1.6 g of imidazole hardener (Shikoku Chemicals, 2E4MZ-CN); 3 g of multivalent acrylic monomer (Nippon Kayaku, R604) which is photoreceptive monomer; 1.5 g of the same multivalent acrylic monomer (KYOEISHA CHEMICAL, DPE6A); 0.71 g of a scattering anti-foaming agent (SANNOPCO, S-65); then adding 2 g of benzophenone (KANTO CHEMICAL) used as a photo-initiator; and 0.2 g of Michler's
- the viscosity is measured by B-type measurement (TOKYO measurement DVL-B type).
- a rotator No. 4 was used in 60 rpm, and a rotator No.3 was used in 6 rpm.
- the manufacturing steps for the multilayer build-up wiring board in the first embodiment will be described with reference to FIGS. 1 through 6 .
- the multilayer build-up wiring board is formed by means of the semi-additive method.
- a copper-clad laminate 30 A including a substrate 30 of glass epoxy resin or BT (Bismaleimide/Triazine) resin and having a 18 ⁇ m copper foil 32 laminated on both sides thereof is used as a starting material.
- the copper-clad laminate 30 A is drilled and subjected to electroless plating and pattern-etching, thereby forming through holes 36 and plain layers 35 and forming a core substrate 30 shown in FIG. 1B .
- the mesh holes 35 a are formed in each plain layer 35 .
- the substrate 30 having the plain layers 35 and the through hole 36 formed thereon is washed and dried.
- roughened layers 38 are provided on the surfaces of the plain layers 35 and the through holes 36 by oxidizing-reducing using an oxidizing (blackening) bath of NaOH (10 g/l), NaCl (40 g/l) and Na 3 PO 4 (6 g/l) and a reducing bath of NaOH (10 g/l) and NaBH 4 (6 g/l) (see FIG. 1C ).
- oxidizing (blackening) bath of NaOH (10 g/l), NaCl (40 g/l) and Na 3 PO 4 (6 g/l) and a reducing bath of NaOH (10 g/l) and NaBH 4 (6 g/l) see FIG. 1C .
- filling resin obtained in (3) above is coated on the both sides of the substrate 30 using a roll coater within 24 hours after preparation, filled into the mesh holes 35 a of the conductor circuits (plain layers) 35 and into the through holes 36 and dried at a temperature of 70° C. for 20 minutes.
- filling resin 40 is filled into the mesh holes 35 a and the through holes 36 and dried at a temperature of 70° C. for 20 minutes (see FIG. 1D ).
- the one side of the substrate which has been subjected to the treatment of (4) above is sanded by belt sanding using a #600 belt sand paper (manufactured by Sankyo Rikagaku Co., Ltd.) so that the filling resin 40 does not remain on the surfaces of the plain layers 35 and the surfaces of the land 36 a of the through hole 36 .
- the one side of the substrate is subjected to buffing. A series of these sanding steps are effected for the other side of the substrate, as well (See FIG. 2E ).
- the surface layer portion of the filling resin 40 filled in the through holes 36 and the like and the roughened layer 38 on the upper surface of the plain layers 35 are removed to thereby smooth the both sides of the substrate.
- a wiring substrate is obtained wherein the filling resin 40 and the sides of the plain layers 35 are fixedly attached to each other through the roughened layers 38 and the inner wall surface of the through hole 36 and the filling resin 40 are fixedly attached to each other through the roughened layers 38 .
- the surface of the filling resin 40 is made flush with that of the surfaces of the plain layers 35 .
- the substrate 30 on which the plain layer 35 has been formed is subjected to alkali degreasing and soft-etching. Then, the substrate 30 is treated by a catalytic solution of palladium chloride and organic acid to add a Pd catalyst to the substrate 30 .
- the substrate is submerged in an electroless plating liquid consisting of 3.2 ⁇ 10 ⁇ 2 mol/l of copper sulfate, 3.9 ⁇ 10 ⁇ 3 mol/l of nickel sulfate, 5.4 ⁇ 10 ⁇ 2 mol/l of a complexing agent, 3.3 ⁇ 10 ⁇ 1 mol/l of sodium hypophosphite, 5.0 ⁇ 10 ⁇ 1 mol/l of boracic acid and 0.1 g/l of surfactant (manufactured by Nisshin Kagaku, Surfeal465) and having a pH of 9.
- an electroless plating liquid consisting of 3.2 ⁇ 10 ⁇ 2 mol/l of copper sulfate, 3.9 ⁇ 10 ⁇ 3 mol/l of nickel sulfate, 5.4 ⁇ 10 ⁇ 2 mol/l of a complexing agent, 3.3 ⁇ 10 ⁇ 1 mol/l of sodium hypophosphite, 5.0 ⁇ 10 ⁇ 1 mol/l of boracic acid and 0.1
- the substrate After one minute of submergence, the substrate is longitudinally and transversely vibrated once for four seconds to thereby provide a coated layer and roughened layer 42 of a needle alloy of Cu—Ni—P on the surface of the plain layer 35 and that of the land 36 a of the through hole 36 (see FIG. 2F ).
- Cu—Sn displacement reaction is conducted under conditions of 0.1 mol/l of tin fluoborate, 1.0 mol/l of thiourea, a temperature of 35° C. and a pH of 1.2 to thereby provide an Sn layer (not shown) of a thickness of 0.3 ⁇ m on the surface of the roughened layer.
- composition of material for preparing an interlayer resin insulating agent described in B is agitated to adjust the viscosity thereof to 1.5 Pa ⁇ s to thereby obtain an interlayer resin insulating agent (for a lower layer).
- composition of material for preparing an electroless plating adhesive agent described in A is agitated to adjust the viscosity thereof to 7 Pa ⁇ s to thereby obtain an electroless plating adhesive agent solution (for an upper layer).
- the interlayer resin insulating agent (for an lower layer) 44 of a viscosity of 1.5 Pa ⁇ s obtained in (7) above is coated on the both sides of the substrate of (6) by a roll coater within 24 hours after preparing the agent and left horizontally for 20 minutes. Thereafter, the agent is dried (or pre-baked) at 60° C. for 30 minutes.
- the photosensitive adhesive agent solution (for an upper layer) 46 of a viscosity of 7 Pa ⁇ s obtained in (7) above is coated on the both sides of the substrate of (6) within 24 hours after preparing the agent and left horizontally for 20 minutes. Thereafter, the agent is dried (or pre-baked) at 60° C. for 30 minutes.
- adhesive agent layers 50 ⁇ of a thickness of 35 ⁇ m are formed (see FIG. 2G ).
- a photo mask film (not shown) on which a 85 ⁇ m ⁇ black circle had been printed is closely contacted with the both sides of the substrate 30 on which the adhesive agent layers have been formed in (8) above and exposed at 500 mJ/cm 2 by an extra-high pressure mercury lamp.
- the resultant film is subjected to spray-development with a DMTG solution.
- the substrate is further exposed at 3000 mJ/cm 2 by the extra-high pressure mercury lamp, and heated (or post-baked) at 100° C. for one hour, at 120° C. for one hour and at 150° C. for three hours.
- interlayer resin insulating layers (two-layer structure) 50 each having a thickness of 35 ⁇ m and having 85 ⁇ m ⁇ openings (via hole formation openings) 48 excellent in dimensional accuracy and corresponding to a photo mask film are formed (see FIG. 2H ).
- a tin plated layer (not shown) is partially exposed to the openings 48 which become via holes.
- the substrate 30 in which the openings 48 have been formed, is submerged in chromic acid for 19 minutes to dissolve and remove epoxy resin particles present on the surfaces of the interlayer resin insulating layers 50 , thereby roughening the surfaces of the interlayer resin insulating layers 50 (see FIG. 3I ).
- the substrate is submerged in a neutralizing solution (manufactured by Shipley Far East) and washed.
- a palladium catalyst manufactured by Atotec
- the substrate 30 is submerged in an electroless copper plating solution which composition is shown below to thereby form electroless plated films 52 of a thickness of 0.6 ⁇ m on the entire surface (see FIG. 3J ).
- the electroless plated films 52 under the plating resist are etched by a mixture liquid of sulfuric acid and peroxide and dissolved, thereby forming conductor circuits 58 , plain layers 59 and via holes 60 each consisting of the electroless copper plated film 52 and the electrolytic copper plated film 60 and having a thickness of 18 ⁇ m ( FIG. 4M ).
- the mesh holes 59 a are formed in the plain layers 59 and the holes 59 a are formed to overlay the mesh holes 35 a of the plain layers 35 formed on both sides of the core substrate 30 .
- the above-stated solder resist composition, as described in D. above of a thickness of 45 ⁇ m is coated on the both sides of the substrate 30 obtained in (16) above. Next, drying treatment at 70° C. for 20 minutes and that at 70° C. for 30 minutes are conducted. Thereafter, a photo mask film (not shown) of a thickness of 5 mm, on which a circle pattern (or mask pattern) is written, is mounted on the substrate while being closely contacted therewith, exposed to ultraviolet rays of 1000 mJ/cm 2 and subjected to DMTG development treatment. Further, heating treatment is conducted at 100° C. for one hour, 120° C. for one hour and 150° C.
- a nickel plating layer 72 having 5 ⁇ m in thickness is formed in the opening portions 71 .
- this substrate is dipped for 7 minutes and 20 seconds into an electroless gold plating liquid constructed by potassium gold cyanide 4.1 ⁇ 10 ⁇ 2 mol/l, ammonium chloride 1.87 ⁇ 10 ⁇ 1 mol/l, sodium citrate 1.16 ⁇ 10 ⁇ 1 mol/l and sodium hypophosphite 1.7 ⁇ 10 ⁇ 1 mol/l in a condition of 80° C.
- an electroless gold plating liquid constructed by potassium gold cyanide 4.1 ⁇ 10 ⁇ 2 mol/l, ammonium chloride 1.87 ⁇ 10 ⁇ 1 mol/l, sodium citrate 1.16 ⁇ 10 ⁇ 1 mol/l and sodium hypophosphite 1.7 ⁇ 10 ⁇ 1 mol/l in a condition of 80° C.
- a gold plating layer 74 having 0.03 ⁇ m in thickness is formed on the nickel plating layer so that a soldering pad 75 is formed in the via hole 160 and the not shown conducting circuit (refer FIG. 5(Q) ).
- Solder bumps (solder bodies) 76 U, 76 D are formed in the opening portions 71 of the solder resist layers 70 , respectively by printing a solder paste and conducting reflow at 200° C. and a multilayer build-up wiring board 10 is formed (see FIG. 6 ).
- FIG. 8A shows a cross-section of a multilayer build-up wiring board in the experimental example according to the present invention.
- the multilayer build-up wiring board in this example is formed in the same manner as that of the multilayer build-up wiring board 10 in the above-described first embodiment.
- the through hole is formed in the core substrate in the first embodiment, whereas no through hole is formed in this experimental example.
- a plain layer 135 is formed on each of the upper and lower surfaces of the core substrate 130 and plain layers 179 and 189 are formed on each of the interlayer resin insulating layers 170 and interlayer resin insulating layers 180 as outermost layers on the upper and lower surfaces.
- FIG. 8B shows how a mesh hole 179 a in the interlayer resin insulating layer 170 relates to a mesh hole 189 a in the plain layer 189 .
- the mesh holes 135 a of the plain layers 135 , the mesh holes 179 a of the plain layers 179 and the mesh holes 189 a of the plain layers 189 on the core substrate 130 are formed to overlay one another.
- the mesh holes of a diameter of 250 ⁇ m are arranged at a pitch of 550 ⁇ m.
- FIG. 9A shows the cross section of a multilayer build-up wiring board in the first comparison example
- FIG. 9B shows how a mesh hole 179 a in plain layers 179 relates to a mesh hole 189 a in plain layer 189 of the multilayer build-up wiring board in the comparison example.
- the multilayer build-up wiring board in the first comparison example is manufactured in exactly the same manner as that in the above experimental example.
- the mesh holes 135 a in the plain layers 135 , the mesh holes 179 a in the plain layers 179 and the mesh holes 189 a in the plain layers 189 on the core substrate 130 are formed not to overlay one another.
- An STEC test was conducted as the insulation test.
- STEC test ten multilayer build-up wiring boards were kept under the conditions of 121° C., 100% RH and 2.1 atm for 336 hours and insulation resistance between the interlayer resin insulating layers was measured.
- the number on the vertical axis indicates a multiplier and the horizontal axis indicates the pitch ( ⁇ m) between the mesh holes and the diameter ( ⁇ m) of the mesh holes.
- the position of the mesh hole and the insulation resistance of the interlayer resin insulating layer correlate to each other. If the mesh holes are arranged to overlay one another as shown in the experimental example, it is possible to increase the insulation resistance of the interlayer resin insulating layer.
- FIG. 8C shows the positional relationship between the mesh holes 189 a in the plain layer 189 formed on the outermost interlayer resin insulating layer 180 and the mesh holes 179 a in the plain layer 179 formed on the interlayer resin insulating layer 170 .
- the positional errors of about 35 ⁇ m are generated between the upper and lower mesh holes 189 a and 179 a . Even if a positional error of about 35 ⁇ m occurs, the insulation resistance of the interlayer resin insulating layer can be increased by setting the diameter of the mesh hole at not less than 70 ⁇ m to overlay at least part of the mesh holes with one another.
- the mesh holes in the upper and lower plain layers are formed such that at least part of them overlay one another, thereby preventing the insulation resistance of the interlayer resin insulating layer from lowering.
- FIG. 16 is a cross-sectional view of a multilayer printed wiring board 10 before an IC chip is mounted thereon.
- FIG. 17 shows a state in which an IC chip 90 is mounted on the multilayer printed wiring board 10 shown in FIG. 10 and the board 10 is attached onto a daughter board 94 .
- through holes 36 are formed in a core substrate 30 .
- a plain layer 34 U which serves as a power layer, is formed on the surface of the core substrate 30 (IC chip side) and a plain layer 34 D, which serves as a ground layer, is formed on the back surface thereof (daughter board side).
- Lower interlayer resin insulating layers 50 on which via holes 60 and conductor circuits 58 are formed, are arranged on the plain layers 34 U and 34 D, respectively.
- Upper interlayer resin insulating layers 150 on which via holes 160 and conductor circuits 158 ( FIG. 16 shows only the back surface side) are formed, are arranged on the lower interlayer resin insulating layers 50 , respectively.
- solder bumps 76 U for connecting to the lands 92 of the IC chip 90 , are provided on the upper surface of the multilayer printed wiring board. Each of the solder bumps 76 U is connected to the through hole 36 through the via hole 160 and the via hole 60 . Solder bumps 76 D for connecting to the lands 96 of the daughter board 94 , are provided on the lower surface of the multilayer printed wiring board 10 . Each of the solder bumps 76 D is connected to the through hole 36 through the via hole 160 and the via hole 60 .
- FIG. 18 is a cross-sectional view taken along line D-D of FIG. 17 , showing the plane of the plain surface 34 U formed on the surface of the core substrate 30 .
- the cross section taken along line E-E of FIG. 18 corresponds to FIG. 17 .
- mesh holes 35 a each having a diameter of 250 ⁇ m are formed outside of a region C (to be referred to as ‘chip mount region’ hereinafter) facing a region on which IC chip 90 is mounted through the interlayer resin insulating layer at intervals of pitch P (560 ⁇ m).
- Lageniform mesh holes 35 b are formed inside the chip mount region C.
- FIG. 18B shows an enlarged mesh hole 35 b .
- the land 36 a of the through hole 36 and the via hole (bottom of the via hole) 60 a are formed with gaps K of 5 to 50 ⁇ m.
- the land 36 a is connected to a pad, to which the via hole is connected, through the conductor circuit 34 c.
- mesh holes 35 b are formed in the chip mount region C of the plain layer 34 U and the land 36 a of the through hole 36 and the pad 60 a , to which the via hole is connected, are provided in each of the mesh holes 35 b . Due to this, the interlayer resin insulating layer 50 formed above the plain layer 34 U and the resin core substrate 30 formed below the plain layer 34 U can be directly contacted with each other through the gaps K of the mesh holes 35 b provided on the outer periphery of the land 36 a and the pad 60 a to which the via hole is connected, thereby making it possible to increase bonding property.
- gas containing moisture and the like absorbed by the interlayer resin insulating layers 50 and the core substrate 30 can be exhaled through the gaps K of the mesh holes 35 b provided on the outer periphery of the land 36 a and the pad 60 a to which the via hole is connected. Due to this, it is possible to increase the insulating properties of the interlayer resin insulating layers 50 and the core substrate 30 and to prevent the interlayer resin insulating layers from peeling off. Further, since the land 36 a and the pad 60 a to which the via hole is connected are formed in each of the mesh holes 35 b in the chip mount region C, irregular portions are not formed and the chip mount region C can be made flat.
- the holes 35 a are left as recessed portions.
- the land 36 a and the pad 60 a are provided in each of the holes, so that the chip mount region C can be made flat. It is noted that the land 36 a and the pad to which the via hole is connected may be integrally formed into lageniform, round-bellied or teardrop shape as shown in FIG. 18C .
- the multilayer build-up wiring board is formed by means of the semi-additive method.
- a copper-clad laminate 30 A including a substrate 30 of glass epoxy resin or BT (Bismaleimide/Triazine) resin and having a 18 ⁇ m copper foil 32 laminated on both sides thereof is used as a starting material.
- the copper-clad laminate 30 A is drilled and subjected to electroless plating and pattern-etching, thereby forming a through hole 36 and plain layers 34 U and 34 D and forming a core substrate 30 shown in FIG. 11B .
- mesh holes 35 a and 35 b are formed in the plain layer 34 U and 34 D, and the land 36 a of a through hole 36 , a conductor circuit 34 c and the bottom 60 a of the via hole are provided in each of the mesh holes 35 b in the chip mount region C.
- the substrate 30 having the plain layers 34 and the through holes 36 formed thereon are washed and dried.
- roughened layers 38 are provided on the surfaces of the plain layers 34 U, 34 D and of through holes 36 by oxidizing-reducing using an oxidizing (blackening) bath of NaOH (10 g/l), NaClO 2 (40 g/l) and Na 3 PO 4 (6 g/l) and a reducing bath of NaOH (10 g/l) and NaBH 4 (6 g/l) (see FIG. 11C ).
- oxidizing (blackening) bath of NaOH (10 g/l), NaClO 2 (40 g/l) and Na 3 PO 4 (6 g/l) and a reducing bath of NaOH (10 g/l) and NaBH 4 (6 g/l) see FIG. 11C .
- the filling resin 40 obtained in (3) above is coated on the both sides of the substrate 30 using a roll coater within 24 hours after preparation, filled into the mesh holes 35 a and 35 b of the conductor circuits (plain layer) 34 and into the through holes 36 and dried at a temperature of 70° C. for 20 minutes.
- the filling resin 40 is filled into the mesh holes 35 a and the through holes 36 and dried at a temperature of 70° C. for 20 minutes (see FIG. 11D ).
- the substrate 30 which has been subjected to the treatment of (4) above, is sanded (see FIG. 12E ). Next, heating treatment is conducted to harden the filling resin 40 .
- a coated layer and roughened layer 42 of a needle alloy of Cu—Ni—P are provided on the surfaces of the plain layers 34 U, 34 D, the lands 36 a of the through holes 36 and the bottoms 60 a of the via holes as in the case of the first embodiment (see FIG. 12F ).
- Cu—Sn displacement reaction is conducted under conditions of 0.1 mol/l of tin fluoborate, 1.0 mol/l of thiourea, a temperature of 35° C. and a pH of 1.2 to thereby provide an Sn layer of a thickness of 0.3 ⁇ m on the surface of the roughened layer (not shown).
- the same composition of material for preparing an electroless plating adhesive agent as that in the first embodiment is agitated to adjust the viscosity thereof to 7 Pa ⁇ s to thereby obtain an electroless plating adhesive agent solution (for an upper layer).
- the interlayer resin insulating agent (for lower layer) 44 obtained in (7) is coated on the both sides of the substrate of (6), the photosensitive adhesive agent solution (for an upper layer) 46 obtained in (7) above is coated and an adhesive agent layers 50 a of a thickness of 35 ⁇ m are formed (see FIG. 12G ).
- a photo mask film 51 ( FIG. 13H ) on which a 85 ⁇ m ⁇ black circle 51 a is printed is in close contact on the both sides of the substrate 30 on which the adhesive agent layer has been formed in (8) above, exposed and developed to thereby form interlayer resin insulating layers (two-layer structure) 50 having a thickness of 35 ⁇ m and 85 ⁇ m ⁇ openings (via hole formation openings) 48 (see FIG. 13I ).
- a tin plated layer (not shown) is partially exposed to the openings 48 which become via holes.
- the substrate 30 in which the openings 48 are formed, is submerged in chromic acid for 19 minutes to dissolve and remove epoxy resin particles present on the surfaces of the interlayer resin insulating layers 50 , thereby roughening the surfaces of the interlayer resin insulating layers 50 (see FIG. 13J ). Thereafter, the substrate is submerged in a neutralizing solution (manufactured by Shipley Far East) and washed.
- a palladium catalyst (manufactured by Atotec) is added to the surface of the substrate 30 which has been subjected to roughening treatment in the step of (10) above, thereby providing catalyst nuclei on the surfaces of the interlayer insulating layers 50 . Thereafter, the substrate 30 is submerged in the same electroless copper plating solution as that in the first embodiment to thereby form electroless plated films 52 of a thickness of 0.6 ⁇ m on the entire surfaces (see FIG. 13K ) (12) A commercially available photosensitive dry film is put on each electroless copper plated film 52 formed in (11) above and a mask is mounted thereon.
- the film is exposed at 100 mJ/cm 2 and developed by 0.8% sodium carbonate, to thereby provide a plating resist 54 of a thickness of 15 ⁇ m (see FIG. 13L ) (13)
- electrolytic copper plating is conducted to portions on which no resist is formed under the same conditions as those in the first embodiment, to thereby form electrolytic copper plated films 56 of a thickness of 15 ⁇ m (see FIG. 14M ).
- solder resist layers thickness: 20 ⁇ m
- openings opening diameter: 200 ⁇ m
- soldering pad portions including a via hole and a via hole land
- nickel plated layers 72 are formed.
- Gold plated layers 74 of a thickness of 0.03 ⁇ m are formed on the nickel plated layers, respectively, thereby forming solder pads 75 on via holes 160 and conductor circuits 158 (only the back side shown) (see FIG. 15S ).
- Solder bumps (solder bodies) 76 U, 76 D are formed in the opening portions 71 of the solder resist layers 70 by printing solder paste and conducting reflow at 200° C., thereby completing a multilayer build-up wiring board 10 (see FIG. 16 ).
- the pads 92 of the IC chip 90 are correspondingly mounted on the solder bumps 76 U of the completed multilayer printed wiring board 10 . Then, reflow is conducted and the IC chip 90 is mounted on the pads 92 . Thereafter, an under-fill 88 is filled between the IC chip 90 and the multilayer printed wiring board 10 .
- the multilayer printed wiring board 10 on which the IC chip 90 is mounted is correspondingly mounted on bumps 96 of the daughter board 94 . Then, reflow is conducted and the board 10 is attached to the daughter board 94 . Thereafter, an under-fill 88 is filled between the multilayer printed wiring board 10 and the daughter board 94 .
- FIG. 19 is a cross-sectional view of a multilayer wiring board 110 in the first modified example.
- the plain layers 34 U and 34 D are provided on the both sides of the core substrate 30 , respectively.
- plain layers 58 U and 58 D are formed on the interlayer resin insulating layers 50 , respectively.
- conductor circuits 34 are formed on the front and back sides of the core substrate 30 , respectively and lower layer side interlayer resin insulating layers 50 are formed on the conductor circuits 34 , respectively.
- Plain layers 58 U and 58 D are formed on the lower layer side interlayer resin insulating layers 50 , respectively.
- the plain layer 58 on the surface side (IC chip side) is used as a power layer
- the plain layer 58 on the back surface side (daughter board side) is used as a ground layer.
- Upper interlayer resin insulating layers 150 are formed on the plain layers 58 U and 58 D, respectively. Via holes 160 and conductor circuits 158 are provided on each of the upper interlayer resin insulating layer 150 .
- FIG. 20A is a cross-sectional view taken along line F-F of FIG. 19 , showing the plane of the plain layer 58 U formed on the interlayer resin insulating layer 50 .
- the cross section G-G of FIG. 20A corresponds to FIG. 19 .
- mesh holes 59 a of a diameter of 200 ⁇ m are formed outside of a chip mount region C of the plain layer 58 U.
- Lageniform meshes 59 b are formed inside the chip mount region C.
- FIG. 20B shows an enlarged lageniform mesh 59 b .
- a via hole 60 formed in the interlayer insulating layer 50 and a pad (bottom of the via hole), to which a via hole formed in the interlayer resin insulating layer 150 is formed, are provided in each of the mesh holes 59 b with a gap K of several tens of microns provided. That is, the land 60 of the via hole and the pad 160 a , to which the via hole is connected, are formed integrally with each other.
- the meshes 59 b are formed in the chip mount region C of the plain layer 58 U and the via hole land 60 and the pad 160 a , to which the via hole is connected, are provided in each of the mesh holes 59 b . Due to this, the interlayer resin insulating layer 150 formed above the plain layer 58 U and the interlayer resin insulating layer 50 formed below the plain layer 58 U can be in direct contact to each other through the gaps K of the mesh holes 59 b provided on the outer periphery of the via hole land 60 and the pad 160 a , to which the via hole is connected, thereby making it possible to increase bonding property.
- gas containing moisture and the like absorbed by the interlayer resin insulating layers 150 and 50 can be exhaled through the gaps K of the mesh holes 59 b provided on the outer periphery of the via hole land 60 the pad 160 a , to which the via hole is connected. Due to this, it is possible to increase the insulating properties of the interlayer resin insulating layers 50 and 150 and to prevent the interlayer resin insulating layers from peeling off. Further, since the via hole land 60 and the pad 160 a , to which the via hole is connected, are formed inside each mesh hole 59 b in the chip mount region C, irregular portions are not formed and the chip mount region C can be formed flat. It is noted that the constricted part of the coupled portion between the via hole land 60 and the pad 160 a , to which the via hole is connected, may be eliminated and the mesh hole 59 b may be round-bellied shaped or teardrop shaped.
- FIG. 21 is a plan view showing a plain layer 34 U formed on the front surface of the core substrate.
- mesh holes 35 b in each of which the through land 36 a and the pad 60 to which the via hole is connected are provided, are formed in the chip mount region C.
- not only lageniform mesh holes 35 b but also circular mesh holes 35 c are provided in the chip mount region C, and a solid conductor layer 34 d is arranged in each mesh hole 35 C.
- the solid conductor layer 34 d may be connected to the plain layer 34 U around the layer 34 d at, at least one portion.
- mesh holes 35 c are formed in the chip mount region C of the plain layer 34 C and the solid conductor layer 34 d is provided in each of the mesh holes 35 c . Due to this, the interlayer resin insulating layer 50 provided above the plain layer 34 U and the resin core substrate 30 provided below the plain layer 34 U can be directly connected to each other through gaps of the mesh holes 35 C each provided on the peripheral portion of the solid conductor layer 34 d , thereby making it possible to increase bonding property.
- gas containing moisture or the like absorbed by the interlayer resin insulating layers 50 and the core substrate 30 can be exhaled through the gaps of the mesh holes 35 c provided around the slid conductor layers 34 d , so that the insulating properties of the interlayer resin insulating layers 50 and the core substrate 30 can be enhanced and the interlayer resin insulating layers can be prevented from peeling off. Further, since the solid conductor 34 d is formed in each of the mesh holes 35 c in the chip mount region C, no irregular portion is formed and the chip mount region C can be made flat.
- FIG. 22A is a plan view showing a plain layer 34 U formed on the front surface of a core substrate.
- mesh holes 35 b in each of which the through land 36 a and the pad 60 to which the via hole is connected are provided, are formed in the chip mount region C.
- circular mesh holes 35 d are formed in a chip mount region C and only a through hole land 36 a is provided in each of the mesh holes 35 d .
- FIG. 22B is a cross-sectional view of an interlayer resin insulating layer 50 and a core substrate 30 in the third modified example.
- a via hole 60 is formed right on the land 36 a of the through hole 36 formed in the core substrate 30 .
- mesh holes 35 d are formed in the chip mount region C of the plain layer 34 U and a land 36 a is provided in each of the mesh holes 35 e . Due to this, the interlayer resin insulating layer 50 provided above the plain layer 34 U and the resin core substrate 30 provided below the plan layer 34 U can be in direct contact to each other through the gaps of the mesh holes 35 d provided on the peripheral portion of the land 36 a , thereby making it possible to enhance bonding property. Also, gas containing moisture and the like absorbed by the interlayer resin insulating layers 50 and the core substrate 30 can be exhaled through the gaps of the mesh holes 35 d provided on the peripheral portion of the land 36 a .
- the land 36 a is formed in each of the mesh holes 34 d in the chip mount region C, no irregular portions are formed and the chip mount region C can be made flat.
- the through hole land 36 a and the via hole 60 may be connected through a conductor layer (cover plating) 36 e covering the through hole.
- FIG. 31 is a cross-sectional view showing a multilayer build-up wiring board (package board) 10 before an integrated circuit chip 90 is mounted thereon.
- FIG. 32 is a cross-sectional view showing the multilayer build-up wiring board 10 in a state in which the integrated circuit chip 90 is mounted. As shown in FIG. 32 , an integrated circuit chip 90 is mounted on the upper surface of the multilayer build-up wiring board 10 and the lower surface of the board 10 is connected to a daughter board 94 .
- the build-up layer 80 A consists of an interlayer resin insulating layer 50 on which a via hole 60 and conductor circuits 58 a and 58 b are formed, and an interlayer resin insulating layer 150 on which via holes 160 A and 160 B and a conductor circuit 158 B are formed.
- the build-up layer 80 B consists of an interlayer resin insulating layer 50 on which a via hole 60 and conductor circuits 58 a and 58 b are formed, and an interlayer resin insulating layer 150 on which via holes 160 A and 160 B and a conductor circuit 158 B are formed.
- Solder bumps 76 UA and 76 UB for connecting to the lands 92 (see FIG. 32 ) of the integrated circuit chip 90 are arranged on the upper surface side.
- Solder bumps 76 DA and 76 DB for connecting to the lands 96 (see FIG. 32 ) of the daughter board (sub-board) 94 are arranged on the lower surface side.
- FIG. 33A is a cross-sectional view taken along line A-A of FIG. 31 , that is, a plan view of the opening portion of the via hole 60 provided in the surface of the interlayer resin insulating layer 50 .
- FIG. 33B is an explanatory view perspectively showing the via hole 60 .
- FIG. 33C is (a cross-sectional view taken along line C-C of FIG. 31 , that is, a plan view of the opening portion of the through hole 36 formed in the surface of the core substrate 30 .
- FIG. 33D is an explanatory view perspectively showing the through hole 36 .
- the via hole 60 is divided into two parts and two wiring paths 61 a and 61 b are formed.
- the through hole 36 is divided into two parts and two wiring paths 37 a and 37 b are formed.
- Semi-circular through hole lands 39 a and 39 b are connected to the wiring paths 37 a and 37 b , respectively.
- the through hole lands 39 a and 39 b are connected to the wiring paths 61 a and 61 b of the via hole, respectively.
- the solder bump 76 UA is connected to the wiring path 37 a of the through hole 36 through the wiring path 61 a of the via hole 60 and the via hole 160 A.
- the bump 76 UA is further connected to the solder bump 76 DA through the wiring path 61 a of the via hole 60 and the via hole 160 A from the wiring path 37 a .
- the solder bump 76 UB is connected to the wiring path 37 b of the through hole 36 through the via hole 160 and the wiring path 61 b of the via hole 60 .
- the bump 75 UB is further connected to the solder bump 76 DB through the wiring path 61 b of the via hole 60 and the via hole 160 B from the wiring path 37 b.
- the lands 39 a and 39 b formed at the opening of the through hole 36 are formed semi-circularly as shown in FIGS. 33C and 33D , and connected to the wiring paths 61 a and 61 b of the via hole, respectively, as shown in FIG. 31 .
- a region right on the through hole 36 can function as an inner layer pad to thereby remove a dead space.
- the arrangement concentration of the through holes 36 provided in the multilayer core substrate 30 improves and the number of the through holes 36 can be thereby increased.
- two wiring paths 37 a and 37 b are arranged per through hole 36 , so that the wiring paths twice as many as the through holes can be provided in the core substrate 30 .
- the via hole 60 arranged just on the through hole 36 consists of two wiring paths 61 a and 61 b , the wiring paths twice as many as the via holes can be provided in the interlayer resin insulating layer 50 . Due to this, the wirings on the multilayer build-up wiring board can be arranged with high concentration. Besides, since the via hole 60 is formed right on the through hole 36 , the wiring length is shortened and a high-speed multilayer build-up wiring board can be, therefore, realized.
- the wirings on the back side thereof are integrated into one another and connected to the bumps on the front side.
- the wirings can be integrated on the build-up wiring layers 90 A and 90 B formed on the front and back sides, respectively, at the same pace.
- the number of build-up wiring layers 90 A and 90 B formed on the front and back sides, respectively can be reduced. That is to say, on the package substrate, wirings from a plurality of bumps on the front surface side (IC chip side) are connected to bumps on the back side (mother board side) while the wirings are integrated, so that more bumps are formed on the front side than the bumps on the back side.
- the number of build-up wiring layers 90 A and 90 B formed on the front and back sides, respectively can be made same (minimum).
- FIGS. 34A and 34B Another mode of the third embodiment according to the present invention will be described with reference to FIGS. 34A and 34B .
- FIGS. 34A and 34B show a case where a build-up wiring layer is formed on one side.
- a conductor pin 230 is inserted into a through hole 36 and fixed by a solder 232 .
- a solder resist 234 is provided on the back side.
- the conductor pin 230 is divided into two parts at the center by an insulator 230 c and the both surfaces are electrically connected to the divided wiring paths 37 a and 37 b of the through hole 36 , respectively.
- the wiring paths 37 a and 37 b are connected to the wiring paths 61 a and 61 b of the via hole 60 , respectively.
- the wiring paths 61 a and 61 b are connected to solder bumps 76 UA and 76 UB through via holes 160 A and 160 B, respectively.
- FIG. 34B shows a case where solder bumps 76 DB and 76 DA for connection purposes are formed on the side opposite to that on which the build-up multilayer wiring layer is formed.
- the solder bumps 76 DB and 76 DA are electrically connected to the divided wiring paths 37 a and 37 b of the through hole 36 , respectively.
- the wiring paths 37 a and 37 b are connected to the wiring paths 61 a and 61 b of the via hole 60 , respectively.
- the wiring paths 61 a and 61 b are connected to solder bumps 76 UA and 76 UB through the via holes 160 A and 160 B, respectively.
- a signal line from the build-up multilayer wiring layer provided on one side of the core substrate can be pulled to the back side by the divided wiring paths 37 a and 37 b of the through hole 36 and the degree of freedom of the wirings on the back side can be improved.
- a copper-clad laminate 30 A including a substrate 30 of glass epoxy resin or BT (Bismaleimide/Triazine) resin and having a 18 ⁇ m copper foil 32 laminated on both sides thereof is used as a starting material (see FIG. 24A ).
- the copper-clad laminate 30 A is drilled and a penetrating hole 16 for a through hole is formed (see FIG. 24B ).
- a Pb catalyst is added and electroless plating treatment is conducted to the substrate, to thereby form a through hole 36 in the penetrating hole 16 (see FIG. 24C ).
- the substrate 30 having the through holes 36 formed of an electroless copper plated film is washed, dried and subjected to oxidation-reduction treatment.
- a roughened layer 20 is provided on the entire surface of conductors including the through holes 36 (see FIG. 24D ).
- a filler. 22 containing copper particles of a mean particle diameter of 10 ⁇ m (manufactured by TATSUTA Electric Wire & Cable Co., Ltd., non-conductive plugging copper paste, product name: DD paste) is filled in the through holes 36 by screen printing, and dried and hardened ( FIG. 24E ).
- electrolytic plating is conducted under the same conditions as those in the first embodiment to thereby form electrolytic copper plated films 24 of a thickness of 15 ⁇ m and to form conductor layers (which become a semi-circular through hole lands) 26 a covering the filler 22 filled in the through hole 36 ( FIG. 25H ).
- a commercially available photosensitive dry film is put on each side of the substrate 30 on which portions which become conductors 26 a are formed, and a mask is mounted thereon. The film is exposed at 100 mJ/cm 2 and developed by 0.8% sodium carbonate, to thereby provide etching resists 25 of a thickness of 15 ⁇ m (see FIG. 25I ).
- the substrate 30 is submerged in the electroless copper plating solution having the same composition as that in the first embodiment to thereby form electroless plated films 52 of a thickness of 0.6 ⁇ m on the entire roughened surface (see FIG. 28U ).
- the wiring concentration on the interlayer resin insulating layer 350 in which the via holes 260 are arranged can be increased by dividing the via holes 260 .
- the multilayer build-up wiring board in the third embodiment due to the fact that one via hole consists of a plurality of wiring paths, several times as many the wiring paths as the via holes can be provided in the interlayer resin insulating layer, thereby making it possible to provide the wirings on the multilayer build-up wiring board with high concentration.
- a different metal film may be formed above or below the two-layer structured conductor layer.
- a roughened layer made of another metal film may be formed to cover the conductor layer.
- the conductor layer and the resin insulating layer having the structures shown in FIG. 36 may be repeatedly formed.
- etching is conducted.
- a conductor layer of a two-layer structure can be formed as shown in FIG. 36 .
- the first plating resist 232 is first formed on an insulating substrate 231 (see FIG. 37A ).
- the first metal film 233 is formed on portions on which the first plating resist 232 is not formed (see FIG. 37B )
- the first metal film 233 may be preferably thick and it is, therefore, desirable that the film 233 is formed by electroplating. In addition, it is desirable that the thickness of the film 233 is almost the same as that of the first plating resist 232 .
- the second metal film 235 is formed so as to fill recessed portions formed by the second plating resists 234 (see FIG. 37D ).
- the plating resists are removed, thereby forming a conductor of a two-layer structure consisting of the first metal film 233 and the second metal film 235 (see FIG. 37E ).
- the multilayer build-up wiring board in the fourth embodiment has a structure in which at least one resin insulating layer and at least one layer of a conductor circuit are formed on a resin substrate.
- the board is characterized in that at least one layer of the conductor circuit is a conductor layer of a two-layer structure in which the second metal film thinner than the first metal film is formed on the first metal film and in that the sides of the second metal film forming the conductor layer protrudes outside compared to the sides of the first metal film.
- the sides of the second metal film formed on the first metal film protrude outside compared to those of the first metal film. Due to this, even if temperature change or the like occurs, stress does not concentrate on the corners of the conductor layer, with the result that it is possible to prevent the resin insulating layer from cracking.
- a resin substrate on which a conductor circuit is directly formed may be used.
- a resin insulating layer and a layer of a conductor circuit may be provided on the resin substrate or two or more resin insulating layers and two or more layers of conductor circuits may be provided on the substrate.
- a resin substrate on which no conductor circuit is formed may be used.
- a resin insulating layer and a layer of a conductor circuit may be provided on the resin substrate or two or more resin insulating layers and two or more layers of conductor circuits may be provided on the substrate.
- the resin insulating layer and the conductor circuit may be provided on one side of the resin substrate or may be provided on both sides thereof.
- a wiring substrate having a lower conductor circuit is formed on the surface of a resin substrate.
- an etching resist is formed on a copper foil and then etching is conducted with an etchant of a mixture liquid of sulfuric acid and peroxide, a sodium persulfate solution or an ammonium persulfate solution to thereby form a lower conductor circuit.
- a penetrating hole is drilled in the resin substrate.
- the wall surface of the hole and the surface of the copper foil are electroless plated to thereby form a through hole. Copper plating is preferably adopted for the electroless plating.
- electroplating may be conducted to thicken the copper foil. Copper plating is preferable for the electroplating.
- the inner wall of the through hole and the surface of the electroplated film surface may be roughened.
- the roughening method there are, for example, blackening (oxidation)—reduction treatment, spray treatment using a mixture liquid of organic acid and cupric complex or Cu—Ni—P needle alloy plating.
- a conductive paste may be filled in the through hole and a conductor layer covering the conductor paste can be formed by electroless plating or electroplating.
- the adhesive agent layer is exposed and developed. Thereafter, the layer is thermally hardened to thereby obtain a via hole opening.
- thermohardening resin the resin layer is thermally hardened and then subjected to laser treatment.
- a via hole opening can be provided in the interlayer resin insulating layer.
- Catalyst nuclei is added to the wiring substrate having the interlayer resin insulating layer of a roughened surface.
- the catalyst nuclei it is preferable to use noble metal ions or noble metal colloid. Normally, palladium chloride or palladium colloid is used.
- palladium is a preferable catalyst nuclei.
- electroless plating is conducted to the surface of the interlayer resin insulating layer on which the catalyst nuclei has been added to thereby form an electroless plated film on the entirety of the roughened surface.
- the thickness of the electroless plated film is preferably 0.5 to 5 ⁇ m.
- Electroplating of a thickness of 5 to 20 ⁇ m is conducted to portions on which no plating resist is formed and an upper conductor circuit and a via hole are formed.
- electroless nickel plating is conducted to form a nickel plated film.
- the reason for forming the nickel plated film is that electroplated coatings of alloy of Cu—Ni—P are easily deposited on the nickel plated film. Also, the nickel plated film functions as a metal resist, so that excessive etching can be advantageously prevented in the later etching step.
- Copper plating is preferable for the above electroplating.
- the substrate from which the plated resist is removed is submerged in a mixture liquid of sulfuric acid and peroxide, a sodium persulfate solution or an ammonium persulfate solution to thereby etch the substrate.
- the electroless plated film present under the plating resist is removed and an independent upper layer conductor circuit is provided.
- the electroless nickel plated film is not etched and the copper plated film is slightly etched. Due to this, the sides of the electroless nickel plated film protrude outside compared to those of the copper plated film and a conductor layer of two-layer structure is formed.
- the substrate from which an oxide film has been removed is submerged into a plating liquid and a roughened layer of porous Cu—Ni—P alloy is formed on the upper layer conductor circuit. See FIG. 36A .
- the roughened layer of Cu—Ni—P alloy is easily deposited on the nickel plated film. Due to this, corners become closer to a curved surface, thereby preventing the concentration of stress even if the conductor layer is expanded or contracted.
- a copper-clad laminate including a substrate 30 of a thickness of 1 mm and of glass epoxy resin or BT (Bismaleimide/Triazihe) resin and having a 18 ⁇ m copper foil 32 laminated on both sides thereof is used as a starting material.
- the copper-clad laminate is drilled and plating resists are formed thereon.
- the substrate 30 is subjected to electroless plating to form through holes 36 and pattern-etched in accordance with an ordinary method, thereby forming an inner layer conductor circuit 32 on each of the both sides of the substrate.
- a filling resin 40 mainly consisting of epoxy resin is coated on both sides of the substrate by using printer, thereby filling the filling resin 40 between inner layer conductor circuits 34 or into the through holes 36 and drying the substrate. That is, the filling resin 40 is filled between the inner layer conductor circuits 34 or into the through hole 36 by these steps (see FIG. 38C ).
- the substrate which has been subjected to the treatment (2) is sanded and buffed. Thereafter, the filling resin 40 thus filled is heated and hardened (see FIG. 38D ).
- a roughened layer 42 of Cu—Ni—P porous alloy having a thickness of 2 ⁇ m is formed on the each of the surfaces of the exposed inner layer conductor circuits 34 and on the lands of the through hole 36 as in the case of the first embodiment. Further, an Sn layer of a thickness of 0.05 ⁇ m is formed on the surface of each roughened layer 42 (see FIG. 39A ) It is noted that the Sn layer is not shown in the drawings.
- An electroless plating adhesive agent is coated on both sides of the substrate twice using a roll coater. The substrate is left horizontally for 20 minutes and then dried at 60° C. for 30 minutes (see FIG. 39B ).
- interlayer resin insulating layers 50 50 a , 50 b ) each having an opening hole (opening hole 48 for a via hole) and having a thickness of 18 ⁇ m (see FIG. 39C ).
- the substrate on which the via hole opening hole 48 has been formed is submerged in a chromic acid solution (700 g/l) at 73° C.
- a palladium catalyst (manufactured by Atotec) is added to the surface of the substrate which the surface has been subjected to roughening treatment, thereby providing catalyst nuclei on the surfaces of the interlayer resin insulating layers 50 and on the inner wall surface of the via hole opening hole 48 .
- the substrate is submerged in an electroless copper plating solution which composition is shown below to thereby form an electroless copper plated film 52 having a thickness of 0.8 ⁇ m on the entirety of the roughened surface (see FIG. 40A ).
- a multilayer build-up wiring board is manufactured in the same manner as that of the fourth embodiment except that the step (11) is not conducted and nickel films are not formed in the second comparison example.
- FIGS. 43A and 43B show microphotographs of the optical microscope showing the cross section obtained in the fourth embodiment.
- the sides of the second metal film forming a conductor layer of two-layer structure protrude outside compared to those of the first metal film. Owing to this, even if resin insulating layers are formed on the conductor layers and temperature change or the like occurs, the stress does not concentrate on the corners of the conductor layers, with the result that it is possible to prevent the resin insulating layer from cracking.
- the sides of the second metal film forming the two conductor layers protrude outside with respect to those of the first metal film. Owing to this, even if temperature change or the like occurs, the stress does not concentrate on the corners of the conductor layers to thereby make it possible to prevent the resin insulating layers from cracking.
Abstract
Description
-
- a plurality of plain layers (which function as power conductor layers or ground conductor layers) are formed as the conductor layers; and
- mesh holes are formed in the plurality of plain layers so that at least part of the mesh holes overlay one another.
-
- plain layers (serving as power conductor layers or ground conductor layers) are formed as conductor layers at least one side of the core substrate;
- a plain layer is formed out of at least one of the conductor layers formed between the interlayer resin insulating layers; and
- mesh holes are formed in the plain layer of the core substrate and the plain layer between the interlayer resin insulating layers so that at least part of the mesh holes overlay one another.
-
- a diameter of each of said mesh holes is set at 75 to 300 μm and a distance between the mesh holes is set at 100 to 1500 μm.
CH3O—(CH2CH2O)n—CH3 (n=1 to 5)
-
- mesh holes are provided in plain layers formed as said conductor layers, and lands of through holes or the via holes and pads connected to the via holes are provided in at least part of mesh holes in a region facing said chip mount region through the interlayer resin insulating layers.
-
- mesh holes are provided in plain layers formed as said conductor layers, and lands of the via holes are provided in at least part of the mesh holes in a region facing said chip mount region through the interlayer resin insulating layers.
-
- mesh holes are provided in plain layers formed as said conductor layers, and solid conductor layers are provided in at least part of mesh holes in a region facing said chip mount region through the interlayer resin insulating layers.
-
- mesh holes are provided in plain layers formed as said conductor layers, and lands of the through holes are provided in at least part of mesh holes in a region facing said chip mount region through the interlayer resin insulating layers.
-
- one of said via holes is formed out of a plurality of wiring paths.
-
- one of said via holes is formed out of two wiring paths.
-
- a plurality of wiring paths are provided in each of the through hole in said core substrate; and
- via holes consisting of a plurality of wiring paths each connected to each of said wiring paths of said through hole are provided right on said through holes in which said plurality of wiring paths are provided.
-
- a plurality of wiring paths are provided in each of the through holes in said core substrate; and
- via holes consisting of a plurality of wiring paths each connected to each of said wiring paths of said through hole are provided right on said through holes in which said plurality of wiring paths are provided.
-
- a filler is filled in the through holes of said core substrate and a conductor layer covering an exposed surface of the filler from the through holes is formed in the through hole;
- the through holes and the conductor layers are divided into a plurality of parts, respectively; and
- via holes consisting of wiring paths connected to the divided parts of the conductor layers, respectively, are provided right on the through holes covered with said divided parts of the conductor layers.
-
- sides of the second metal film forming said conductor layer protrude outside compared with sides of said first metal film.
-
- at least one layer of said conductor circuit includes a conductor layer of two layer structure in which a second metal film, thinner than a first metal film is provided on said first metal film; and
- sides of the second metal film forming said conductor layer protrude outside compared with sides of said first metal film.
(2) The
(3) The composition of material for preparing a filling resin described in C above is mixed and kneaded to obtain a filling resin.
(4) The filling resin obtained in (3) above is coated on the both sides of the
(5) The one side of the substrate which has been subjected to the treatment of (4) above is sanded by belt sanding using a #600 belt sand paper (manufactured by Sankyo Rikagaku Co., Ltd.) so that the filling
(9) A photo mask film (not shown) on which a 85 μmφ black circle had been printed is closely contacted with the both sides of the
(10) The
(11) A palladium catalyst (manufactured by Atotec) is added to the surface of the
[Electroless Plating Solution]
EDTA | 150 | g/l | ||
Copper sulfate | 20 | g/ | ||
HCHO | ||||
30 | ml/l | |||
NaOH | 40 | g/l | ||
α, α′-bypyridil | 80 | mg/l | ||
PEG | 0.1 | g/l | ||
[Electroless Plating Conditions]
-
- Solution temperature: 70° C.
- Time: 30 minutes
(12) A commercially available photosensitive dry film is put on each electroless copper plated film formed in (11) above and a mask is mounted thereon. The film is exposed at 100 mJ/cm2 and developed by 0.8% sodium carbonate, to thereby provide plating resists 54 of a thickness of 15 μm (seeFIG. 3K ).
(13) Next, electrolytic copper plating is conducted to portions on which no resist is formed under the following conditions, to thereby form electrolytic copper platedfilms 56 of a thickness of 15 μm (seeFIG. 3L )
[Electrolytic Plating Solution]
Sulfuric acid | 180 | g/l | ||
Copper sulfate | 80 | g/l | ||
Additive (manufactured by | 1 | ml/l | ||
Atotec Japan, Karapacido GL) | ||||
[Electrolytic Plating Conditions]
Current density | 1 | A/dm2 | ||
Time | 30 | minutes | ||
Temperature | Room | temperature | ||
(14) After the plating resists 54 are peeled off by 5% KOH, the electroless plated
(15) The same treatment as in (6) is conducted and a roughened
(16) The steps of (7) to (15) are repeated, thereby forming interlayer
(17) Thereafter, a solder bump is formed on the above-stated multilayer build-up wiring board. The above-stated solder resist composition, as described in D. above of a thickness of 45 μm is coated on the both sides of the
(18) Next, the
(19) Solder bumps (solder bodies) 76U, 76D are formed in the opening
(2) The
(3) The same composition of material for preparing a filling resin described in the first embodiment is mixed and kneaded to obtain a filling resin.
(4) The filling
(5) The
(6) A coated layer and roughened
(9) A photo mask film 51 (
(10) The
(11) A palladium catalyst (manufactured by Atotec) is added to the surface of the
(12) A commercially available photosensitive dry film is put on each electroless copper plated
(13) Next, electrolytic copper plating is conducted to portions on which no resist is formed under the same conditions as those in the first embodiment, to thereby form electrolytic copper plated
(14) After the plating resists 54 are peeled off by 5% KOH, the electroless plated
(15) The same treatment as in (6) is conducted and roughened
(16) The steps of (7) to (15) are repeated, thereby forming interlayer
(17) Thereafter, a solder bump is formed on the above-stated multilayer build-up wiring board. The same solder resist composition 70 a of a thickness of 45 μm as that in the first embodiment is coated on the both sides of the
(18) Next, nickel plated
(19) Solder bumps (solder bodies) 76U, 76D are formed in the opening
(2) The
(3) Next, a filler. 22 containing copper particles of a mean particle diameter of 10 μm (manufactured by TATSUTA Electric Wire & Cable Co., Ltd., non-conductive plugging copper paste, product name: DD paste) is filled in the through
(4) A palladium catalyst (manufactured by Atotec) is added to the surface of the
(5) Next, electrolytic plating is conducted under the same conditions as those in the first embodiment to thereby form electrolytic copper plated
(6) A commercially available photosensitive dry film is put on each side of the
(7) Portions of the plated
(8) Furthermore, a carbon dioxide laser of 2×10−4-second short pulse is applied to thereby remove part of the
(9) Next, the exposed through
(10) Thereafter, the surface of the through
(11) Further, a metal mask having an opening is mounted in the through
(12) The same composition of material for preparing a filling resin as in the first embodiment is mixed and kneaded to obtain a filling resin. The filling
(13) A coated layer and roughened
(16) A photo mask film (not shown), on which a black circle has been printed, is closely contacted with the both sides of the
(17) The
(18) A commercially available photosensitive dry film is put on and a mask formed into a predetermined pattern is mounted on the substrate. The film is exposed at 100 mJ/cm2 and developed by 0.8% sodium carbonate, to thereby provide plating resists 51 for dividing the
(21) Next, electrolytic copper plating is conducted to portions on which no resists are formed under the same conditions as those in the first embodiment, to thereby form electrolytic copper plated
(22) After the plating resists 51 and 54 are peeled off by 5% KOH, the electroless plated
(23) The same treatment as in (13) is conducted and a roughened
(24) The steps of (14) to (23) are repeated, thereby forming upper interlayer
(25) The solder resist composition described in D. above and having a thickness of 20 μm is coated on the both sides of the
(26) Next, nickel plated
(27) Thereafter, a solder paste is printed in the opening
(5) Catalyst nuclei is added to the wiring substrate having the interlayer resin insulating layer of a roughened surface. To add the catalyst nuclei, it is preferable to use noble metal ions or noble metal colloid. Normally, palladium chloride or palladium colloid is used. To fix the catalyst nuclei, it is preferable to conduct heat treatment. Palladium is a preferable catalyst nuclei.
(6) Next, electroless plating is conducted to the surface of the interlayer resin insulating layer on which the catalyst nuclei has been added to thereby form an electroless plated film on the entirety of the roughened surface. The thickness of the electroless plated film is preferably 0.5 to 5 μm.
(3) The substrate which has been subjected to the treatment (2) is sanded and buffed. Thereafter, the filling
(4) A roughened
(5) An electroless plating adhesive agent is coated on both sides of the substrate twice using a roll coater. The substrate is left horizontally for 20 minutes and then dried at 60° C. for 30 minutes (see
(6) The substrate on which the electroless plating adhesive agent layer is formed in (5) above is exposed and developed to thereby form interlayer resin insulating layers 50 (50 a, 50 b) each having an opening hole (opening
(7) The substrate on which the via
EDTA | 60 | g/ | ||
Copper sulfate | ||||
10 | g/l | |||
HCHO | 6 | ml/ | ||
NaOH | ||||
10 | g/l | |||
α, α′-bypyridil | 80 | mg/l | ||
Polyethylene glycol (PEG) | 0.1 | g/l | ||
[Electroless Plating Conditions]
-
- Solution temperature: 60° C.
- Time: 20 minutes
(9) A commercially available photosensitive dry film is put on the electroless copper platedfilm 52 and a mask is mounted thereon. The film is exposed at 100 mJ/cm2 and developed by 0.8% sodium carbonate, to thereby provide plating resists 54 (seeFIG. 40B ).
(10) Next, electrolytic copper plating is conducted under the same conditions as those in the first embodiment to thereby form electrolytic copper platedfilms 56 of a thickness of 13 μm.
(11) Further, the substrate is submerged in an electroless nickel batch of a solution (90° C.) of nickel chloride (30 g/l), sodium hypophosphite (10 g/l) and sodium citrate (10 g/l) to thereby formnickel films 57 of a thickness of 1.2 μm on the electrolytic copperplated films, respectively (seeFIG. 40C ).
(12) After the plating resists 54 are peeled off by 5% KOH, the electroless platedfilms 52 under the plating resist 54 are etched away by a mixture liquid of sulfuric acid and peroxide, thereby forming upper layer conductor circuits 58 (including via holes 60) each consisting of the electroless copper platedfilm 52, the electrolytic copper platedfilm 56 and thenickel film 57, having L/S=28/28 and a thickness of 11 μm (seeFIG. 40D ).
(13) After the oxide films on the nickel films are removed by 18 parts by weight of hydrochloric acid, the same treatment as in (4) above is conducted to thereby form roughenedlayers 42 of Cu—Ni—P alloy having a thickness of 2 μm on the surfaces of the upperlayer conductor circuits 58, respectively.
(14) The steps of (5) to (13) are repeated and further upperlayer conductor circuits 158, viaholes 160 and roughenedlayers 42 are formed. Finally, solder resistlayers 70 each having openings are formed, nickel platedfilms 72 and gold platedfilms 74 are formed. Thereafter, solder bumps 76 are formed to thereby obtain a multilayer build-up wiring board having solder bumps 18 (seeFIGS. 41A to 42C ).
Claims (11)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/334,062 US7514779B2 (en) | 1998-09-17 | 2002-12-31 | Multilayer build-up wiring board |
US12/406,009 US7847318B2 (en) | 1998-09-17 | 2009-03-17 | Multilayer build-up wiring board including a chip mount region |
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28343798A JP4127433B2 (en) | 1998-09-17 | 1998-09-17 | Multilayer buildup wiring board and method for manufacturing multilayer buildup wiring board |
JP10-283437 | 1998-09-17 | ||
JP32453598A JP2000133941A (en) | 1998-10-28 | 1998-10-28 | Multilayer build-up wiring board |
JP10-324535 | 1998-10-28 | ||
JP36296198A JP2000188447A (en) | 1998-12-21 | 1998-12-21 | Wiring board and printed wiring board |
JP10-362961 | 1998-12-21 | ||
JP00031599A JP4127440B2 (en) | 1999-01-05 | 1999-01-05 | Multilayer build-up wiring board |
JP11-315 | 1999-01-05 | ||
US09/787,321 US6613986B1 (en) | 1998-09-17 | 1999-09-08 | Multilayer build-up wiring board |
US10/334,062 US7514779B2 (en) | 1998-09-17 | 2002-12-31 | Multilayer build-up wiring board |
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PCT/JP1999/004895 Division WO2000018202A1 (en) | 1998-09-17 | 1999-09-08 | Multilayer build-up wiring board |
US09787321 Division | 1999-09-08 | ||
US09/787,321 Division US6613986B1 (en) | 1998-09-17 | 1999-09-08 | Multilayer build-up wiring board |
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Application Number | Title | Priority Date | Filing Date |
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US12/406,009 Division US7847318B2 (en) | 1998-09-17 | 2009-03-17 | Multilayer build-up wiring board including a chip mount region |
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US20030102151A1 US20030102151A1 (en) | 2003-06-05 |
US7514779B2 true US7514779B2 (en) | 2009-04-07 |
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US10/334,062 Expired - Fee Related US7514779B2 (en) | 1998-09-17 | 2002-12-31 | Multilayer build-up wiring board |
US12/406,009 Expired - Fee Related US7847318B2 (en) | 1998-09-17 | 2009-03-17 | Multilayer build-up wiring board including a chip mount region |
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US09/787,321 Expired - Lifetime US6613986B1 (en) | 1998-09-17 | 1999-09-08 | Multilayer build-up wiring board |
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US12/406,009 Expired - Fee Related US7847318B2 (en) | 1998-09-17 | 2009-03-17 | Multilayer build-up wiring board including a chip mount region |
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US (3) | US6613986B1 (en) |
EP (2) | EP1137333B1 (en) |
KR (4) | KR20090059173A (en) |
CN (1) | CN1318274A (en) |
DE (1) | DE69942279D1 (en) |
MY (2) | MY141631A (en) |
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WO (1) | WO2000018202A1 (en) |
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US6787443B1 (en) * | 2003-05-20 | 2004-09-07 | Intel Corporation | PCB design and method for providing vented blind vias |
CN101160026B (en) * | 2003-05-21 | 2011-08-03 | 日立化成工业株式会社 | Primer, conductor foil with resin, laminate and process for producing the laminate |
KR100567087B1 (en) * | 2003-10-20 | 2006-03-31 | 삼성전기주식회사 | Method for fabricating the multi layer printed circuit board in parallel with improved interconnection |
US7057115B2 (en) * | 2004-01-26 | 2006-06-06 | Litton Systems, Inc. | Multilayered circuit board for high-speed, differential signals |
JP2005303090A (en) * | 2004-04-13 | 2005-10-27 | Toshiba Corp | Wiring board and its manufacturing method |
KR100557540B1 (en) * | 2004-07-26 | 2006-03-03 | 삼성전기주식회사 | BGA package board and method for manufacturing the same |
US7659193B2 (en) * | 2005-12-23 | 2010-02-09 | Phoenix Precision Technology Corporation | Conductive structures for electrically conductive pads of circuit board and fabrication method thereof |
JP4824397B2 (en) * | 2005-12-27 | 2011-11-30 | イビデン株式会社 | Multilayer printed wiring board |
WO2007144322A1 (en) * | 2006-06-14 | 2007-12-21 | Basf Se | Method for producing electrically conductive surfaces on a carrier |
US8022552B2 (en) | 2006-06-27 | 2011-09-20 | Megica Corporation | Integrated circuit and method for fabricating the same |
JP2008016630A (en) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | Printed circuit board, and its manufacturing method |
US7595112B1 (en) * | 2006-07-31 | 2009-09-29 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Resin infusion of layered metal/composite hybrid and resulting metal/composite hybrid laminate |
KR100772113B1 (en) * | 2006-09-28 | 2007-11-01 | 주식회사 하이닉스반도체 | Solid printed circuit board |
US20080142252A1 (en) * | 2006-12-13 | 2008-06-19 | Romi Mayder | Solid via with a contact pad for mating with an interposer of an ATE tester |
US20080169124A1 (en) * | 2007-01-12 | 2008-07-17 | Tonglong Zhang | Padless via and method for making same |
TWI316381B (en) * | 2007-01-24 | 2009-10-21 | Phoenix Prec Technology Corp | Circuit board and fabrication method thereof |
US8193636B2 (en) | 2007-03-13 | 2012-06-05 | Megica Corporation | Chip assembly with interconnection by metal bump |
US8455766B2 (en) * | 2007-08-08 | 2013-06-04 | Ibiden Co., Ltd. | Substrate with low-elasticity layer and low-thermal-expansion layer |
JP5085266B2 (en) | 2007-10-12 | 2012-11-28 | 富士通株式会社 | Wiring board and manufacturing method thereof |
US8129828B2 (en) * | 2008-09-29 | 2012-03-06 | Ngk Spark Plug Co., Ltd. | Wiring substrate with reinforcement |
US8186053B2 (en) | 2008-11-14 | 2012-05-29 | Fujitsu Limited | Circuit board and method of manufacturing the same |
JP5142967B2 (en) * | 2008-12-10 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US20100149771A1 (en) * | 2008-12-16 | 2010-06-17 | Cree, Inc. | Methods and Apparatus for Flexible Mounting of Light Emitting Devices |
JPWO2010087336A1 (en) * | 2009-01-27 | 2012-08-02 | パナソニック株式会社 | Semiconductor chip mounting method, semiconductor device obtained by using the method, semiconductor chip connection method, three-dimensional structure provided with wiring on the surface, and manufacturing method thereof |
KR101609597B1 (en) * | 2009-02-16 | 2016-04-07 | 삼성디스플레이 주식회사 | Circuit board and display panel assembly having the same |
JP5463235B2 (en) * | 2010-07-30 | 2014-04-09 | 日立オートモティブシステムズ株式会社 | Substrate structure used for in-vehicle electronic devices |
US8643154B2 (en) | 2011-01-31 | 2014-02-04 | Ibiden Co., Ltd. | Semiconductor mounting device having multiple substrates connected via bumps |
US8780576B2 (en) * | 2011-09-14 | 2014-07-15 | Invensas Corporation | Low CTE interposer |
TW201340807A (en) * | 2011-12-28 | 2013-10-01 | Panasonic Corp | Flexible wiring board, method for manufacturing flexible wiring board, package product using flexible wiring board, and flexible multilayer wiring board |
US20130168132A1 (en) * | 2011-12-29 | 2013-07-04 | Sumsung Electro-Mechanics Co., Ltd. | Printed circuit board and method of manufacturing the same |
JP4990419B1 (en) * | 2012-02-15 | 2012-08-01 | 株式会社イースタン | Substrate reference hole processing method |
US9275925B2 (en) * | 2013-03-12 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
CN104378907B (en) * | 2013-08-12 | 2017-06-30 | 富葵精密组件(深圳)有限公司 | Circuit board and preparation method thereof |
US9153550B2 (en) * | 2013-11-14 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design with balanced metal and solder resist density |
JP6270630B2 (en) * | 2014-05-27 | 2018-01-31 | 株式会社伸光製作所 | Method for manufacturing printed wiring board having end face electrode |
JP6270628B2 (en) * | 2014-05-27 | 2018-01-31 | 株式会社伸光製作所 | Method for manufacturing printed wiring board having end face electrode |
JP6270629B2 (en) * | 2014-05-27 | 2018-01-31 | 株式会社伸光製作所 | Method for manufacturing printed wiring board having end face electrode |
JP6281871B2 (en) * | 2014-05-27 | 2018-02-21 | 株式会社伸光製作所 | Method for manufacturing printed wiring board having end face electrode |
JP6590447B2 (en) * | 2014-11-28 | 2019-10-16 | インテル・コーポレーション | Manufacturing method of multilayer printed wiring board |
SG10202011924YA (en) * | 2016-06-06 | 2021-01-28 | Showa Denko Materials Co Ltd | Method for manufacturing multilayer wiring board |
SG10202011919XA (en) * | 2016-06-06 | 2021-01-28 | Showa Denko Materials Co Ltd | Method for manufacturing multilayer wiring board |
JP6346916B2 (en) * | 2016-06-13 | 2018-06-20 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
JP6691835B2 (en) * | 2016-06-17 | 2020-05-13 | 株式会社アムコー・テクノロジー・ジャパン | Method for manufacturing semiconductor package |
US10054979B1 (en) * | 2017-06-19 | 2018-08-21 | Dell Products, L.P. | Placement of ground vias for high-speed differential signals |
EP3709779A1 (en) * | 2019-03-12 | 2020-09-16 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier and method of manufacturing the same |
CN111415587B (en) * | 2020-03-31 | 2022-04-19 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display panel |
CN112018481B (en) * | 2020-08-07 | 2021-07-23 | 中国电子科技集团公司第三十八研究所 | Miniaturized integrated microwave power divider with asymmetric near-metal grating transmission line |
CN112867243A (en) * | 2021-01-06 | 2021-05-28 | 英韧科技(上海)有限公司 | Multilayer circuit board |
Citations (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3739469A (en) | 1971-12-27 | 1973-06-19 | Ibm | Multilayer printed circuit board and method of manufacture |
US3781596A (en) | 1972-07-07 | 1973-12-25 | R Galli | Semiconductor chip carriers and strips thereof |
US3799777A (en) | 1972-06-20 | 1974-03-26 | Westinghouse Electric Corp | Micro-miniature electronic components by double rejection |
JPS49117970A (en) | 1973-03-16 | 1974-11-11 | ||
US4075416A (en) | 1975-03-07 | 1978-02-21 | Robert Bosch Gmbh | Electronic thin film circuit unit and method of making the same |
US4081601A (en) | 1975-03-31 | 1978-03-28 | Western Electric Co., Inc. | Bonding contact members to circuit boards |
US4303715A (en) * | 1977-04-07 | 1981-12-01 | Western Electric Company, Incorporated | Printed wiring board |
WO1983003040A1 (en) | 1982-02-26 | 1983-09-01 | Serras Paulet Edouard | Printed electric circuit |
US4506004A (en) * | 1982-04-01 | 1985-03-19 | Sullivan Donald F | Printed wiring board |
US4543715A (en) | 1983-02-28 | 1985-10-01 | Allied Corporation | Method of forming vertical traces on printed circuit board |
JPS60211897A (en) | 1984-04-05 | 1985-10-24 | 日本電気株式会社 | Multilayer circuit substrate |
US4754371A (en) | 1984-04-27 | 1988-06-28 | Nec Corporation | Large scale integrated circuit package |
JPS63199487A (en) | 1987-02-14 | 1988-08-17 | 日本電気株式会社 | Manufacture of wiring board |
US4795670A (en) * | 1986-05-14 | 1989-01-03 | Narumi China Corporation | Multilayer ceramic substrate with circuit patterns |
JPH01163634A (en) | 1987-12-21 | 1989-06-27 | Daido Steel Co Ltd | Temperature measuring method |
JPH01282888A (en) | 1988-05-10 | 1989-11-14 | Seiji Ando | Multilayer printed wiring board |
US4893404A (en) * | 1986-05-30 | 1990-01-16 | Furukawa Denki Kogyo Kabushiki Kaisha | Method for producing a multilayer printed wiring board |
JPH0455555A (en) | 1990-06-25 | 1992-02-24 | Misawa Homes Co Ltd | Mounting construction of hand-rail post of building |
JPH0464279A (en) | 1990-07-04 | 1992-02-28 | Fujitsu Ltd | Multilayer thin film wiring board |
US5153987A (en) | 1988-07-15 | 1992-10-13 | Hitachi Chemical Company, Ltd. | Process for producing printed wiring boards |
JPH0575258A (en) | 1991-09-11 | 1993-03-26 | Fujitsu Ltd | Manufacture of printed wiring board |
JPH0669660A (en) | 1992-03-26 | 1994-03-11 | Nec Corp | Printed wiring board and its manufacture |
US5296649A (en) | 1991-03-26 | 1994-03-22 | The Furukawa Electric Co., Ltd. | Solder-coated printed circuit board and method of manufacturing the same |
JPH07115283A (en) | 1993-10-19 | 1995-05-02 | Shin Kobe Electric Mach Co Ltd | Multilayer sealed board containing inner layer circuit and inner layer circuit board |
US5469615A (en) | 1993-05-06 | 1995-11-28 | Minnesota Mining And Manufacturing Company | Method for electrical interconnection of metallic patterns |
US5479138A (en) | 1993-12-27 | 1995-12-26 | Ngk Spark Plug Co., Ltd. | Multi-layer wiring board |
JPH085581A (en) | 1994-06-17 | 1996-01-12 | Kanebo Ltd | Contamination detector for thread winding bobbin |
US5493074A (en) | 1993-09-03 | 1996-02-20 | Nippon Graphite Industries Ltd. | Flexible printed circuit board comprising conductive circuits, an adhesive layer and cured films |
US5519177A (en) * | 1993-05-19 | 1996-05-21 | Ibiden Co., Ltd. | Adhesives, adhesive layers for electroless plating and printed circuit boards |
WO1996017503A1 (en) | 1994-12-01 | 1996-06-06 | Ibiden Co., Ltd. | Multilayer printed wiring board and process for producing the same |
US5562970A (en) * | 1990-03-19 | 1996-10-08 | Fujitsu Ltd. | Multilayer circuit structure having projecting via lead |
WO1997016056A1 (en) | 1995-10-23 | 1997-05-01 | Ibiden Co., Ltd. | Resin filler and multilayer printed wiring board |
JPH09246732A (en) * | 1996-03-01 | 1997-09-19 | Ibiden Co Ltd | Multilayer printed wiring board and manufacturing method thereof |
US5698470A (en) | 1995-12-27 | 1997-12-16 | Nec Corporation | Fabrication method of multilayer printed wiring board |
JPH1013026A (en) | 1996-06-19 | 1998-01-16 | Ibiden Co Ltd | Multilayer printed wiring board |
US5741575A (en) * | 1991-07-23 | 1998-04-21 | Ibiden Co., Ltd. | Adhesive for printed circuit board |
EP0844809A2 (en) | 1996-11-20 | 1998-05-27 | Ibiden Co, Ltd. | Solder resist composition and printed circuit boards |
JPH10163634A (en) | 1996-11-27 | 1998-06-19 | Kyocera Corp | Multilayer wiring board |
JPH10200271A (en) | 1997-01-13 | 1998-07-31 | Kyocera Corp | Multilayer interconnection board |
JPH10261869A (en) | 1997-01-17 | 1998-09-29 | Ibiden Co Ltd | Multilayer printed wiring board |
US5826330A (en) | 1995-12-28 | 1998-10-27 | Hitachi Aic Inc. | Method of manufacturing multilayer printed wiring board |
JPH10335817A (en) | 1997-05-27 | 1998-12-18 | Kyocera Corp | Multilayered wiring board |
US5879568A (en) | 1996-06-18 | 1999-03-09 | Hitachi, Ltd. | Process for producing multilayer printed circuit board for wire bonding |
JPH11121933A (en) | 1997-10-17 | 1999-04-30 | Canon Inc | Multilayered printed wiring board, and printed wiring board mounted with electronic components |
US5939789A (en) * | 1994-02-28 | 1999-08-17 | Hitachi, Ltd. | Multilayer substrates methods for manufacturing multilayer substrates and electronic devices |
US6046909A (en) * | 1998-11-16 | 2000-04-04 | Intel Corporation | Computer card with a printed circuit board with vias providing strength to the printed circuit board |
US6127633A (en) | 1995-04-28 | 2000-10-03 | Victor Company Of Japan, Ltd. | Multilayer print circuit board having a blind hole in an insulation layer with a roughened surface formed by application of an oxidizing agent and method of production |
US6134118A (en) * | 1995-01-19 | 2000-10-17 | Cubic Memory Inc. | Conductive epoxy flip-chip package and method |
US6178093B1 (en) * | 1996-06-28 | 2001-01-23 | International Business Machines Corporation | Information handling system with circuit assembly having holes filled with filler material |
US6248657B1 (en) * | 1998-03-13 | 2001-06-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
US20010004944A1 (en) * | 1999-12-14 | 2001-06-28 | Kei Nakamura | Double-sided circuit board and multilayer wiring board comprising the same and process for producing double-sided circuit board |
US20010011607A1 (en) * | 1997-12-26 | 2001-08-09 | Kiyokazu Moriizumi | Multilayer thin-film wiring board |
US20010029065A1 (en) * | 1996-11-08 | 2001-10-11 | Paul J. Fischer | Dimensionally stable core for use in high density chip packages and a method of fabricating same |
US6303871B1 (en) | 1999-06-11 | 2001-10-16 | Intel Corporation | Degassing hole design for olga trace impedance |
US6376049B1 (en) * | 1997-10-14 | 2002-04-23 | Ibiden Co., Ltd. | Multilayer printed wiring board and its manufacturing method, and resin composition for filling through-hole |
US6392898B1 (en) * | 1997-10-17 | 2002-05-21 | Ibiden Co., Ltd. | Package substrate |
US20020112885A1 (en) * | 1999-02-10 | 2002-08-22 | Sinichi Hotta | Printed circuit board and method for manufacturing same |
US20030007332A1 (en) * | 1999-04-01 | 2003-01-09 | Yasuaki Seki | Insulating resin composition for multilayer printed-wiring board |
US6512186B1 (en) * | 1998-06-26 | 2003-01-28 | Ibiden Co., Ltd. | Multilayer printed wiring board having a roughened inner conductor layer and production method thereof |
US6525275B1 (en) * | 1996-08-05 | 2003-02-25 | Ibiden Co., Ltd. | Multilayer printed circuit boards |
US6523252B1 (en) * | 1997-10-22 | 2003-02-25 | Nokia Mobile Phones Limited | Coaxial cable, method for manufacturing a coaxial cable, and wireless communication device |
US6528145B1 (en) * | 2000-06-29 | 2003-03-04 | International Business Machines Corporation | Polymer and ceramic composite electronic substrates |
US6571467B2 (en) * | 1998-09-18 | 2003-06-03 | International Business Machines Corporation | Method for producing a doublesided wiring board |
US20030194564A1 (en) * | 1995-12-08 | 2003-10-16 | Takayuki Araki | Fluorine-containing adhesive and adhesive film and laminated article produced by using same |
US6662442B1 (en) * | 1999-07-19 | 2003-12-16 | Nitto Denko Corporation | Process for manufacturing printed wiring board using metal plating techniques |
US6667235B2 (en) * | 1999-12-15 | 2003-12-23 | Shinko Electric Industries Co., Ltd. | Semiconductor device and manufacturing method therefor |
US6835895B1 (en) * | 1996-12-19 | 2004-12-28 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
MY121310A (en) | 1997-10-14 | 2006-01-28 | Ibiden Co Ltd | Multilayer printed wiring board and its manufacturing method,and resin composition for filling through-hole |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4120027Y1 (en) | 1964-02-04 | 1966-09-21 | ||
US3646246A (en) * | 1970-05-22 | 1972-02-29 | Honeywell Inf Systems | Circuit board and method of making |
CA1167403A (en) * | 1979-07-10 | 1984-05-15 | Unilever Limited | Microbial heteropolysaccharide |
JPS56119679U (en) * | 1980-02-15 | 1981-09-11 | ||
US5182420A (en) * | 1989-04-25 | 1993-01-26 | Cray Research, Inc. | Method of fabricating metallized chip carriers from wafer-shaped substrates |
JP2664485B2 (en) * | 1989-07-03 | 1997-10-15 | 日本電信電話株式会社 | Ceramic multilayer wiring board |
US5270488A (en) * | 1990-07-27 | 1993-12-14 | Mitsubishi Denki Kabushiki Kaisha | Shield construction for electrical devices |
US5173987A (en) * | 1991-04-12 | 1992-12-29 | Abington, Inc. | Rotary air jet screen cleaning device |
JPH0621611A (en) * | 1992-06-30 | 1994-01-28 | Fujitsu Ltd | Manufacture of printed wiring board |
JPH06120659A (en) * | 1992-10-06 | 1994-04-28 | Toray Ind Inc | Multilayer wiring structure |
EP0657932B1 (en) * | 1993-12-13 | 2001-09-05 | Matsushita Electric Industrial Co., Ltd. | Chip package assembly and method of production |
US5639989A (en) * | 1994-04-19 | 1997-06-17 | Motorola Inc. | Shielded electronic component assembly and method for making the same |
US5767447A (en) * | 1995-12-05 | 1998-06-16 | Lucent Technologies Inc. | Electronic device package enclosed by pliant medium laterally confined by a plastic rim member |
US6078502A (en) * | 1996-04-01 | 2000-06-20 | Lsi Logic Corporation | System having heat dissipating leadframes |
US6323436B1 (en) * | 1997-04-08 | 2001-11-27 | International Business Machines Corporation | High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer |
US6639155B1 (en) * | 1997-06-11 | 2003-10-28 | International Business Machines Corporation | High performance packaging platform and method of making same |
DE69942279D1 (en) | 1998-09-17 | 2010-06-02 | Ibiden Co Ltd | MULTILAYER CONSTRUCTED PCB |
-
1999
- 1999-09-08 DE DE69942279T patent/DE69942279D1/en not_active Expired - Lifetime
- 1999-09-08 KR KR1020097011027A patent/KR20090059173A/en active Search and Examination
- 1999-09-08 CN CN99811085A patent/CN1318274A/en active Pending
- 1999-09-08 US US09/787,321 patent/US6613986B1/en not_active Expired - Lifetime
- 1999-09-08 KR KR1020017003399A patent/KR20010085811A/en active Search and Examination
- 1999-09-08 KR KR1020087005014A patent/KR20080024239A/en active Application Filing
- 1999-09-08 EP EP99943231A patent/EP1137333B1/en not_active Expired - Lifetime
- 1999-09-08 KR KR1020087005013A patent/KR20080023369A/en not_active Application Discontinuation
- 1999-09-08 WO PCT/JP1999/004895 patent/WO2000018202A1/en active Application Filing
- 1999-09-08 EP EP07115803A patent/EP1868423A1/en not_active Withdrawn
- 1999-09-13 TW TW088115730A patent/TW453146B/en not_active IP Right Cessation
- 1999-09-16 MY MYPI20044069A patent/MY141631A/en unknown
- 1999-09-16 MY MYPI99004017A patent/MY123224A/en unknown
-
2002
- 2002-12-31 US US10/334,062 patent/US7514779B2/en not_active Expired - Fee Related
-
2009
- 2009-03-17 US US12/406,009 patent/US7847318B2/en not_active Expired - Fee Related
Patent Citations (70)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3739469A (en) | 1971-12-27 | 1973-06-19 | Ibm | Multilayer printed circuit board and method of manufacture |
US3799777A (en) | 1972-06-20 | 1974-03-26 | Westinghouse Electric Corp | Micro-miniature electronic components by double rejection |
US3781596A (en) | 1972-07-07 | 1973-12-25 | R Galli | Semiconductor chip carriers and strips thereof |
JPS49117970A (en) | 1973-03-16 | 1974-11-11 | ||
US4075416A (en) | 1975-03-07 | 1978-02-21 | Robert Bosch Gmbh | Electronic thin film circuit unit and method of making the same |
US4081601A (en) | 1975-03-31 | 1978-03-28 | Western Electric Co., Inc. | Bonding contact members to circuit boards |
US4303715A (en) * | 1977-04-07 | 1981-12-01 | Western Electric Company, Incorporated | Printed wiring board |
FR2522459A1 (en) | 1982-02-26 | 1983-09-02 | Serras Paulet Edouard | PRINTED ELECTRICAL CIRCUIT |
WO1983003040A1 (en) | 1982-02-26 | 1983-09-01 | Serras Paulet Edouard | Printed electric circuit |
US4506004A (en) * | 1982-04-01 | 1985-03-19 | Sullivan Donald F | Printed wiring board |
US4543715A (en) | 1983-02-28 | 1985-10-01 | Allied Corporation | Method of forming vertical traces on printed circuit board |
JPS60211897A (en) | 1984-04-05 | 1985-10-24 | 日本電気株式会社 | Multilayer circuit substrate |
US4754371A (en) | 1984-04-27 | 1988-06-28 | Nec Corporation | Large scale integrated circuit package |
US4795670A (en) * | 1986-05-14 | 1989-01-03 | Narumi China Corporation | Multilayer ceramic substrate with circuit patterns |
US4893404A (en) * | 1986-05-30 | 1990-01-16 | Furukawa Denki Kogyo Kabushiki Kaisha | Method for producing a multilayer printed wiring board |
JPS63199487A (en) | 1987-02-14 | 1988-08-17 | 日本電気株式会社 | Manufacture of wiring board |
JPH01163634A (en) | 1987-12-21 | 1989-06-27 | Daido Steel Co Ltd | Temperature measuring method |
JPH01282888A (en) | 1988-05-10 | 1989-11-14 | Seiji Ando | Multilayer printed wiring board |
US5153987A (en) | 1988-07-15 | 1992-10-13 | Hitachi Chemical Company, Ltd. | Process for producing printed wiring boards |
US5562970A (en) * | 1990-03-19 | 1996-10-08 | Fujitsu Ltd. | Multilayer circuit structure having projecting via lead |
JPH0455555A (en) | 1990-06-25 | 1992-02-24 | Misawa Homes Co Ltd | Mounting construction of hand-rail post of building |
JPH0464279A (en) | 1990-07-04 | 1992-02-28 | Fujitsu Ltd | Multilayer thin film wiring board |
US5296649A (en) | 1991-03-26 | 1994-03-22 | The Furukawa Electric Co., Ltd. | Solder-coated printed circuit board and method of manufacturing the same |
US5741575A (en) * | 1991-07-23 | 1998-04-21 | Ibiden Co., Ltd. | Adhesive for printed circuit board |
JPH0575258A (en) | 1991-09-11 | 1993-03-26 | Fujitsu Ltd | Manufacture of printed wiring board |
JPH0669660A (en) | 1992-03-26 | 1994-03-11 | Nec Corp | Printed wiring board and its manufacture |
US5469615A (en) | 1993-05-06 | 1995-11-28 | Minnesota Mining And Manufacturing Company | Method for electrical interconnection of metallic patterns |
US5519177A (en) * | 1993-05-19 | 1996-05-21 | Ibiden Co., Ltd. | Adhesives, adhesive layers for electroless plating and printed circuit boards |
US5493074A (en) | 1993-09-03 | 1996-02-20 | Nippon Graphite Industries Ltd. | Flexible printed circuit board comprising conductive circuits, an adhesive layer and cured films |
JPH07115283A (en) | 1993-10-19 | 1995-05-02 | Shin Kobe Electric Mach Co Ltd | Multilayer sealed board containing inner layer circuit and inner layer circuit board |
US5479138A (en) | 1993-12-27 | 1995-12-26 | Ngk Spark Plug Co., Ltd. | Multi-layer wiring board |
US5939789A (en) * | 1994-02-28 | 1999-08-17 | Hitachi, Ltd. | Multilayer substrates methods for manufacturing multilayer substrates and electronic devices |
JPH085581A (en) | 1994-06-17 | 1996-01-12 | Kanebo Ltd | Contamination detector for thread winding bobbin |
WO1996017503A1 (en) | 1994-12-01 | 1996-06-06 | Ibiden Co., Ltd. | Multilayer printed wiring board and process for producing the same |
US6134118A (en) * | 1995-01-19 | 2000-10-17 | Cubic Memory Inc. | Conductive epoxy flip-chip package and method |
US6127633A (en) | 1995-04-28 | 2000-10-03 | Victor Company Of Japan, Ltd. | Multilayer print circuit board having a blind hole in an insulation layer with a roughened surface formed by application of an oxidizing agent and method of production |
WO1997016056A1 (en) | 1995-10-23 | 1997-05-01 | Ibiden Co., Ltd. | Resin filler and multilayer printed wiring board |
US20030194564A1 (en) * | 1995-12-08 | 2003-10-16 | Takayuki Araki | Fluorine-containing adhesive and adhesive film and laminated article produced by using same |
US5698470A (en) | 1995-12-27 | 1997-12-16 | Nec Corporation | Fabrication method of multilayer printed wiring board |
US5826330A (en) | 1995-12-28 | 1998-10-27 | Hitachi Aic Inc. | Method of manufacturing multilayer printed wiring board |
JPH09246732A (en) * | 1996-03-01 | 1997-09-19 | Ibiden Co Ltd | Multilayer printed wiring board and manufacturing method thereof |
US5879568A (en) | 1996-06-18 | 1999-03-09 | Hitachi, Ltd. | Process for producing multilayer printed circuit board for wire bonding |
JPH1013026A (en) | 1996-06-19 | 1998-01-16 | Ibiden Co Ltd | Multilayer printed wiring board |
US6178093B1 (en) * | 1996-06-28 | 2001-01-23 | International Business Machines Corporation | Information handling system with circuit assembly having holes filled with filler material |
US6525275B1 (en) * | 1996-08-05 | 2003-02-25 | Ibiden Co., Ltd. | Multilayer printed circuit boards |
US20010029065A1 (en) * | 1996-11-08 | 2001-10-11 | Paul J. Fischer | Dimensionally stable core for use in high density chip packages and a method of fabricating same |
US6217987B1 (en) * | 1996-11-20 | 2001-04-17 | Ibiden Co. Ltd. | Solder resist composition and printed circuit boards |
EP0844809A2 (en) | 1996-11-20 | 1998-05-27 | Ibiden Co, Ltd. | Solder resist composition and printed circuit boards |
JPH10163634A (en) | 1996-11-27 | 1998-06-19 | Kyocera Corp | Multilayer wiring board |
US6835895B1 (en) * | 1996-12-19 | 2004-12-28 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
JPH10200271A (en) | 1997-01-13 | 1998-07-31 | Kyocera Corp | Multilayer interconnection board |
JPH10261869A (en) | 1997-01-17 | 1998-09-29 | Ibiden Co Ltd | Multilayer printed wiring board |
JPH10335817A (en) | 1997-05-27 | 1998-12-18 | Kyocera Corp | Multilayered wiring board |
MY121310A (en) | 1997-10-14 | 2006-01-28 | Ibiden Co Ltd | Multilayer printed wiring board and its manufacturing method,and resin composition for filling through-hole |
US6376049B1 (en) * | 1997-10-14 | 2002-04-23 | Ibiden Co., Ltd. | Multilayer printed wiring board and its manufacturing method, and resin composition for filling through-hole |
US6392898B1 (en) * | 1997-10-17 | 2002-05-21 | Ibiden Co., Ltd. | Package substrate |
JPH11121933A (en) | 1997-10-17 | 1999-04-30 | Canon Inc | Multilayered printed wiring board, and printed wiring board mounted with electronic components |
US6523252B1 (en) * | 1997-10-22 | 2003-02-25 | Nokia Mobile Phones Limited | Coaxial cable, method for manufacturing a coaxial cable, and wireless communication device |
US20010011607A1 (en) * | 1997-12-26 | 2001-08-09 | Kiyokazu Moriizumi | Multilayer thin-film wiring board |
US6248657B1 (en) * | 1998-03-13 | 2001-06-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
US6512186B1 (en) * | 1998-06-26 | 2003-01-28 | Ibiden Co., Ltd. | Multilayer printed wiring board having a roughened inner conductor layer and production method thereof |
US6571467B2 (en) * | 1998-09-18 | 2003-06-03 | International Business Machines Corporation | Method for producing a doublesided wiring board |
US6046909A (en) * | 1998-11-16 | 2000-04-04 | Intel Corporation | Computer card with a printed circuit board with vias providing strength to the printed circuit board |
US20020112885A1 (en) * | 1999-02-10 | 2002-08-22 | Sinichi Hotta | Printed circuit board and method for manufacturing same |
US20030007332A1 (en) * | 1999-04-01 | 2003-01-09 | Yasuaki Seki | Insulating resin composition for multilayer printed-wiring board |
US6303871B1 (en) | 1999-06-11 | 2001-10-16 | Intel Corporation | Degassing hole design for olga trace impedance |
US6662442B1 (en) * | 1999-07-19 | 2003-12-16 | Nitto Denko Corporation | Process for manufacturing printed wiring board using metal plating techniques |
US20010004944A1 (en) * | 1999-12-14 | 2001-06-28 | Kei Nakamura | Double-sided circuit board and multilayer wiring board comprising the same and process for producing double-sided circuit board |
US6667235B2 (en) * | 1999-12-15 | 2003-12-23 | Shinko Electric Industries Co., Ltd. | Semiconductor device and manufacturing method therefor |
US6528145B1 (en) * | 2000-06-29 | 2003-03-04 | International Business Machines Corporation | Polymer and ceramic composite electronic substrates |
Non-Patent Citations (11)
Title |
---|
Microfilm of the specification and drawings annexed to the request of Japanese Utility Model Application No. 18148/1980 )Laid-open No. 119679/1981) (NEC Corporation ), Sep. 11, 1981 (Family: none). |
Microfilm of the specification and drawings annexed to the request of Japanese Utility Model Application No. 18148/1980)Laid-open No. 119679/1981) (NEC Corporation), Sep. 11, 1981 (Family: none). |
Patent Abstracts of Japan, JP 01-282888, Nov. 14, 1989. |
Patent Abstracts of Japan, JP 03-036791, Feb. 18, 1991. |
Patent Abstracts of Japan, JP 04-064279, Feb. 28, 1992. |
Patent Abstracts of Japan, JP 05-075258, Mar. 26, 1993. |
Patent Abstracts of Japan, JP 06-021611, Jan. 28, 1994. |
Patent Abstracts of Japan, JP 06-069660, Mar. 11, 1994. |
Patent Abstracts of Japan, JP 06-120659, Apr. 28, 1994. |
Patent Abstracts of Japan, JP 10-163634, Jun. 19, 1998. |
Patent Abstracts of Japan, JP 56-119679, Sep. 19, 1981. |
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Also Published As
Publication number | Publication date |
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US6613986B1 (en) | 2003-09-02 |
CN1318274A (en) | 2001-10-17 |
KR20010085811A (en) | 2001-09-07 |
KR20090059173A (en) | 2009-06-10 |
EP1137333B1 (en) | 2010-04-21 |
DE69942279D1 (en) | 2010-06-02 |
EP1868423A1 (en) | 2007-12-19 |
US7847318B2 (en) | 2010-12-07 |
MY141631A (en) | 2010-05-31 |
MY123224A (en) | 2006-05-31 |
KR20080024239A (en) | 2008-03-17 |
US20090173523A1 (en) | 2009-07-09 |
EP1137333A1 (en) | 2001-09-26 |
TW453146B (en) | 2001-09-01 |
US20030102151A1 (en) | 2003-06-05 |
KR20080023369A (en) | 2008-03-13 |
EP1137333A4 (en) | 2004-03-24 |
WO2000018202A1 (en) | 2000-03-30 |
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