US7659767B2 - Boost circuit and level shifter - Google Patents

Boost circuit and level shifter Download PDF

Info

Publication number
US7659767B2
US7659767B2 US12/194,348 US19434808A US7659767B2 US 7659767 B2 US7659767 B2 US 7659767B2 US 19434808 A US19434808 A US 19434808A US 7659767 B2 US7659767 B2 US 7659767B2
Authority
US
United States
Prior art keywords
drain
coupled
source
gate
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US12/194,348
Other versions
US20080303578A1 (en
Inventor
Yen-Wen Chen
Yen-Ynn Chou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Princeton Technology Corp
Original Assignee
Princeton Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Princeton Technology Corp filed Critical Princeton Technology Corp
Priority to US12/194,348 priority Critical patent/US7659767B2/en
Publication of US20080303578A1 publication Critical patent/US20080303578A1/en
Application granted granted Critical
Publication of US7659767B2 publication Critical patent/US7659767B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Definitions

  • the invention relates to a level shifter, and more particularly to a two-stage level shifter with a boost circuit.
  • the conventional voltage pull-up circuit is typically implemented by a level shifter.
  • the level shifter includes two input terminals respectively receiving an input signal and an inverted input signal.
  • the input terminal is electrically connected to the gate of a transistor. If the output current of the level shifter needs to be increased, the W/L ratio of the transistor coupled to the input terminal must be raised firstly, thus, the layout area of the level shifter will be increased.
  • the input positive voltage applied to the gate of the NMOS transistor must exceed a predetermined voltage level. If the input positive voltage applied to the gate of the NMOS transistor does not exceed the predetermined voltage level, the NMOS transistor can not be completely turned on and only outputs small output current. If the voltage level of the input signal applied to the level shift does not exceed a predetermined voltage level, the level shifter may be not properly driven.
  • a boost circuit comprising a first transistor, a second transistor, a capacitor module, a third transistor, a fourth transistor and a fifth transistor.
  • the first transistor has a first source, a first gate and a first drain, wherein the first source is coupled to a voltage source.
  • the second transistor has a second source, a second gate and a second drain, wherein the second drain is coupled to the first drain, the second source is grounded, and the second gate is coupled to the first gate to receive an input signal.
  • the capacitor module has a first terminal and a second terminal, and is controlled by a control signal to change a capacitance of the capacitor module for changing the discharge time of the capacitor module, wherein the first terminal is coupled to the first drain and the second drain.
  • the third transistor has a third source, a third gate and a third drain, wherein the third source is coupled to the voltage source, and the third gate is coupled to an output terminal.
  • the fourth transistor has a fourth source, a fourth gate and a fourth drain, wherein the fourth gate receives the input signal, the fourth source and the third drain are coupled to the second terminal of the capacitor module, and the fourth drain is coupled to the output terminal.
  • the fifth transistor has a fifth source, a fifth gate and a fifth drain, wherein the fifth gate receives the input signal, the fifth drain is coupled to the output terminal, and the fifth source is grounded.
  • a level shifter comprises a first boost circuit, an inverter, a second boost circuit and a level shift circuit.
  • the first boost circuit receives an input signal, and determines a first amplification factor of the input signal based on a control signal.
  • the inverter receives the input signal to generate an inverted input signal.
  • the second boost circuit is coupled to an output terminal of the inverter to receive the inverted input signal, and to determine a second amplification factor of the inverted input signal based on the control signal.
  • the level shift circuit has a first input terminal and a second input terminal respectively coupled to output terminals of the first boost circuit and second boost circuit to change the voltage level of output signals from the first boost circuit and second boost circuit to a first voltage level.
  • FIG. 1 is a circuit diagram of an embodiment of a boost circuit of the invention.
  • FIG. 2 shows an embodiment of the capacitor module 11 in FIG. 1 .
  • FIG. 3 is a circuit diagram of an embodiment of a level shifter in accordance with the invention.
  • FIG. 1 is a circuit diagram of an embodiment of a boost circuit of the invention.
  • the transistor T 1 has a first source, a first gate and a first drain, wherein the first source is coupled to a voltage source VDD.
  • the second transistor T 2 has a second source, a second gate and a second drain, wherein the second drain is coupled to the first drain, the second source is grounded, and the second gate is coupled to the first gate to receive an input signal Vin.
  • the capacitor module 11 has a first terminal and a second terminal, and is controlled by a control signal Cs to change a capacitance of the capacitor module for changing the discharge time of the capacitor module, wherein the first terminal is coupled to the first drain and the second drain.
  • the capacitor module 11 includes a first capacitor and a second capacitor, the first capacitor is further coupled to a switch device, and the first capacitor is connected in parallel to the second capacitor in response to the switch device is turned on based on the control signal.
  • the first capacitor and the second capacitor can be formed by transistors.
  • the third transistor T 3 has a third source, a third gate and a third drain, wherein the third source is coupled to the voltage source VDD, and the third gate is used for outputting an output signal Vout.
  • the fourth transistor T 4 has a fourth source a fourth gate and a fourth drain, wherein the fourth gate receives the input signal Vin, the fourth source and the third drain are coupled to the second terminal of the capacitor module 11 , and the fourth drain outputs the output signal Vout.
  • the fifth transistor T 5 has a fifth source, a fifth gate and a fifth drain, wherein the fifth gate receives the input signal Vin, the fifth drain outputs the output signal Vout, and the fifth source is grounded.
  • the transistor T 5 When the input signal Vin is at high voltage level, the transistor T 5 is turned on and the voltage level of the output signal is 0.
  • the voltage level of the third drain is at VDD because the capacitor module 11 is charged in a previous cycle.
  • the capacitor module 11 When the input signal Vin is at low voltage level, the capacitor module 11 is charged by the voltage VDD and the voltage level of the third drain is pulled up to 2VDD. Because the input signal Vin is at low voltage level, the transistor T 5 and the transistor T 4 are turned on, thus, the voltage level of the output signal is 2VDD.
  • the capacitance and the discharge time of the capacitor module 11 can be changed by the control signal Cs.
  • FIG. 2 shows an embodiment of the capacitor module 11 in FIG. 1 .
  • the sources and drains of transistor T 6 , T 7 and T 8 are coupled to the first terminal of the capacitor module 11 .
  • the gates of the transistor T 7 and transistor T 8 are coupled to the second terminal of the capacitor module 11 .
  • the gate of transistor T 6 is coupled to a transmission gate 22 .
  • the transmission gate 22 is controlled by two control signals, control signal Cs and the inverted control signal from inverter 21 . When the transmission gate 22 is turned off, the capacitance of the capacitor module 11 is determined by the capacitor formed by the transistors T 7 and T 8 .
  • the capacitance of the capacitor module 11 is determined by the capacitor formed by the transistors T 6 , T 7 and T 8 . According to the described architecture of capacitor module 11 , the capacitance and the discharge time of the capacitor module 11 can be changed by the control signal Cs.
  • FIG. 3 is a circuit diagram of an embodiment of a level shifter in accordance with the invention.
  • the first boost circuit 31 coupled to the first voltage source VDD 1 , receives the input signal Vin and determines the first amplification factor for the input signal Vin based on the control signal Se 1 .
  • the second boost circuit 32 is coupled to the first voltage source VDD 1 and the output terminal of the inverter 33 to receive the inverted input signal Vin and to determine the second amplification factor for the inverted input signal Vin based on the control signal Se 1 .
  • Embodiments of the first boost circuit 31 and the second boost circuit 32 are illustrated in FIG. 1 .
  • the transistor T 11 has a source, a gate and a drain, wherein the source of the transistor T 11 is coupled to the second voltage source VDD 2 , the drain of the transistor T 11 is coupled to one terminal of the resistor R 1 .
  • the transistor T 12 has a source, a gate and a drain, wherein the source of the transistor T 12 is coupled to the second voltage source VDD 2 , the drain of the transistor T 12 is coupled to one terminal of the resistor R 2 , and the gate of the transistor T 12 is coupled to another terminal of the resistor R 1 .
  • the transistor T 13 has a source, a gate and a drain, wherein the drain of the transistor T 13 is coupled to the gate of the transistor T 12 , the gate of the transistor T 13 receives the output signal of the first boost circuit 31 , and the source of the transistor T 13 is grounded.
  • the transistor T 14 has a source, a gate and a drain, wherein the drain of the transistor T 14 is coupled to the gate of the transistor T 11 , the gate of the transistor T 14 receives the output signal of the second boost circuit 32 , and the source of the transistor T 14 is grounded.
  • the transistor T 15 has a source, a gate and a drain, wherein the source of the transistor T 15 is coupled to the second voltage source VDD 2 , and the gate of the transistor T 15 is coupled to the gate of the transistor T 11 .
  • the transistor T 16 has a source, a gate and a drain, wherein the drain of the transistor T 16 is coupled to the drain of the transistor T 15 , the gate of the transistor T 16 is coupled to the gate of the transistor T 11 , and the source of the transistor T 16 is grounded.
  • the transistor T 17 has a source, a gate and a drain, wherein the source of the transistor T 17 is coupled to the second voltage source VDD 2 , the gate of the transistor T 17 is coupled to the drains of the transistors T 15 and T 16 , the drain of the transistor T 17 is coupled to one terminal of the resistor R 3 , and outputs the output signal Vout.
  • the transistor T 18 has a source, a gate and a drain, wherein the source of the transistor T 18 is coupled to the second voltage source VDD 2 , and the gate of the transistor T 18 is coupled to the gate of the transistor T 11 .
  • the transistor T 19 has a source, a gate and a drain, wherein the drain of the transistor T 19 is coupled to the drain of the transistor T 18 , the gate of the transistor T 19 is coupled to the gate of the transistor T 11 , and the source of the transistor T 19 is grounded.
  • the transistor T 20 has a source, a gate and a drain, wherein the gate of the transistor T 20 is coupled to the drains of the transistors T 18 and T 19 , the drain of the transistor T 20 is coupled to another terminal of the resistor R 3 , and the source of the transistor T 20 is grounded.
  • the cathode of the diode 34 is coupled between the drain of the transistor T 20 and the resistor R 3 , and the anode of the diode 34 is grounded.
  • the output signal of the second boost circuit 32 When the output signal of the second boost circuit 32 is at low voltage level and the transistors T 12 and T 13 are turned on, the transistors T 16 and T 17 are turned on, and the voltage level of the output signal Vout is VDD 2 .
  • the voltage level of the input signal Vin is pulled up to 2VDD 1 by the first boost circuit 31 or the second boost circuit 32 , and a voltage shifting circuit then pulls up the voltage level of the output signal of the first boost circuit 31 or the second boost circuit 32 from 2VDD 1 to VDD 2 .
  • the voltage shifting circuit comprises diode 34 and transistors T 11 to T 20 , wherein the gates of the transistor T 13 and T 14 denote the input terminals of the voltage shifting circuit, and the drain of the transistor T 17 outputs an output signal.
  • the layout area of the level shifter shown in FIG. 3 increases due to the first boost circuit 31 and the second boost circuit 32 , the performance of level shifter also significantly increases.
  • the first boost circuit 31 and the second boost circuit 32 are the low operating voltage elements, thus, the total power consumption increases only slightly. Further, the level shifter shown in FIG. 3 avoids DC current generation and breakdown voltage issues.

Abstract

A level shifter including a first boost circuit, an inverter, a second boost circuit and a level shift circuit is disclosed. The first boost circuit receives an input signal, and a first amplification factor for the input signal is determined based on a control signal. The inverter receives the input signal to generate an inverted input signal. The second boost circuit is coupled to an output terminal of the inverter to receive the inverted input signal, and a second amplification factor for the inverted input signal is determined based on the control signal. The level shift circuit has a first input terminal and a second input terminal respectively coupled to output terminals of the first boost circuit and second boost circuit to change the voltage level of output signals from the first boost circuit and second boost circuit to a first voltage level.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a Divisional of co-pending application Ser. No. 11/727,556, filed on Mar. 27, 2007, and for which priority is claimed under 35 U.S.C. §120; and this application claims priority of Application No. 095145330 filed in Taiwan, R.O.C. on Dec. 6, 2006 under 35 U.S.C. §119; the entire contents of all of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a level shifter, and more particularly to a two-stage level shifter with a boost circuit.
2. Brief Description of the Related Art
The conventional voltage pull-up circuit is typically implemented by a level shifter. The level shifter includes two input terminals respectively receiving an input signal and an inverted input signal. In a typical level shifter, the input terminal is electrically connected to the gate of a transistor. If the output current of the level shifter needs to be increased, the W/L ratio of the transistor coupled to the input terminal must be raised firstly, thus, the layout area of the level shifter will be increased. To completely turn on an NMOS transistor, the input positive voltage applied to the gate of the NMOS transistor must exceed a predetermined voltage level. If the input positive voltage applied to the gate of the NMOS transistor does not exceed the predetermined voltage level, the NMOS transistor can not be completely turned on and only outputs small output current. If the voltage level of the input signal applied to the level shift does not exceed a predetermined voltage level, the level shifter may be not properly driven.
BRIEF SUMMARY OF THE INVENTION
In one aspect of the invention, a boost circuit comprising a first transistor, a second transistor, a capacitor module, a third transistor, a fourth transistor and a fifth transistor is provided. The first transistor has a first source, a first gate and a first drain, wherein the first source is coupled to a voltage source. The second transistor has a second source, a second gate and a second drain, wherein the second drain is coupled to the first drain, the second source is grounded, and the second gate is coupled to the first gate to receive an input signal. The capacitor module has a first terminal and a second terminal, and is controlled by a control signal to change a capacitance of the capacitor module for changing the discharge time of the capacitor module, wherein the first terminal is coupled to the first drain and the second drain. The third transistor has a third source, a third gate and a third drain, wherein the third source is coupled to the voltage source, and the third gate is coupled to an output terminal. The fourth transistor has a fourth source, a fourth gate and a fourth drain, wherein the fourth gate receives the input signal, the fourth source and the third drain are coupled to the second terminal of the capacitor module, and the fourth drain is coupled to the output terminal. The fifth transistor has a fifth source, a fifth gate and a fifth drain, wherein the fifth gate receives the input signal, the fifth drain is coupled to the output terminal, and the fifth source is grounded.
In another aspect of the invention, a level shifter comprises a first boost circuit, an inverter, a second boost circuit and a level shift circuit is provided. The first boost circuit receives an input signal, and determines a first amplification factor of the input signal based on a control signal. The inverter receives the input signal to generate an inverted input signal. The second boost circuit is coupled to an output terminal of the inverter to receive the inverted input signal, and to determine a second amplification factor of the inverted input signal based on the control signal. The level shift circuit has a first input terminal and a second input terminal respectively coupled to output terminals of the first boost circuit and second boost circuit to change the voltage level of output signals from the first boost circuit and second boost circuit to a first voltage level.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the subsequent detailed description and the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
FIG. 1 is a circuit diagram of an embodiment of a boost circuit of the invention.
FIG. 2 shows an embodiment of the capacitor module 11 in FIG. 1.
FIG. 3 is a circuit diagram of an embodiment of a level shifter in accordance with the invention.
 DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 1 is a circuit diagram of an embodiment of a boost circuit of the invention. The transistor T1 has a first source, a first gate and a first drain, wherein the first source is coupled to a voltage source VDD. The second transistor T2 has a second source, a second gate and a second drain, wherein the second drain is coupled to the first drain, the second source is grounded, and the second gate is coupled to the first gate to receive an input signal Vin. The capacitor module 11 has a first terminal and a second terminal, and is controlled by a control signal Cs to change a capacitance of the capacitor module for changing the discharge time of the capacitor module, wherein the first terminal is coupled to the first drain and the second drain. The capacitor module 11 includes a first capacitor and a second capacitor, the first capacitor is further coupled to a switch device, and the first capacitor is connected in parallel to the second capacitor in response to the switch device is turned on based on the control signal. In one embodiment, the first capacitor and the second capacitor can be formed by transistors. The third transistor T3 has a third source, a third gate and a third drain, wherein the third source is coupled to the voltage source VDD, and the third gate is used for outputting an output signal Vout. The fourth transistor T4 has a fourth source a fourth gate and a fourth drain, wherein the fourth gate receives the input signal Vin, the fourth source and the third drain are coupled to the second terminal of the capacitor module 11, and the fourth drain outputs the output signal Vout. The fifth transistor T5 has a fifth source, a fifth gate and a fifth drain, wherein the fifth gate receives the input signal Vin, the fifth drain outputs the output signal Vout, and the fifth source is grounded.
When the input signal Vin is at high voltage level, the transistor T5 is turned on and the voltage level of the output signal is 0. The voltage level of the third drain is at VDD because the capacitor module 11 is charged in a previous cycle. When the input signal Vin is at low voltage level, the capacitor module 11 is charged by the voltage VDD and the voltage level of the third drain is pulled up to 2VDD. Because the input signal Vin is at low voltage level, the transistor T5 and the transistor T4 are turned on, thus, the voltage level of the output signal is 2VDD. In this embodiment, the capacitance and the discharge time of the capacitor module 11 can be changed by the control signal Cs.
For further illustration, please refer to FIG. 2. FIG. 2 shows an embodiment of the capacitor module 11 in FIG. 1. The sources and drains of transistor T6, T7 and T8 are coupled to the first terminal of the capacitor module 11. The gates of the transistor T7 and transistor T8 are coupled to the second terminal of the capacitor module 11. The gate of transistor T6 is coupled to a transmission gate 22. The transmission gate 22 is controlled by two control signals, control signal Cs and the inverted control signal from inverter 21. When the transmission gate 22 is turned off, the capacitance of the capacitor module 11 is determined by the capacitor formed by the transistors T7 and T8. When the transmission gate 22 is turned on, the capacitance of the capacitor module 11 is determined by the capacitor formed by the transistors T6, T7 and T8. According to the described architecture of capacitor module 11, the capacitance and the discharge time of the capacitor module 11 can be changed by the control signal Cs.
FIG. 3 is a circuit diagram of an embodiment of a level shifter in accordance with the invention. The first boost circuit 31, coupled to the first voltage source VDD1, receives the input signal Vin and determines the first amplification factor for the input signal Vin based on the control signal Se1. The second boost circuit 32 is coupled to the first voltage source VDD1 and the output terminal of the inverter 33 to receive the inverted input signal Vin and to determine the second amplification factor for the inverted input signal Vin based on the control signal Se1. Embodiments of the first boost circuit 31 and the second boost circuit 32 are illustrated in FIG. 1. The transistor T11 has a source, a gate and a drain, wherein the source of the transistor T11 is coupled to the second voltage source VDD2, the drain of the transistor T11 is coupled to one terminal of the resistor R1. The transistor T12 has a source, a gate and a drain, wherein the source of the transistor T12 is coupled to the second voltage source VDD2, the drain of the transistor T12 is coupled to one terminal of the resistor R2, and the gate of the transistor T12 is coupled to another terminal of the resistor R1. The transistor T13 has a source, a gate and a drain, wherein the drain of the transistor T13 is coupled to the gate of the transistor T12, the gate of the transistor T13 receives the output signal of the first boost circuit 31, and the source of the transistor T13 is grounded. The transistor T14 has a source, a gate and a drain, wherein the drain of the transistor T14 is coupled to the gate of the transistor T11, the gate of the transistor T14 receives the output signal of the second boost circuit 32, and the source of the transistor T14 is grounded. The transistor T15 has a source, a gate and a drain, wherein the source of the transistor T15 is coupled to the second voltage source VDD2, and the gate of the transistor T15 is coupled to the gate of the transistor T11. The transistor T16 has a source, a gate and a drain, wherein the drain of the transistor T16 is coupled to the drain of the transistor T15, the gate of the transistor T16 is coupled to the gate of the transistor T11, and the source of the transistor T16 is grounded. The transistor T17 has a source, a gate and a drain, wherein the source of the transistor T17 is coupled to the second voltage source VDD2, the gate of the transistor T17 is coupled to the drains of the transistors T15 and T16, the drain of the transistor T17 is coupled to one terminal of the resistor R3, and outputs the output signal Vout. The transistor T18 has a source, a gate and a drain, wherein the source of the transistor T18 is coupled to the second voltage source VDD2, and the gate of the transistor T18 is coupled to the gate of the transistor T11. The transistor T19 has a source, a gate and a drain, wherein the drain of the transistor T19 is coupled to the drain of the transistor T18, the gate of the transistor T19 is coupled to the gate of the transistor T11, and the source of the transistor T19 is grounded. The transistor T20 has a source, a gate and a drain, wherein the gate of the transistor T20 is coupled to the drains of the transistors T18 and T19, the drain of the transistor T20 is coupled to another terminal of the resistor R3, and the source of the transistor T20 is grounded. The cathode of the diode 34 is coupled between the drain of the transistor T20 and the resistor R3, and the anode of the diode 34 is grounded.
When the output signal of the second boost circuit 32 is at low voltage level and the transistors T12 and T13 are turned on, the transistors T16 and T17 are turned on, and the voltage level of the output signal Vout is VDD2. In FIG. 3, the voltage level of the input signal Vin is pulled up to 2VDD1 by the first boost circuit 31 or the second boost circuit 32, and a voltage shifting circuit then pulls up the voltage level of the output signal of the first boost circuit 31 or the second boost circuit 32 from 2VDD1 to VDD2. In this embodiment, the voltage shifting circuit comprises diode 34 and transistors T11 to T20, wherein the gates of the transistor T13 and T14 denote the input terminals of the voltage shifting circuit, and the drain of the transistor T17 outputs an output signal. Although the layout area of the level shifter shown in FIG. 3 increases due to the first boost circuit 31 and the second boost circuit 32, the performance of level shifter also significantly increases. Furthermore, the first boost circuit 31 and the second boost circuit 32 are the low operating voltage elements, thus, the total power consumption increases only slightly. Further, the level shifter shown in FIG. 3 avoids DC current generation and breakdown voltage issues.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (6)

1. A level shifter, comprising:
a first boost circuit for receiving an input signal and determining a first amplification factor of the input signal based on a control signal, wherein the first boost circuit is powered by a first voltage source, and the first amplification factor of the input signal is dependent on the voltage level of the first voltage source;
a first inverter for receiving the input signal to generate an inverted input signal;
a second boost circuit coupled to an output terminal of the inverter to receive the inverted input signal and to determine a second amplification factor of the inverted input signal based on the control signal, wherein the second boost circuit is powered by the first voltage source, and the second amplification factor is dependent on the voltage level of the first voltage source; and
a level shift circuit powered by a second voltage source with the voltage level higher than that of the first voltage source, wherein the level shift circuit has a first input terminal and a second input terminal respectively coupled to output terminals of the first boost circuit and second boost circuit to generate an output signal according to output signals from the first boost circuit and second boost circuit, wherein a level shift of the output of the level shift circuit is dependent on the first voltage source and the second voltage source.
2. The level shifter as claimed in claim 1, wherein each of the first and second boost circuits comprises:
a first transistor, having a first source, a first gate and a first drain, wherein the first source is coupled to the first voltage source and the first gate receives the input signal;
a second transistor, having a second source, a second gate and a second drain, wherein the second source is coupled to ground, the second gate is coupled to the first gate and the second drain is coupled to the first drain;
a third transistor, having a third source, a third gate and a third drain, wherein the third source is coupled to the first voltage source;
a fourth transistor, having a fourth source, a fourth gate and a fourth drain, wherein the fourth source is coupled to the third drain;
a fifth transistor, having a fifth source, a fifth gate and a fifth drain, wherein the fifth source is coupled to the ground, the fifth gate receives the input signal and is coupled to the fourth gate, and the fifth drain is coupled to the fourth drain and the third gate; and
a capacitor module, coupled between the first drain and the third drain and controlled by the control signal,
wherein the third gate works as an output terminal of the boost circuit.
3. The level shift as claimed in claim 2, wherein the capacitor module comprises:
a sixth transistor, having a sixth source, a sixth gate and a sixth drain, wherein the sixth source and the sixth drain are coupled together to an input terminal of the capacitor module;
a seventh transistor, having a seventh source, a seventh gate and a seventh drain, wherein the seventh source and the seventh drain are coupled together to the input terminal of the capacitor module, and the seventh gate is coupled to the output terminal of the capacitor module;
a eighth transistor, having a eighth source, a eighth gate and a eighth drain, wherein the eighth source and the eighth drain are coupled together to the input terminal of the capacitor module and the eighth gate is coupled to the output terminal of the capacitor module; and
a transmission gate, coupled between the sixth gate and the output terminal of the capacitor module, and controlled by the control signal and an inverse of the control signal.
4. The level shifter as claimed in claim 1, wherein the level shift circuit further comprises:
a eleventh transistor, having a eleventh source, a eleventh gate and a eleventh drain, wherein the eleventh source is coupled to the second voltage source;
a twelfth transistor, having a twelfth source, a twelfth gate and a twelfth drain, wherein the twelfth source is coupled to the second voltage source;
a thirteenth transistor, having a thirteenth drain, a thirteenth gate and a thirteenth source, wherein the thirteenth drain is coupled to the twelfth gate and the eleventh drain, the thirteenth gate is coupled to the output terminal of the first boost circuit, and the thirteenth source is coupled to ground;
a fourteenth transistor, having a fourteenth drain, a fourteenth gate and a fourteenth source, wherein the fourteenth drain is coupled to the eleventh gate and the twelfth drain, the fourteenth gate is coupled to the output terminal of the second boost circuit, and the fourteenth source is coupled to the ground;
a second inverter, powered by the second voltage source, having an input terminal coupled to the fourteenth drain, and having an output terminal;
a third inverter, powered by second voltage source, having an input terminal coupled to the fourteenth drain, and having an output terminal;
a seventeenth transistor, having a seventeenth source, a seventeenth gate and a seventeenth drain, wherein the seventeenth source is coupled to the second voltage source, the seventeenth gate is coupled to the output terminal of the second inverter;
a twentieth transistor, having a twentieth drain, a twentieth gate and a twentieth source, wherein the twentieth drain is coupled to the seventeenth drain, the twentieth gate is coupled to the output terminal of the third inverter, and the twentieth source is coupled to the ground; and
a diode, having an anode and a cathode, wherein the anode is coupled to the ground and the cathode is coupled to the twentieth drain,
wherein the seventeenth drain provides the output signal of the level shift circuit.
5. The level shifter as claimed in claim 4, wherein the level shift circuit further comprises:
a first resistor, coupled between the eleventh drain and the thirteenth drain; and
a second resistor, coupled between the twelfth drain and the fourteenth drain.
6. The level shifter as claimed in claim 2, wherein the level shift circuit further comprises:
a third resistor, coupled between the seventeenth drain and the twentieth drain.
US12/194,348 2006-12-06 2008-08-19 Boost circuit and level shifter Active US7659767B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/194,348 US7659767B2 (en) 2006-12-06 2008-08-19 Boost circuit and level shifter

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
TW095145330A TWI330922B (en) 2006-12-06 2006-12-06 Boost circuit and level shifter
TW95145330A 2006-12-06
TW095145330 2006-12-06
US11/727,556 US20080136487A1 (en) 2006-12-06 2007-03-27 Boost circuit and level shifter
US12/194,348 US7659767B2 (en) 2006-12-06 2008-08-19 Boost circuit and level shifter

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/727,556 Division US20080136487A1 (en) 2006-12-06 2007-03-27 Boost circuit and level shifter

Publications (2)

Publication Number Publication Date
US20080303578A1 US20080303578A1 (en) 2008-12-11
US7659767B2 true US7659767B2 (en) 2010-02-09

Family

ID=39497240

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/727,556 Abandoned US20080136487A1 (en) 2006-12-06 2007-03-27 Boost circuit and level shifter
US12/194,348 Active US7659767B2 (en) 2006-12-06 2008-08-19 Boost circuit and level shifter

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/727,556 Abandoned US20080136487A1 (en) 2006-12-06 2007-03-27 Boost circuit and level shifter

Country Status (3)

Country Link
US (2) US20080136487A1 (en)
JP (2) JP2008148544A (en)
TW (1) TWI330922B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100244923A1 (en) * 2006-07-20 2010-09-30 Chang-Ho Do Semiconductor device
US20120229114A1 (en) * 2011-03-07 2012-09-13 Chen-Hao Yang Dc/dc boost converter
US9800246B2 (en) * 2015-09-18 2017-10-24 Qualcomm Incorporated Level shifter applicable to low voltage domain to high voltage domain conversion

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200525869A (en) 2004-01-28 2005-08-01 Renesas Tech Corp Switching power supply and semiconductor IC
US20080297224A1 (en) * 2007-06-01 2008-12-04 Texas Instruments Incorporated Minimizing Static Current Consumption While Providing Higher-Swing Output Signals when Components of an Integrated Circuit are Fabricated using a Lower-Voltage Process
US8816748B2 (en) 2012-06-12 2014-08-26 Lsi Corporation Jitter reduction in high speed low core voltage level shifter
US8873270B2 (en) * 2012-12-14 2014-10-28 Palo Alto Research Center Incorporated Pulse generator and ferroelectric memory circuit
KR102048254B1 (en) * 2013-04-11 2020-01-08 에스케이하이닉스 주식회사 Data output circuit and operating method thereof
CN108736878B (en) 2017-04-13 2022-01-25 华邦电子股份有限公司 Voltage level shifter
CN112286276B (en) * 2020-11-05 2022-04-05 中国电子科技集团公司第十四研究所 Positive and negative voltage control circuit based on MOS pipe
CN115240597B (en) * 2022-09-20 2023-01-10 惠科股份有限公司 Pixel circuit, display panel and display device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020153934A1 (en) * 2001-04-18 2002-10-24 Samsung Electronics Co., Ltd. On-chip system with voltage level converting device for preventing leakage current due to voltage level difference
US7180355B2 (en) * 2004-06-21 2007-02-20 Oki Electric Industry Co., Ltd. Level shifter circuit with stress test function
US7368970B2 (en) * 2005-06-29 2008-05-06 Sunplus Technology Co., Ltd. Level shifter circuit
US20080265972A1 (en) * 2007-04-24 2008-10-30 Emi Nakamura Output circuit and multi-output circuit
US7511709B2 (en) * 2003-07-18 2009-03-31 Semiconductor Energy Laboratory Co., Ltd. Display device
US7514960B2 (en) * 2005-04-06 2009-04-07 Nec Electronics Corporation Level shifter circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3457435A (en) * 1965-12-21 1969-07-22 Rca Corp Complementary field-effect transistor transmission gate
JPH07105447B2 (en) * 1988-12-15 1995-11-13 株式会社東芝 Transmission gate
JPH044609A (en) * 1990-04-23 1992-01-09 Nec Corp Output buffer circuit
JPH08330938A (en) * 1995-06-02 1996-12-13 Matsushita Electric Ind Co Ltd Level shift circuit
US6191642B1 (en) * 1999-03-30 2001-02-20 Silicon Storage Technology, Inc. Charge pump circuit
JP2001273784A (en) * 2000-03-29 2001-10-05 Mitsubishi Electric Corp Boosting circuit and semiconductor memory
JP3696125B2 (en) * 2000-05-24 2005-09-14 株式会社東芝 Potential detection circuit and semiconductor integrated circuit
US6356137B1 (en) * 2000-06-26 2002-03-12 Fairchild Semiconductor Corporation Voltage boost circuit with low power supply voltage
JP2002100193A (en) * 2000-09-25 2002-04-05 Toshiba Microelectronics Corp Boosting circuit
JP4257064B2 (en) * 2002-02-21 2009-04-22 エルピーダメモリ株式会社 Boosted potential generation circuit and control method
JPWO2004030191A1 (en) * 2002-09-27 2006-01-26 株式会社日立製作所 Semiconductor integrated circuit device
US7920017B2 (en) * 2004-12-16 2011-04-05 Analog Devices, Inc. Programmable clock booster system
US7218165B1 (en) * 2005-12-27 2007-05-15 Ememory Technology Inc. Boost circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020153934A1 (en) * 2001-04-18 2002-10-24 Samsung Electronics Co., Ltd. On-chip system with voltage level converting device for preventing leakage current due to voltage level difference
US7511709B2 (en) * 2003-07-18 2009-03-31 Semiconductor Energy Laboratory Co., Ltd. Display device
US7180355B2 (en) * 2004-06-21 2007-02-20 Oki Electric Industry Co., Ltd. Level shifter circuit with stress test function
US7514960B2 (en) * 2005-04-06 2009-04-07 Nec Electronics Corporation Level shifter circuit
US7368970B2 (en) * 2005-06-29 2008-05-06 Sunplus Technology Co., Ltd. Level shifter circuit
US20080265972A1 (en) * 2007-04-24 2008-10-30 Emi Nakamura Output circuit and multi-output circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100244923A1 (en) * 2006-07-20 2010-09-30 Chang-Ho Do Semiconductor device
US7940109B2 (en) * 2006-07-20 2011-05-10 Hynix Semiconductor Inc. Semiconductor device
US20120229114A1 (en) * 2011-03-07 2012-09-13 Chen-Hao Yang Dc/dc boost converter
US8513932B2 (en) * 2011-03-07 2013-08-20 Au Optronics Corp. DC/DC boost converter
US9800246B2 (en) * 2015-09-18 2017-10-24 Qualcomm Incorporated Level shifter applicable to low voltage domain to high voltage domain conversion

Also Published As

Publication number Publication date
US20080303578A1 (en) 2008-12-11
JP2008148544A (en) 2008-06-26
US20080136487A1 (en) 2008-06-12
JP2010279246A (en) 2010-12-09
TWI330922B (en) 2010-09-21
JP5236699B2 (en) 2013-07-17
TW200826445A (en) 2008-06-16

Similar Documents

Publication Publication Date Title
US7659767B2 (en) Boost circuit and level shifter
US6812782B2 (en) Switch mode converter that allows 100% duty cycle on gate driver
US7511560B2 (en) Charge pump circuit
US7009424B2 (en) Single supply level shifter
US20060220727A1 (en) Electronic switch and operational method for transistor
US7924080B2 (en) Level shifter circuit
CN1365540A (en) Fast high voltage level shifter with gate oxide protection
US7446564B2 (en) Level shifter
US6850090B2 (en) Level shifter
KR20020019390A (en) Semiconductor integrated circuit device
US20080157844A1 (en) Time delay circuit
US8379009B2 (en) Booster power supply circuit that boosts input voltage
US7518429B2 (en) Delay circuit
US7969217B2 (en) Output buffer with slew-rate enhancement output stage
US6975153B2 (en) Low power input with hysteresis circuit and methods therefor
US8963583B2 (en) Voltage level converter and RF switching driver apparatus using the same
US10630268B2 (en) Voltage level shifter circuit
JP2010021818A (en) Multifunctional driver circuit
US11283441B2 (en) Device for charging and discharging a capacitor
US20080143430A1 (en) Output signal driving circuit and method of driving output signal
CN115865074B (en) Level conversion circuit, radio frequency switch control circuit and radio frequency front end module
CN106249453B (en) Low-power source electrode driving circuit
US7459953B1 (en) Voltage adjusting circuit
US9124224B2 (en) Power generating circuit and switching circuit
US8044700B2 (en) Systems including level shifter having voltage distributor

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2553); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

Year of fee payment: 12