US7673221B2 - Optimal bit allocation system for Reed-Solomon coded data - Google Patents
Optimal bit allocation system for Reed-Solomon coded data Download PDFInfo
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- US7673221B2 US7673221B2 US10/046,639 US4663901A US7673221B2 US 7673221 B2 US7673221 B2 US 7673221B2 US 4663901 A US4663901 A US 4663901A US 7673221 B2 US7673221 B2 US 7673221B2
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- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004590 computer program Methods 0.000 description 3
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
- H04L1/006—Trellis-coded modulation
Definitions
- the present invention relates generally to a method and apparatus for providing a forward error correction scheme for data transmission and specifically to an improved method for selecting error correction parameters.
- DSL Digital Subscriber Line
- POTS Plain Old Telephone Service
- ADSL Asymmetric DSL
- DMT Discrete Multi-Tone
- an error-correcting code such as the Reed-Solomon (RS) code is used.
- RS Reed-Solomon
- n code-word length
- r redundant, or parity, length
- this difficulty is not confined to DSL, but also applies to other communications technologies, such as cable modems, CD and DVD players, digital audio and broadcast, HDTV/Digital TV, data storage, wireless communications, wireless enabled personal digital assistants, digital satellite communication and broadcast, and Redundant Array of Independent Disk (RAID) controllers with fault tolerance.
- other communications technologies such as cable modems, CD and DVD players, digital audio and broadcast, HDTV/Digital TV, data storage, wireless communications, wireless enabled personal digital assistants, digital satellite communication and broadcast, and Redundant Array of Independent Disk (RAID) controllers with fault tolerance.
- an iterative method for dynamically determining parameters for a forward error correction (FEC) coding scheme for optimizing data transmission in a specific environment.
- a specific method comprises the steps of establishing a relationship between the FEC parameters and a coding gain; initializing the coding gain to a minimum predetermined value; using the relationship between the parameters and the coding gain to determine an intermediate set of parameters for providing a preferred result for the coding gain; incrementing the value of the coding gain by a predetermined amount; repeating the previous steps until the coding gain reaches a predefined maximum value; and determining a preferred set of parameters from the intermediate sets of parameters, wherein the preferred set of parameters provides the forward error correction scheme with an optimal set of values for balancing code length and error rate.
- a Reed-Solomon code is employed.
- FIG. 1 is a block diagram of a Reed-Solomon code word
- FIG. 2 is a flowchart illustrating a bit allocation scheme
- FIG. 3 is a flowchart illustrating an alternate bit allocation scheme
- FIG. 4 is a flowchart illustrating yet an alternate bit allocation scheme
- FIG. 5 is a flowchart illustrating yet an alternate bit allocation scheme
- FIG. 6 is a block diagram of an ADSL modem implementing the processes of FIGS. 2-5 .
- a block diagram of a code word is illustrated generally by numeral 100 .
- a Reed-Solomon (RS) code is specified as RS (n,r), where n is the code length (also referred to as the size) of the code word, in symbols, and r is a number of redundant symbols in the code word. Therefore, the total number of information symbols is n-r.
- coding gain refers to the difference in power that the non-error correcting system would require to transmit data of a specified bit error rate as compared to the power required by the error correcting system.
- the following describes a bit allocation process for RS coded data.
- the process determines the RS code that best maximizes the transmitted data rate and minimizes the transmitted power.
- Other constraints such as impulse noise protection and maximum latency, are included as well.
- a flowchart illustrating the steps of the process is illustrated generally by numeral 200 .
- a gross coding gain G of the RS code is pre-calculated for different values of code-word length n and redundant length r.
- a relationship between the gain G, the code word length n, and the redundant length r is established and recorded.
- the relationship is recorded either as a table or represented by a mathematical expression, such as a polynomial approximation. If a table is used for representing the relationship, the row/column entries are code word length n and redundant length r, and the table content is the gross coding gain of the RS code for the associated code word length n and redundant length r. If a polynomial expression is used for representing the relationship, the gross coding gain can be calculated as a function of the code word length n and redundant length r.
- a total number of bits that can be transmitted over all DMT tones for one DMT symbol when RS code is not used is calculated using the following equation:
- SNR k is a signal-to-noise ratio (SNR) for a k th tone
- ⁇ is an energy gap associated with quadrature amplitude modulation (QAM) and a required bit error rate (BER)
- BER bit error rate
- ⁇ is a required margin for guaranteeing a BER performance with some noise tolerance
- M is the number of DMT tones used over one DMT symbol.
- a total number of bits b that can be transmitted over all tones of one DMT symbol is calculated using the following equation:
- B the integer portion of b divided by B is used because for G.992. 1 and G.992.2 compliant modems, the number of bits that a DMT symbol can carry is restricted to a multiple of eight.
- the DMT symbol can carry an integer number of bytes.
- n BS
- the number of symbols S comprises the set S ⁇ 1,2,4,8,16 ⁇ ).
- the number of redundant bytes r comprises the set r ⁇ 4,8,16 ⁇ .
- the number of redundant bytes is r, where r ⁇ 2,4,6,8,10,12,14,16 ⁇ ).
- the gross coding gain is obtained either by look-up table or by mathematical calculation.
- the table or mathematical function is obtained from step 202 .
- the code pair RS (n, r) having the largest number of information bytes per symbol B inf (G) available is selected as the best code pair B inf — max — local (G).
- the best code pair B inf — max — local (G) for each iteration has a corresponding gross coding gain G and code pair RS (n, r).
- the values for G, B inf — max — local (G) and the pair RS (n, r) are stored in a memory.
- the selection of S and r is limited by those factors. For example, if protection against an error burst longer than P bytes is desired, the constraint to be used is r*D/2>P, where D is an interleaver depth of an inner interleaver associated with the RS code. If a maximum latency of the system is to be less than L max ms, then the constraint to be used is
- the value of the gross coding gain G is incremented by ⁇ G. Steps 208 through 212 are repeated until the gross coding gain G is greater than or equal to a maximum gross coding gain value G max .
- the maximum gross coding gain G max is the maximum gross coding gain for all possible values of the code word length n and redundant length r.
- step 216 once the gross coding gain has equaled or exceeded the maximum gross coding gain G max , the largest value for the number of information bytes per symbol B inf (G) is found for all values of G. That is, for all values of the gross coding gain G from G min to G max with step size ⁇ G, the values of B inf — max — local (G) are compared. The code pair RS (n, r) having the largest number of information bytes per symbol B inf — max associated with it is selected.
- the largest number of bytes per symbol B inf — max for a gross coding gain between G min and G max is the maximum number of information bytes that can be transmitted over one DMT symbol, and its associated code pair RS (n, r) are the best parameters to support it.
- a final step 218 compares the largest number of bytes per symbol B inf — max with the maximum number of bytes per symbol B 0 had the RS code not been used. This comparison ensures that the RS code improves the capacity of the transmission. If the largest number of bytes per symbol B inf — max is less than B 0 , then the RS code should not be used.
- trellis-coded modulation is used over all tones of one DMT symbol.
- the pre-calculated gross coding gain is the gross coding gain of the RS code over TCM QAM, not conventional QAM. Therefore, the coding gain from TCM needs to be included in the calculation of number of bits per DMT symbol in Equations (1) and (2).
- the table for RS coding over QAM differs from the table to be used for RS coding over TCM-QAM. Therefore, a new table is computed and stored as required.
- Equations (1) and (2) to calculate the number of bits over one DMT symbol can be complicated. Therefore, in an alternate embodiment, the SNR thresholds (with or without coding gain) are pre-calculated for different QAM sizes. The SNR for each tone is quantized to determine the number of bits to be transmitted with a minimum change in power on the tone while maintaining an average power for all tones that does not increase.
- SNR thresholds to determine the number of bits to be transferred is known in the art and, therefore, will not be discussed in great detail.
- the SNR in the bin is compared with 15 thresholds.
- Each of the thresholds represents a constellation size up to 15 bits per constellation.
- the number of bits b i is set to be the constellation size (that is, the number of bits carried in that constellation) whose SNR threshold is closest to the bin SNR.
- the thresholds are computed in accordance with the following equation:
- a flowchart for yet another alternate embodiment is illustrated generally by numeral 300 .
- Searching for the final optimal solution that is, B inf — max and its associated parameters, is implemented differently than in previous embodiments. Rather than storing each maximum number of information bytes per symbol B inf for different values of G and then comparing all stored numbers once the value of G max is exceeded, B inf is continuously updated. That is, for example, the value of B inf for G min is stored as B inf — max . For each of the following iterations, B inf — max is only replaced if the value of B inf has a greater value.
- the above-described procedure is performed in step 302 .
- the other steps in the process 300 are equivalent to those in the process 200 of FIG. 2 and their details are not repeated.
- a flowchart for yet another alternate embodiment is illustrated generally by numeral 400 .
- the speed of the process may be enhanced by checking the value of the maximum number of bits per symbol B, in step 402 . If the value for B increases once the code gain G is increased, then the process proceeds as previously described. If, however, the new value for B does not increase once the code gain G is increased, the steps 210 to 212 are skipped and the value for G is incremented again.
- the other steps in the process 400 are equivalent to those in the process 300 of FIG. 3 and their details are not repeated.
- a flowchart for yet another alternate embodiment is illustrated generally by numeral 500 .
- the speed of the process may be enhanced by stopping the iterations once a predetermined level has been reached. For example, if the maximum number of bytes per symbol B inf does not increase once the code gain is increased, the final optimal solution B inf — max is set to higher value of B inf and the process is terminated.
- This can be seen in the process 500 by the process flowing directly from step 402 to step 218 when the condition of step 402 is not met. (Compare this with the process 400 of FIG. 4 which does not flow directly from step 402 to step 218 when the condition is not met.)
- the other steps in the process 500 are equivalent to those in the process 400 of FIG. 4 and their details are not repeated.
- FIG. 6 is a block diagram of an ADSL modem 600 that implements one or more of the above-described processes.
- the ADSL modem 600 includes a processor 602 and a memory 604 .
- the memory 604 stores various data such as the parameters G, B, n and r, and the data to be transmitted.
- the processor 602 implements one or more of the processes 200 , 300 , 400 or 500 .
- the processor 602 may also code the data to be transmitted according to the resulting preferred set of parameters and may generate code words 100 corresponding thereto.
- the ADSL modem 600 is illustrated with the processor and memory being separate, according to another embodiment they may be together.
- the processor 602 may be implemented as a dedicated processor or application-specific integrated circuit that is pre-configured to perform the above-described processes.
- the processor 602 may be implemented as a more general device that executes a computer program, microcode, or other software in order to perform the above-described processes.
- the computer program may be stored in the memory 604 or on some other computer-readable medium such as a floppy disk, hard drive or CD-ROM.
Abstract
Description
where x is a constant system delay in milliseconds. Modifications of this nature in the selection of S and r are known, and their use in the present invention will be apparent to a person skilled in the art.
Claims (24)
Applications Claiming Priority (2)
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CA2324574 | 2000-10-26 | ||
CA002324574A CA2324574A1 (en) | 2000-10-26 | 2000-10-26 | An optimal bit allocation algorithm for reed-solomon coded data for adsl |
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US20020140991A1 US20020140991A1 (en) | 2002-10-03 |
US7673221B2 true US7673221B2 (en) | 2010-03-02 |
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US10/046,639 Active 2028-12-26 US7673221B2 (en) | 2000-10-26 | 2001-10-26 | Optimal bit allocation system for Reed-Solomon coded data |
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US (1) | US7673221B2 (en) |
AU (1) | AU2002229134A1 (en) |
CA (1) | CA2324574A1 (en) |
WO (1) | WO2002035445A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20080141105A1 (en) * | 2006-12-08 | 2008-06-12 | Fujitsu Limited | Transmission apparatus, reception apparatus, and data transmission method |
US20100220771A1 (en) * | 2004-03-03 | 2010-09-02 | Aware, Inc. | Impulse noise management |
US20100281341A1 (en) * | 2009-05-04 | 2010-11-04 | National Tsing Hua University | Non-volatile memory management method |
US8209582B1 (en) * | 2006-11-07 | 2012-06-26 | Marvell International Ltd. | Systems and methods for optimizing a product code structure |
US20140136927A1 (en) * | 2010-10-27 | 2014-05-15 | Lsi Corporation | Adaptive ecc techniques for flash memory based data storage |
Families Citing this family (5)
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US20050213650A1 (en) * | 2004-03-25 | 2005-09-29 | Modlin Cory S | Minimizing the differential delay in ADSL2 and ADSL2+ to support bonding |
US7646804B2 (en) * | 2005-01-03 | 2010-01-12 | Texas Instruments Incorporated | System and method for improving bit-loading in discrete multitone-based digital subscriber line modems |
US20070220403A1 (en) * | 2006-02-27 | 2007-09-20 | Honeywell International Inc. | System and method for dynamic allocation of forward error encoding |
WO2008030150A1 (en) * | 2006-09-04 | 2008-03-13 | Telefonaktiebolaget Lm Ericsson (Publ) | Method for bit-loading in a multi-tone dsl system |
US10157161B2 (en) * | 2015-10-16 | 2018-12-18 | Qualcomm Incorporated | Conditional embedding of dynamically shielded information on a bus |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5600663A (en) | 1994-11-16 | 1997-02-04 | Lucent Technologies Inc. | Adaptive forward error correction system |
US5699369A (en) | 1995-03-29 | 1997-12-16 | Network Systems Corporation | Adaptive forward error correction system and method |
US5737337A (en) | 1996-09-30 | 1998-04-07 | Motorola, Inc. | Method and apparatus for interleaving data in an asymmetric digital subscriber line (ADSL) transmitter |
US5987061A (en) * | 1996-05-09 | 1999-11-16 | Texas Instruments Incorporated | Modem initialization process for line code and rate selection in DSL data communication |
US6072990A (en) | 1997-05-08 | 2000-06-06 | Lucent Technologies, Inc. | Transmitter-receiver pair for wireless network power-code operating point is determined based on error rate |
US6310909B1 (en) * | 1998-12-23 | 2001-10-30 | Broadcom Corporation | DSL rate adaptation |
US6330700B1 (en) | 1999-05-18 | 2001-12-11 | Omnipoint Corporation | Out-of-band forward error correction |
US6598188B1 (en) * | 1999-05-10 | 2003-07-22 | Texas Instruments Incorporated | Error-corrected codeword configuration and method |
-
2000
- 2000-10-26 CA CA002324574A patent/CA2324574A1/en not_active Abandoned
-
2001
- 2001-10-26 US US10/046,639 patent/US7673221B2/en active Active
- 2001-10-26 AU AU2002229134A patent/AU2002229134A1/en not_active Abandoned
- 2001-10-26 WO PCT/US2001/050943 patent/WO2002035445A1/en active Application Filing
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5600663A (en) | 1994-11-16 | 1997-02-04 | Lucent Technologies Inc. | Adaptive forward error correction system |
US5699369A (en) | 1995-03-29 | 1997-12-16 | Network Systems Corporation | Adaptive forward error correction system and method |
US5987061A (en) * | 1996-05-09 | 1999-11-16 | Texas Instruments Incorporated | Modem initialization process for line code and rate selection in DSL data communication |
US5737337A (en) | 1996-09-30 | 1998-04-07 | Motorola, Inc. | Method and apparatus for interleaving data in an asymmetric digital subscriber line (ADSL) transmitter |
US6072990A (en) | 1997-05-08 | 2000-06-06 | Lucent Technologies, Inc. | Transmitter-receiver pair for wireless network power-code operating point is determined based on error rate |
US6310909B1 (en) * | 1998-12-23 | 2001-10-30 | Broadcom Corporation | DSL rate adaptation |
US6598188B1 (en) * | 1999-05-10 | 2003-07-22 | Texas Instruments Incorporated | Error-corrected codeword configuration and method |
US6330700B1 (en) | 1999-05-18 | 2001-12-11 | Omnipoint Corporation | Out-of-band forward error correction |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8594162B2 (en) | 2004-03-03 | 2013-11-26 | Tq Delta, Llc | Impulse noise management |
US20100220771A1 (en) * | 2004-03-03 | 2010-09-02 | Aware, Inc. | Impulse noise management |
US11005591B2 (en) | 2004-03-03 | 2021-05-11 | Tq Delta, Llc | Impulse noise management |
US10805040B2 (en) | 2004-03-03 | 2020-10-13 | Tq Delta, Llc | Impulse noise management |
US10567112B2 (en) | 2004-03-03 | 2020-02-18 | Tq Delta, Llc | Impulse noise management |
US8743932B2 (en) | 2004-03-03 | 2014-06-03 | Tq Delta, Llc | Impulse noise management |
US8462835B2 (en) | 2004-03-03 | 2013-06-11 | Tq Delta, Llc | Impulse noise management |
US8209582B1 (en) * | 2006-11-07 | 2012-06-26 | Marvell International Ltd. | Systems and methods for optimizing a product code structure |
US8595587B1 (en) | 2006-11-07 | 2013-11-26 | Marvell International Ltd. | Systems and methods for optimizing a product code structure |
US8392790B1 (en) | 2006-11-07 | 2013-03-05 | Marvell International Ltd. | Systems and methods for optimizing a product code structure |
US20080141105A1 (en) * | 2006-12-08 | 2008-06-12 | Fujitsu Limited | Transmission apparatus, reception apparatus, and data transmission method |
US8307261B2 (en) * | 2009-05-04 | 2012-11-06 | National Tsing Hua University | Non-volatile memory management method |
US20100281341A1 (en) * | 2009-05-04 | 2010-11-04 | National Tsing Hua University | Non-volatile memory management method |
US20140136927A1 (en) * | 2010-10-27 | 2014-05-15 | Lsi Corporation | Adaptive ecc techniques for flash memory based data storage |
US20160188405A1 (en) * | 2010-10-27 | 2016-06-30 | Seagate Technology Llc | Adaptive ecc techniques for flash memory based data storage |
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US20020140991A1 (en) | 2002-10-03 |
AU2002229134A1 (en) | 2002-05-06 |
CA2324574A1 (en) | 2002-04-26 |
WO2002035445A1 (en) | 2002-05-02 |
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