US7676529B2 - System and method for efficient rectangular to polar signal conversion using cordic algorithm - Google Patents
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
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- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5446—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation using crossaddition algorithms, e.g. CORDIC
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- the invention relates generally to systems and methods for converting digital representations of electromagnetic signals from a rectangular format to a polar format, and more particularly to methods and apparatuses for efficient conversion using a CORDIC algorithm.
- Electromagnetic waves and signals are utilized for many different purposes.
- electromagnetic signals may be processed in order to convey information, such as by attenuating and/or amplifying electromagnetic wave characteristics, for instance, as is seen when modulating the amplitude, frequency or phase of an electrical current or radio frequency (RF) wave to transmit data.
- RF radio frequency
- power may be conveyed along a wave in a controlled fashion by attenuating and/or amplifying electromagnetic signals, such as is seen when modulating voltage or current in a circuit.
- the uses may be combined, such as when information may be conveyed through a signal by processing power characteristics.
- Electromagnetic signal processing may be accomplished through digital or analog techniques. Digital and analog attenuation and/or amplification also may be combined—that is, the same wave form may be subject to various types of digital and/or analog attenuation and/or amplification within a system in order to accomplish desired tasks. Other types of processing also may be used to modify electromagnetic signals, including pre-distortion, various types of modulation, etc.
- electromagnetic signals may be represented in various ways.
- a signal may be represented as a sequence of vectors indicative of the amplitude and phase of the signal.
- the vectors may be represented using various coordinate systems, including rectangular coordinates and polar coordinates.
- a particular vector V may be represented as the vector coordinate pair (x,y), where “x” represents the vector component in the x direction (i.e., along the x-axis), and “y” represents the vector component in they direction (i.e, along the y-axis.).
- rectangular coordinates are sometimes represented as “IQ” data, wherein a particular vector V may be represented as the complex number I+jQ.
- I represents the vector component in the x direction
- Q represents the vector component in they direction.
- IQ data may simply be denoted as (I,Q), which is the same as the (x,y) notation discussed above.
- Polar coordinates also are useful in representing electromagnetic signals.
- a particular vector V may be represented as the vector coordinate pair ( ⁇ , ⁇ ), where “ ⁇ ” represents the magnitude of the vector and “ ⁇ ” represents the angle of the vector from the x-axis.
- CORDIC Coordinate Rotation DIgital Computer
- CORDIC algorithms convert a 2-dimensional vector (x,y) from rectangular coordinates into polar coordinates ( ⁇ , ⁇ ). The algorithms accomplish this by performing a successive approximation operation that rotates the vector asymptotically toward the x-axis.
- the polar angle coordinate, ⁇ may be determined based on the angle by which the vector has been rotated
- polar magnitude coordinate, ⁇ may be determined based on the point at which the rotated vector ends on (or near) the x-axis.
- the number of iterations required of a CORDIC algorithm depends on the bit width of the input vector and the desired accuracy of the final calculation.
- a disadvantage of known CORDIC algorithms is that, as the number of iterations increases, so does the amount of time required to complete each vector conversion. This results in a propagation delay between receipt of the rectangular input vector and output of the converted polar vector.
- Another disadvantage of known CORDIC algorithms is that the algorithm must complete the conversion of one input vector (including all necessary iterations) before it may begin the conversion of the next input vector in the sequence. If the propagation delay is longer than the sampling period of the input signal, then the overall propagation delay between the input signal and the output signal will grow with each additional input vector conversion. In certain practical applications, such as high-speed communication systems, this increasing propagation delay is undesirable.
- a system for processing an input signal including a sequence of input vectors, each input vector including a pair of rectangular coordinates.
- a first input register is configured to store a first input vector of the input signal
- a second input register is configured to store a second input vector of the input signal.
- a first instance of a CORDIC algorithm instance configured to receive the first input vector and to convert the first input vector to a first output vector including a first pair of polar coordinates.
- a second instance of a CORDIC algorithm is configured to receive the second input vector and to convert the second input vector to a second output vector including a second pair of polar coordinates.
- a recombiner is configured to receive the first and second output vectors and to combine at least the first and second output vectors in sequence to form an output signal.
- a system for processing an input signal including a sequence of at least N input vectors, where N ⁇ 2, and wherein each input vector includes a pair of rectangular coordinates.
- Each of a plurality of N input registers is configured to store an input vector of the input signal.
- the system includes a plurality of N CORDIC algorithm instances, each in communication with a corresponding one of the N input registers.
- Each CORDIC algorithm instance is configured to receive the input vector stored in the corresponding input register and to convert the received input vector to a corresponding output vector including a pair of polar coordinates.
- a recombiner is configured to receive the N output vectors and to recombine at least the N output vectors in sequence to form an output signal.
- a method for processing an input signal including a sequence of at least N input vectors, where N ⁇ 2, and wherein each input vector includes a pair of rectangular coordinates.
- a plurality of N CORDIC algorithm instances are instantiated.
- Each of the first N input vectors is processed using one of the N CORDIC algorithm instances, wherein the nth CORDIC algorithm instance converts the nth input vector to an nth output vector including an nth pair of polar coordinates, and wherein 1 ⁇ n ⁇ N.
- At least the N output vectors are combined in sequence to form an output signal.
- FIG. 1 is a block diagram illustrating a transmitter including a signal processor according to one aspect of the invention.
- FIG. 2 is a block diagram illustrating a signal processor for converting the vectors of an input signal from rectangular to polar coordinates according to another aspect of the invention.
- FIG. 3 is a flow diagram illustrating a method for converting the vectors of an input signal from rectangular to polar coordinates according to another aspect of the invention.
- FIG. 4 is a timing diagram illustrating a method for converting the vectors of an input signal from rectangular to polar coordinates according to another aspect of the invention.
- Embodiments of the invention include systems, methods, and articles of manufacture for processing electromagnetic waves and signals.
- an exemplary embodiment comprises a signal processor for converting a sequence of rectangular coordinate input vectors to a sequence of polar coordinate output vectors.
- the systems and methods described in this application may be implemented in a wide range of applications, such as, for example, a digital signal processor, a baseband processor, a phase, frequency, or amplitude modulator, an amplifier, a transmitter, a receiver, etc.
- an exemplary transmitter including a phase modulator according to one aspect of the invention, is illustrated in FIG. 1 .
- the transmitter 100 includes a signal processor 110 , a phase modulator 120 , an amplitude modulator 130 , a power amplifier 140 , and an antenna 150 .
- the various components of the exemplary transmitter 100 may be analog or digital in nature.
- the exemplary transmitter 100 also may include a combination of analog and digital components.
- signal should be broadly construed to include any manner of conveying data from one place to another, such as, for example, an electric current or electromagnetic field, including without limitation, a direct current that is switched on and off or an alternating-current or electromagnetic carrier that contains one or more data streams. Data, for example, may be superimposed on a carrier current or wave by means of modulation, which may be accomplished in analog or digital form.
- data as used herein should also be broadly construed to comprise any type of intelligence or other information, such as, for example and without limitation, audio, video, and/or text information.
- CORDIC algorithms convert a 2-dimensional vector from rectangular coordinates (x,y) into polar coordinates ( ⁇ , ⁇ ).
- the algorithm typically begins by detecting which of the four quadrants contains the vector. If the vector resides in either the upper left quadrant or the lower left quadrant, then the algorithm maps the vector into the upper right quadrant or the lower right quadrant, respectively. The algorithm then applies a successive approximation operation on the vector, which rotates the vector asymptotically toward the x-axis. After N iterations, the algorithm terminates.
- the distance moved from the location of the original vector to the x-axis becomes the polar angle coordinate, ⁇ , and the point at which the vector terminates on (or near) the x-axis becomes the polar magnitude coordinate, ⁇ . It may also be necessary to factor the inherent CORDIC gain out of the polar magnitude coordinate, as is known in the art.
- N The number of iterations required, depends on the bit width of the input vector and the desired accuracy of the final calculation.
- the accuracy may be defined as the asymptotic proximity of the final rotated vector to the x-axis.
- Each iteration of the algorithm requires a determination of which quadrant contains the current rotated vector (i.e., the upper right quadrant or the lower right quadrant), which is required to determine the direction in which the vector must be rotated to move it toward the x-axis.
- the complexity of the overall logic increases with each additional iteration of the algorithm. This has a negative impact on the speed of the conversion, which requires more time to provide more accuracy.
- the maximum processing frequency, f max is a function of the propagation delay, p del . This is because all of the iterations for a given conversion must be performed before a final converted polar coordinate vector may be obtained.
- the relationship between f max and p del is defined as:
- a parallel processing/recombining scheme significantly increases the CORDIC conversion performance.
- the significant increase in performance may be realized by instantiating multiple (i.e., N) instances of the CORDIC algorithm to process input vectors in parallel, and then recombining the output of the multiple algorithms in the proper sequence to form the output signal.
- N ( p del +p del ′) ⁇ f desired , where p del ′ ⁇ p del
- the factor p del ′ is an additional propagation delay caused by the necessary recombining circuitry. This additional delay is generally small compared to the propagation delay p del of the CORDIC algorithm.
- N the number of CORDIC algorithms that may be instantiated in parallel.
- a large number of CORDIC algorithms may exceed the loading limits of the input and output circuitry, which may slow down the input and output signal processing.
- the use of multiple parallel CORDIC algorithms can provide significant increases in performance compared to the use of a single instance of a CORDIC algorithm.
- the signal processor 110 may be, for example, a digital signal processor, such as a digital signal processor capable of generating a power control signal and a data control signal in response to the input signal.
- the input signal may be, for example, a baseband signal. Electrical power may be regulated by the data control signal in order to generate an output signal for transmission that is an amplified version of the input signal.
- the signal processor 110 converts the vectors of native I,Q data from rectangular coordinates into polar coordinates to create a data control signal that contains the amplitude component of the input signal, and an electromagnetic signal that contains the phase component of the input signal.
- the signal processor 110 uses the CORDIC algorithm discussed above to output polar coordinates, for example, in the form R, P(sin) and P(cos).
- the R coordinate represents the amplitude component of the input signal
- the P(sin) and P(cos) coordinates represent the phase component of the signal.
- the amplitude and phase components of the input signal are then transmitted through separate paths to power amplifier 140 .
- the amplitude component of the original input signal may be modulated by optional amplitude modulator 130 as a series of digital pulses comprising a digital word quantized into bits B 0 to B N ⁇ 1 with a most significant bit and a least significant bit.
- the digital word may be of varying lengths in various embodiments.
- phase component may be processed separately by optional phase modulator 120 and then applied to power amplifier 140 .
- the phase component may be modulated by the phase modulator 120 to yield an on-channel, phase modulated carrier.
- the phase modulated carrier may then be provided to the power amplifier 140 .
- the power amplifier 140 may then combine the phase modulated carrier with the amplitude component to generate a fully-modulated carrier with the required output power signal level.
- FIG. 2 is a block diagram illustrating a signal processor 100 for converting the vectors of an input signal from rectangular to polar coordinates according to another aspect of the invention.
- the signal processor 200 is one example of a signal processor 110 for use with the transmitter 100 shown in FIG. 1 .
- the signal processor 200 may be implemented in a variety of architectures.
- the signal processor may be implemented using logic instructions programmed on a dedicated, special-purpose digital signal processing device.
- the signal processor may be implemented using logic instructions programmed along with various other applications on a general purpose microprocessor.
- the signal processor 200 includes a system clock 210 , which provides a period clock signal for timing of operations. Alternatively, the signal processor 200 may receive a clock signal from an external system clock.
- the signal processor 200 also includes a controller or control unit 220 , which controls operation of the signal processor 200 based in part on the clock signal from the system clock 210 .
- One function of the controller 220 is to provide particular input vectors to particular input registers by controlling the input of each vector from the input signal, VECTOR_IN, to one of the N input registers 230 , 232 , 234 .
- Each of the input vectors includes a pair of rectangular coordinates, (x,y). For convenience, only three input registers 230 , 232 , 234 are shown in FIG. 2 . In practice, however, the signal processor 200 may include any desired number, N, of input registers, as discussed in more detail below.
- the controller 220 may control selection and routing of the input vectors in various ways. For instance, as illustrated in FIG. 2 , the controller 220 may send control signals along control lines to each of the input registers 230 , 232 , 234 . In accordance with the control signals and the clock signal from the system clock 210 , each of the input registers 230 , 232 , 234 enables its input port at the appropriate time to receive the appropriate input vector from the input signal.
- the input registers 230 , 232 , 234 store the input vectors for purposes of the CORDIC conversion.
- Each of the input registers 230 , 232 , 234 is in communication with one of N instances 240 , 242 , 244 of a CORDIC algorithm.
- Each of these CORDIC algorithm instances 240 , 242 , 244 is instantiated separately to enable parallel conversion of successive input vectors.
- the signal processor 200 may include any desired number, N, of CORDIC algorithm instances, as discussed in more detail below.
- Each of the CORDIC algorithm instances 240 , 242 , 244 is configured to receive a rectangular coordinate input vector from its associated input register 230 , 232 , 234 .
- the CORDIC algorithm instances 240 , 242 , 244 are further configured to convert the received input vectors to polar coordinate vectors by performing a desired number of CORDIC rotation iterations.
- Each of the polar coordinate vectors, or output vectors includes a pair of polar coordinates, ( ⁇ , ⁇ ).
- each of the CORDIC algorithm instances 240 , 242 , 244 provides the converted polar coordinate vector to the recombiner 250 .
- the recombiner 250 is configured to receive converted polar coordinate output vectors from each of the N CORDIC algorithm instances 240 , 242 , 244 and to recombine the converted vectors in sequence to form a sequenced output signal. As illustrated in the exemplary signal processor 200 of FIG. 2 , the recombiner 250 sequences the output vectors according to a control signal received from the controller 220 . Alternative arrangements for sequencing the output vectors also are possible. As desired, the output signal includes the proper sequence (matched to the sequence of the input signal) of vectors converted to polar coordinates.
- the recombiner 250 may provide the polar coordinate output vectors of the output signal in a variety of ways. As illustrated in FIG. 2 , the recombiner 250 provides the output vectors as two component output signals, MAG and PHASE, which represent the magnitude and phase of the output signal, respectively. In this arrangement, the polar magnitude coordinate, ⁇ , of each output vector is included in the magnitude component output signal, MAG. Likewise, the polar phase coordinate, ⁇ , of each output vector is included in the phase component output signal, PHASE.
- the signal processor 200 illustrated in FIG. 2 includes two output registers 260 , 262 configured to receive the magnitude and phase component output signals, PHASE and MAG, respectively.
- the output registers 260 , 262 are further configured to temporarily store the component output signals and to provide these component output signals to other devices or systems for amplification, attenuation, further signal processing, etc., according to the particular application.
- FIG. 2 illustrates the source of the CORDIC propagation delay, p del , 270 resulting from a single vector conversion.
- FIG. 2 also illustrates the additional propagation delay, p del ′, 280 resulting from the recombination circuitry required to sequence the converted output vectors to form an output signal.
- These two separate propagation delays are included in FIG. 2 merely to illustrate the source of the delays and are not drawn to scale. In practice, the propagation delay due to recombination, p del ′, 280 typically would be small relative to the CORDIC propagation delay, p del , 270 .
- FIG. 3 the figure is a flow diagram illustrating a method for converting the vectors of an input signal from rectangular to polar coordinates according to another aspect of the invention.
- a desired number N CORDIC algorithms are instantiated 310 .
- N parallel CORDIC algorithm instances 240 , 242 , 244 are instantiated 310 .
- each instance would be of exactly the same CORDIC algorithm.
- various different known CORDIC algorithms may be used for different instances, depending on particular design parameters.
- an index counter k is initiated and set to zero 320 .
- the counter k is used as an index for the rectangular input vectors, V r (k), and the polar output vectors, V p (k).
- a second index counter n also is initiated and set to zero 330 .
- the counter n is used to index the N CORDIC algorithm instances and to assign particular input vectors to particular input registers 230 , 232 , 234 and CORDIC algorithm instances 240 , 242 , 244 .
- the counters k and n illustrated here are exemplary, but other counters and indexing methods may be used consistent with the invention.
- a particular input vector, V r (k), is stored 340 in the nth input register (e.g., 230 , 232 , 234 in FIG. 2 ), based on the current values of the index counters k and n.
- the input vector, V r (k) is then passed 350 to a CORDIC instance, CORDIC(n), based on the current values of the index counters k and n.
- the CORDIC instance, CORDIC(n) converts 360 the rectangular coordinate input vector V r (k) to a polar coordinate output vector V p (k) by performing the desired number of CORDIC iterations. For example, each CORDIC instance may perform between 8 and 12 iterations of the algorithm for each conversion. The bit width of the vector representations for these conversions may be between 9 and 13 bits.
- the converted polar coordinate output vector V p (k) is then recombined 360 in sequence in the output signal.
- next sequential input vector is loaded and passed to the next CORDIC instance.
- the parallel processing in FIG. 3 is illustrated by dashed lines.
- the next input vector V r (k) is then stored 340 in the nth input register based on the updated values of the index counters k and n, and the process continues as described above, passing 350 the input vector V r (k) to the CORDIC instance CORDIC(n) (again, based on the updated values of k and n), converting 360 the input vector V r (k) to a polar coordinate output vector V p (k), and recombining 370 the polar output vector V p (k) in sequence in the output signal.
- the method returns to using the first CORDIC instance, CORDIC(0), for the next conversion.
- the next input vector V r (k) is then stored 340 in the nth input register based on the updated values of the index counters k and n, and the process continues as described above, passing 350 the input vector V r (k) to the CORDIC instance CORDIC(n) (again, based on the updated values of k and n), converting 360 the input vector V r (k) to a polar coordinate output vector V p (k), and recombining 370 the polar output vector V p (k) in sequence in the output signal.
- the process illustrated in FIG. 3 is complete when the last input vector has been converted into an output vector, which is recombined into the output signal.
- the desired number of CORDIC algorithm instances 240 , 242 , 244 may be selected depending on a variety of design factors. For instance, it may be desirable to match the number of CORDIC algorithm instances to the number of algorithm iterations performed in each CORDIC conversion. This arrangement is particularly advantageous when a single iteration of the CORDIC algorithm can be completed within one clock cycle period. This is illustrated in the timing diagram of FIG. 4 .
- FIG. 4 is a timing diagram according to another aspect of the invention for a system running four parallel CORDIC instances, where each CORDIC instance requires four clock cycles to complete a single CORDIC conversion.
- the scale of the timing diagram is based on the system clock signal 410 .
- the VECTOR IN signal 420 represents the receipt of each sequential input vector V r (k) by an input register 230 , 232 , 234 .
- the COUNT signal 430 is an index counter similar to the counter n discussed above with respect to FIG. 3 .
- the COR REG IN signals 440 , 450 , 460 , 470 represent the time required for each of the CORDIC instances to convert particular input vectors.
- the PH/MAG OUT signal 480 represents the sequenced timing of the output vectors V p (k) in the output signal.
- the first input vector V r (0) is received at the first input register 230 during the clock cycle period ending at time t 0 .
- the value of the index counter n at this time is zero, so the first input vector V r (0) is passed to the first CORDIC instance, CORDIC(0), for conversion.
- the conversion process begins during the next clock cycle period, shortly after time t 0 .
- Each conversion illustrated in FIG. 4 requires four clock cycle periods.
- the CORDIC algorithm may perform four iterations per conversion, where a single iteration requires a single clock cycle period. (Alternatively, the CORDIC algorithm may perform two iterations per conversion, where a single iteration requires two clock cycle periods.)
- the first CORDIC instance, CORDIC(0) performs the conversion of the first input vector V r (0) during the four clock cycle periods between times t 0 and t 4 .
- the converted polar coordinate output vector V p (0) is then provided shortly after time t 4 .
- next input vector V r (1) is received at the next input register 232 during the clock cycle period ending at time t 1 .
- the value of the index counter n at this time is one, so the input vector V r (1) is passed to the next CORDIC instance, CORDIC(1), for conversion.
- the conversion process begins during the next clock cycle period, shortly after time t 1 .
- the CORDIC(1) instance performs the conversion of the input vector V r (1) during the four clock cycle periods between times t 1 and t 5 .
- the converted polar coordinate output vector V p (1) is then provided shortly after time 5 .
- This process continues in parallel, with the CORDIC(2) and CORDIC(3) instances beginning conversion of input vectors V r (2) and V r (3) before the CORDIC(0) instance completes conversion of the first input vector V r (0).
- the CORDIC(2) instance performs the conversion of the input vector V r (2) during the four clock cycle periods between times t 2 and t 6 , and the converted polar coordinate output vector V p (2) is provided shortly after time t 6 .
- the CORDIC(3) instance performs the conversion of the input vector V r (3) during the four clock cycle periods between times t 3 and t 7 , and the converted polar coordinate output vector V p (3) is provided shortly after time t 7 .
- the counter n is reset to zero.
- the process returns to using the first input register 230 and the first CORDIC instance 240 , CORDIC(0).
- the CORDIC(0) instance performs the conversion of the conversion of the input vector V r (4) during the four clock cycle periods between times t 4 and t 8 , and the converted polar coordinate output vector V p (4) is provided shortly after time t 8 .
- the CORDIC(0) instance is performing this conversion, the CORDIC(1), CORDIC(2), and CORDIC(3) instances begin in parallel to perform conversions of the input vectors V r (5), V r (6), and V r (7). This conversion process continues, cycling through the four parallel CORDIC instances, for as long as new input vectors are received.
- transmitters, receivers, transceivers, and other components such as transmitter 100 and signal processors 10 and 200 may be specialized for particular input signals, carrier waves, and output signals (e.g., various types of cell phones, such as CDMA, CDMA2000, WCDMA, GSM, TDMA), as well as various other types of devices, both wired and wireless (e.g., Bluetooth, 802.11a, -b, -g, radar, IxRTT, radios, GPRS, EDGE, computers, computer or non-computer communication devices, or handheld devices).
- various types of cell phones such as CDMA, CDMA2000, WCDMA, GSM, TDMA
- various other types of devices e.g., Bluetooth, 802.11a, -b, -g, radar, IxRTT, radios, GPRS, EDGE, computers, computer or non-computer communication devices, or handheld devices.
- the modulation schemes used in these environments may include, for example, GMSK, which is used in GSM; GFSK, which is used in DECT & Bluetooth; 8-PSK, which is used in EDGE; OQPSK & HPSK, which are used in IS-2000; p/4 DQPSK, which is used in TDMA; and OFDM, which is used in 802.11.
- GMSK which is used in GSM
- GFSK which is used in DECT & Bluetooth
- 8-PSK which is used in EDGE
- OQPSK & HPSK which are used in IS-2000
- p/4 DQPSK which is used in TDMA
- OFDM which is used in 802.11.
Abstract
Description
N=(p del +p del′)×f desired, where p del ′□p del
The factor pdel′ is an additional propagation delay caused by the necessary recombining circuitry. This additional delay is generally small compared to the propagation delay pdel of the CORDIC algorithm.
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US8572150B1 (en) * | 2007-10-05 | 2013-10-29 | Xilinx, Inc. | Parameterization of a CORDIC algorithm for providing a CORDIC engine |
US8149899B2 (en) * | 2008-11-26 | 2012-04-03 | Advanced Receiver Technologies, Llc | Efficient despread and respread of multi-rate CDMA signals |
US8572151B2 (en) * | 2010-03-15 | 2013-10-29 | Integrated Device Technology, Inc. | Methods and apparatuses for cordic processing |
US11455144B1 (en) * | 2019-11-21 | 2022-09-27 | Xilinx, Inc. | Softmax calculation and architecture using a modified coordinate rotation digital computer (CORDIC) approach |
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