|Numéro de publication||US7689748 B2|
|Type de publication||Octroi|
|Numéro de demande||US 11/418,788|
|Date de publication||30 mars 2010|
|Date de dépôt||5 mai 2006|
|Date de priorité||5 mai 2006|
|État de paiement des frais||Payé|
|Autre référence de publication||US20070260796|
|Numéro de publication||11418788, 418788, US 7689748 B2, US 7689748B2, US-B2-7689748, US7689748 B2, US7689748B2|
|Inventeurs||Mark Grossman, Jeffrey G. Cheng, Gordon Caruk, Joel Wilke, Elaine Poon|
|Cessionnaire d'origine||Ati Technologies, Inc.|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Citations de brevets (21), Référencé par (17), Classifications (5), Événements juridiques (2)|
|Liens externes: USPTO, Cession USPTO, Espacenet|
The invention is in the field of scheduling operations in complex data processing systems.
In typical complex data processing systems, many different processing tasks or operations are being performed by multiple sub-units of the system at any one time. Usually, all of the operations of the system are under the control of a host processor, or central processing unit (CPU) that runs a particular operating system (OS). The CPU communicates with various input/output (IO) units of the system through one or more buses, such as a peripheral component interface (PCI) bus or a PCI Express (PCIE) bus for example.
The host processor manages operations in the system, including execution of various tasks by various IO units. The IO units must necessarily communicate a lot of information with the host processor in a manner dictated by the OS. For example, when a task is executing on an IO unit and becomes stalled or interrupted, perhaps because of lack of particular data for example, the IO unit generates an interrupt to the host processor in such a way that the host processor can identify the IO unit and the cause of the interrupt, “fix” the cause of the interrupt, and signal the IO unit that the problem is fixed and that it can proceed with the task. Traditionally, interrupts are signaled by the IO unit writing a value to an interrupt status register. According to one scheme, an interrupt status register may contain multiple bits, any one of which signals an interrupt when it is a particular value, such as a logic “1” (also referred to as a logic high). The values in the interrupt status register are OR'd and if any of the values is high, an interrupt signal is sent to the host processor, which must perform a register read to determine which bit or bits are high. The host processor also must perform a register write to clear interrupts after fixing their causes. This interrupt scheme is sometimes referred to as level-based, because the level of the interrupt bit and line remains at the level set by the IO unit until the interrupt is cleared by the host processor.
IO units are often sophisticated special-purpose processors such as graphics processing units (GPUs). As greater processing speeds are demanded for complex functions, such as graphics processing or video processing, techniques for maximizing the use of system resources constantly evolve. System resources include processing units (such as GPUs), and memory. One common technique for maximizing the use of processing system resources is multi-threaded processing, which requires context switching between tasks. Resources capable of context switching encounter an event that causes the pause or stall of one task, and in response, store the current state of the stalled task (also referred to as switching out the current context) and proceed with another task (or switch in another context) while waiting for the cause of the stall to be cured, or fixed. The host processor must be informed of the stall, for example by the resource issuing an interrupt to the host, and the host is responsible for fixing the cause of the interrupt, and informing the resource that it can switch the previous context back in and continue with the operation that had been interrupted. Such interrupts are not level-based, but are typically signaled by a pulse. In addition, such interrupts do not require storage of interrupt status information in a register, or register reads and writes by the host processor.
In a context-switching environment, the traditional register-based signal-clear mechanism no longer works. This is because the interrupt status register becomes context-sensitive. Consider the following scenario: an IO unit client under a particular context generates an interrupt; a moment later the context is switched away. When an interrupt service routine (ISR) of the host comes to service the interrupt, it reads the interrupt status register which now belongs to a different context. There are race conditions in such a scenario. An interrupt delivery mechanism that is functional in context-switching systems is thus required. One mechanism for supporting context-based interrupts over a PCIE bus is called message signaled interrupt, or MSI. Another mechanism for supporting context-based interrupts over a PCIE bus is MSI-X, which is another version of MSI. MSI allows up to 32 different interrupt sources to have their unique messages without the need for the ISR to read hardware registers. MSI-X expands the number of interrupt vectors to up to 2048.
But traditional level-based interrupts should also be supported for transitional systems or system components that support only level-based interrupts and do not support MSI or MSI-X.
In order to support context-switchable environments, one cannot associate a fixed vector with a given interrupt source. One reason is that an interrupt source can be associated with different contexts. Since all interrupt events must be reserved, if an interrupt source is assigned to a fixed vector, it is possible for a vector to be overwritten by a second interrupt before the ISR processes the first interrupt associated with the first context.
Another reason the traditional register-based mechanism is impractical for complex IO units, regardless of whether context switching occurs or not, is that the number of interrupt sources keeps growing. For example, the number of different interrupt sources for a complex GPU exceeds what a single traditional 32-bit interrupt status register can accommodate. If the ISR has to read the interrupt status register, it may need to read more than one register to locate the interrupt source. Register reads from software (the OS) are slow by nature, but the ISR may have hundreds of interrupts per second to service. This creates performance concerns.
In the drawings, the same reference numbers identify identical or substantially similar elements or acts. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the Figure number in which that element is first introduced (e.g., element 102 is first introduced and discussed with respect to
Embodiments of a system and method for handling interrupts are described herein. In an embodiment events, or interrupts from various client components in a system (also referred to as clients) are processed by one event handler, or interrupt handler component uniformly. The various clients signal interrupts in different manners. For example, some clients signal interrupts in a level-based manner, and some clients signal interrupts in a pulse-based manner. In an embodiment, the non-context switchable, level-based components perform permanent tasks, and the pulse based, context switchable components perform serialized volatile tasks. In an embodiment, a permanent task involves a single thread of execution, while a volatile task involves multiple threads of execution by allowing its state to be saved and restored at selected points in time.
In an embodiment, each interrupt received by the interrupt handler is formed into an event message according to a uniform format regardless of the interrupt type or source. The event message includes all information necessary for a host processor interrupt service routine (ISR) to service the interrupts without reading hardware registers. Embodiments include an IO unit interrupt handler that collects all interrupts generated by clients of the IO unit and forms them into event messages. The interrupt handler stores event messages from the input unit into a designated event buffer in memory that is accessible to the host processor, also referred to simply as the host. The interrupt handler also sends an interrupt signal to the host, which responds by reading the event buffer and handling all of the event messages appropriately. The host acknowledges a pulse-based interrupt by updating a read pointer of the event buffer; and acknowledges a level-based interrupt by a register write to clear the interrupt source. In an embodiment, the read pointer is updated by interrupt handler software running on the host after it has read the contents of the event buffer that lie between the current state of the read pointer and the current state of the write pointer. Embodiments further include an adapter unit that receives level-based interrupts from level-based interrupt clients and generates an appropriate event message for storage by the IO unit to the event buffer.
The host 104 may be any central processing unit, such as a processor that is intended for consumers who wish to run various applications. The host 104 also includes or communicates with hardware and software (not shown) to facilitate transactions on the bus 124. For purposes of this disclosure, the host 104 and other components, such as the memory 108 are understood to communicate via the bus 124 through any necessary hardware and software that it known in such systems, but is not shown here for clarity. For example, various system components may be coupled via one or more bus bridges in a known manner. The IO unit 102 may be any IO unit that is capable of performing a function under control of the host 104 according to the applicable operating system of the host 104. As an example for purposes of illustrating the embodiments, the IO unit 102 is a graphics processing unit (GPU). Embodiments of the invention include any relatively complex IO unit along with a host that is capable of controlling one or more such complex IO units.
The IO unit 102 includes various clients, each of which performs a designated operation or operations. For example, the clients may include various sub-units or components. For example, when the IO unit 102 is a graphics or video processor, the clients may include a 3-D engine, and a video engine. The clients include multiple context-switchable clients 112 and multiple “legacy clients” 114. Herein, the term “legacy” refers to clients that are capable of level-based interrupt signaling, such as a display engine for example. Context-switchable clients 112 typically include such sub-units as 3-D engines and video engines. The numbers of clients 112 and 114 shown herein are for illustration only and are not limiting.
The context-switchable clients 112 and the legacy clients 114 communicate with an interrupt handler 106. The context-switchable clients 112 communicate with the interrupt handler 106 via an interface 113. The legacy clients 114 communicate with respective adapters 116. As further explained below, the adapters 116 facilitate uniform handling by the interrupt handler 106 of both level-based interrupts from the legacy clients 114, and pulse-based interrupts from the context-switchable clients 112. Context-switchable clients 112 perform volatile tasks and generate pulse-based interrupts. Communication between the context-switchable clients 112 and the interrupt handler 106 includes an interruptible message stream. The legacy clients communicate with the interrupt handler 106 via the adapters 116 and an interface 113.
The IO unit 102 further includes a memory controller 118 and a local memory 120. The memory controller 118 has the capability to access the local memory 120, and also the system memory 108 via the bus 124. The host 104 has access to both the system memory 108 and the local memory 120. Accesses of the local memory 120 by the host 104 occur through a host interface controller 122, and are typically slower than accesses of the system memory 108 by the host 104 via the bus 124.
The host interface controller 122 communicates with the interrupt handler 106 via an interface 107. The host interface controller 122 communicates with other system components external to the IO unit 102 via the bus 124 and controls access in both directions between the host 104 and the IO unit 102.
As further described below, the system memory 108 includes an event buffer 110 that is designated to store event messages at the request of the interrupt handler. In various other embodiments, the event buffer may be located elsewhere, such as in the local memory 120, or any other memory location that is accessible by both the interrupt handler 102 and the host 104. The event buffer 110 is read by the host 104, and an interrupt service routine (ISR) 105 of the host 104 handles the interrupts associated with the event messages stored in the event buffer 110.
In an embodiment, the event buffer 110 is allocated in cacheable system memory 108, which allows the ISR 105 to quickly read event messages. The ISR 105 is not expected to write to the event buffer. It is preferable for the write pointer writeback location to be a location that allows the ISR 105 to read the read pointer quickly. In an embodiment in which the IO unit is a GPU, the cacheable system memory is mapped to a graphics address remapping table (GART). In various embodiments the GART may support virtual mappings, per-context mappings, or global, system mappings
The size of the event buffer should be sufficient to buffer the speed difference as a result of parallel execution between hardware and software. In worst cases, hardware may be generating interrupts in the order of thousands per second, and software may be overloaded by interrupts. The ISR 105 should try to avoid overflow of the event buffer where possible. In an embodiment, the event buffer 110 stores 4096 event messages of 128 bits each, or 64 Kbytes. The event buffer 110 in various embodiments could be smaller or larger than 64 Kbytes, and can be allocated based on empirical data.
In an embodiment, the control of the event buffer 110 is similar to the control of a ring FIFO buffer. There is a read pointer for the consumer, a write pointer for the producer, and a wrapping mechanism. One property of the event buffer 110 is that the consumer, in this case the ISR 105, can be designed to consume all outstanding interrupt data in the event buffer 110 instead of processing one interrupt and returning, which may be less efficient. By processing all outstanding interrupts, the ISR 105 also has the opportunity to prioritize those interrupts in an order desirable to software.
There may be an issue when the ISR 105 is slowed or stopped while processing interrupts, causing the event buffer 110 to overflow. As hardware cannot wait for software, the choices include stopping the generation of subsequent interrupts, or overwriting unprocessed older interrupts in the event buffer 110. In an embodiment, there is an option to stop the generation of subsequent interrupts, which is controlled by a register setting. It is suggested that losing older interrupts that signaled outdated events is a better choice over losing more recent interrupting events. Therefore there is a flag to indicate such overflow events from hardware, so that the ISR 105 can capture the more recent interrupts by calculating the difference between the read pointer, the write pointer, and taking the overflow flag into account. Embodiments support both losing older interrupts and losing newer interrupts. Under normal situations, software should be able to set up a reasonably sized ring buffer (2048 entries, for example) that is sufficient to buffer interrupts.
The interrupt handler 106 sequences through all outstanding interrupt requests from all clients 112 and 114, maintains the event buffer 110, and signals the host interface controller 122 to signal an interrupt to the host 104. There is also an option to stop the generation of subsequent interrupts, which is controlled by a register setting.
As previously shown and described, the interrupt handler 106 communicates with the memory controller 118 and the host interface controller 122, each of which communicate with other system 100 components via the bus 124. The host 104, and the system memory 108 and its event buffer 110 are also shown connected to the bus 124. As previously explained, a connection as shown in the figure may not actually be a direct connection, but is shown as such for clarity of illustration.
Various context-switchable clients 112 are shown, as well as various legacy clients 114. The context-switchable clients 112 and the legacy clients 114 communicate interrupts to the interrupt handler 106 via respective interfaces 113. The interrupts are stored in an input unit 202, which in an embodiment is a series of first-in-first-out buffers (FIFOs) as shown. The input unit 202, in an embodiment, contains a consumer FIFO for each client interface 113. The input unit 202 receives at least one signal from the clients, including an interrupt occurrence and at least one of an interrupt source identifier and an interrupt type identifier.
An arbiter 204 receives interrupt requests from the input unit 202 and arbitrates among them to determine in what order they will be handled (also referred to as serviced or processed). In an embodiment, the arbitration scheme is a round-robin scheme in which the output of the input unit 202 FIFOs is processed in the order received. In other embodiments, as further described below, other arbitration schemes could be employed, including priority assignment based on information in the interrupts.
Each context-switchable client 112 sends an interrupt request to the interrupt handler 106 along with a context identification (context ID) value. In an embodiment, the client-interrupt handler interface 113 includes a CLIENT_IH_interrupt_send signal that indicates the client is sending the interrupt handler 106 an interrupt. The interface 113 further includes a CLIENT_IH_interrupt_id, which in one embodiment is an interrupt source identification (ID) sent over four cycles. The CLIENT_IH_interrupt_id stays active until an acknowledgement is received. An interrupt source ID uniquely identifies the interrupt source.
The interface 113 further includes a CLIENT_IH_interrupt_ctxid signal. From a context-switchable client 113, the CLIENT_IH_interrupt_ctxid is a Context ID associated with an interrupt and sent over four cycles. In one embodiment, the Context ID is 28-bits. In the case of legacy clients 114, this part of the interface 113 may be used to send supplemental information.
The interface 113 further includes a CLIENT_IH_interrupt_free signal that is transmitted to the sender to indicate the interrupt-sending transaction is complete and the sender is free.
The interface 113 further includes a CLIENT_IH_block_status signal, which is a single null-protocol line used by legacy clients 114. In an embodiment, the CLIENT_IH_block_status signal is the OR of all of the legacy client's interrupt status bits. The CLIENT_IH_block_status signal is made available in the interrupt handler level_status register 232.
The event buffer controller 206 receives interrupts and stores them as ordered event messages in the event buffer 110. The event buffer controller 206 keeps track of an event buffer 110 read pointer (RPTR) 230 and an event buffer 110 write pointer (WPTR) 220 to determine if enough space is available for the current event message. Event buffer full, full drain and overflow conditions are also determined in the event buffer controller 206. If there is enough space in the event buffer 110 and memory write controller 208 is ready, the event message is sent to the memory write controller 208. The event buffer WPTR 220 is incremented when the memory write controller 208 acknowledges write clean of memory write requests. A timestamp of the interrupt request is captured in the memory write controller 208 in units of 128-system clock (128-sclk). In an embodiment, the system clock uses a crystal-based clock counter, which provides a relatively more stable clock. The timestamp is packaged with the interrupt request to form an event message. In an embodiment, the WPTR 220 is a hardware pointer and should not be written under normal operations. In an embodiment, the event buffer controller 206 contains a 32-deep FIFO. This FIFO size can be changed, for performance analysis purposes for example.
For context-switchable interrupt clients, each event message includes at least one of a context ID and an interrupt source ID. For non-context-switchable interrupt clients, each event message includes an interrupt source ID and a flag indicating the non-context switched nature of the interrupt, or a unique context ID as the flag. The event message according to an embodiment is 128 bits as illustrated in Table 1.
Interrupt Source ID
Source Data (context ID or source-specific status)
SCLK counter divided with a prescribed divider (128)
The ISR 105 can decide whether a context ID is present when processing an interrupt by doing a table lookup on the Interrupt Source ID field. The full list of interrupt sources (not shown) indicates which are context-specific. Non-context switched interrupt sources can make use of the Source Data field for interrupt-specific information to be delivered to the system, which reduces register reads for the ISR 105.
In an embodiment, the interrupt handler 106 is responsible for generating the interrupt source ID. One option for identifying the interrupt source is to assign a hard-code ID to each of the interrupt sources based on their input line into the interrupt handler 106. The ISR 105 uses the same set of hard-coded IDs to identify the interrupt source. Another option is to set up an array in the interrupt handler 106 internal memory for software to program each interrupt source with a desirable ID. This involves either an index/data register pair for software to assign an arbitrary interrupt source ID, or a self-incrementing counter for software to write the interrupt source IDs to the array in sequential order. This option allows the ISR 105 flexibility to group interrupt sources that go into the same process code paths. Generally, the ISR 105 should be able to process different interrupt sources with pre-coded values with little overhead, even when some interrupts are processed by the same code path. Some components have multiple sources internally, so they will pass the Source ID explicitly. If there is only one internal source for a particular component, its Source ID may be hard-wired.
The SCLK counter is used as a timestamp for each interrupt triggering event. The timestamp is used by software to trace interrupt-generation, in handling time differences, and in debugging potential interrupt problems such as interrupt loss, overrun, anomaly in servicing time intervals, and performance analysis.
Interrupt sources are listed in a table (not shown) that includes various attributes for each source. A “Source Type” attribute indicates whether the ultimate source in the driving component is a level or pulse. A “Combined I/F To IH” attribute indicates that one interrupt interface covers more than one source. Some level-based interrupt clients may choose to OR their internal interrupt sources together to a single line to the interrupt handler. If the interrupt sources are OR'ed, the ISR first identifies the interrupt client from the event buffer, and reads the interrupt status register in the interrupt client. The mask (if applicable) and acknowledgement is also made in the interrupt client rather than the interrupt handler. Most legacy clients provide access to the individual interrupt signals before they are OR'ed. These can make use of the interface adapter described later.
A “FIFO Depth” attribute specifies how many entries are needed for the data link between an interrupt client and the interrupt handler. This is to account for the latency due to the interrupt handler waiting for previous interrupt requests to go through the memory controller. If the memory controller FIFO is full, the interrupt client is back-pressured to stall.
A “Mask & Clear” attribute indicates whether interrupts are permanently lost when the source is masked, and whether an interrupt source needs a register write to clear. Masks are discussed further below. Level-based interrupts cannot be lost because their level remains high until a clear is received from the ISR 105. Pulse-based interrupts are lost when masked, because the interrupts are transient and there is no sticky status maintained.
A memory write controller 208 receives event messages from the event buffer controller 206 and communicates with the memory controller 118 to request writes to the event buffer 110 in the system memory 108. The memory write controller 208 receives an event message from the event buffer controller 206. In an embodiment, the event buffer controller 206 contains a 32-deep FIFO. This FIFO size can be changed, for performance analysis purposes for example. The event messages are sent to the memory write controller 208 on a debit/credit protocol in an embodiment. The default number of credits is 16. The minimum number of credits to send an event message is two.
The memory controller-interrupt handler interface 109 is used to perform writes of event messages to the event buffer 110. In an embodiment, the interface 109 has an aligned write request size of 8 Bytes, with an 8 Byte data field. In an embodiment, a write mask is included, which indicates when asserted that a particular 1 Byte in the write data should be written to memory. For read/write coherency the memory write controller 208 may use two-phase write-clean signals. Any memory controller interface appropriate to the normal operation of the system is applicable to embodiments as described herein.
A register unit 218 performs register writes and reads in an interrupt handler 106 register decode space. Serial register commands are received from the host interface controller 122. The interrupt handler registers in the register unit 218 are updated based on the de-serialized register command. For register reads, the register value is serialized and sent to the host interface controller 122. The register unit 218 includes the WPTR register 220 and the RPTR register 230. The register unit 218 also includes a WPTR address register 224, a base address register 228, a write overflow register 222, and an event buffer size register 226. The event buffer size register 226 in an embodiment contains the size of the event buffer 110 expressed in log 2 of the actual size in DWORDSs. The value is between 3 and 16. Event buffer size=2^RB_SIZE DWORDs. The event buffer is full when 2^RB_SIZE-1 DWORDs are consumed. A level status register 232 contains the status of each level-based client 114.
The host interface controller-interrupt handler interface 107 is used for the interrupt handler 106 to communicate an interrupt from the interrupt generator 216 to the host 104. The interface 107 is also used by the host 104 to update the RPTR 230 of the interrupt handler 106.
The interrupt handler 106 further includes an interrupt generator 216 that generates an interrupt signal to the host 104 through the host interface controller 122. In an embodiment, the interrupt generator 216 generates rising and falling edges on the an interrupt line. If the event buffer is enabled, the interrupt line is asserted if the RPTR 230 and the WPTR 220 mismatch. If the event buffer is disabled, the interrupt line is asserted based on the OR of client status lines.
A performance counter 210 receives performance signals from all other units in the interrupt controller 106. In an embodiment, two 32-bit performance counters are supported. Events to be profiled are selected from a list in a particular register.
A status unit 212 collects status signals from all the units in interrupt handler 106 and reports them in a status register.
For purposes of illustration, the adapter 116 is shown supporting three independent interrupt source lines, int_line_A, int_line_B, and int_line_C, each supported by an input block 302. Each block 302 also receives an int_type_X signal, and an int_id_X signal. The adapter 116 can support any number of lines with any number of blocks 302. Each line is received by detector (DET) unit 304 that can be configured to handle the protocol of the incoming line. A detected new interrupt event goes to a requester unit (REQ) 306 that asks an arbiter (ARB) 312 to queue a new request into a request FIFO 314. Each line also has its own hard-wired source ID, set by tying off the int_id_X inputs. If a new interrupt event arrives before the request is queued, or the request FIFO overflows, an overrun flag is set. New interrupt events are lost if there is an overrun. Overrun status can be read from a status register 310 by the host via the host interface controller. The OR of all level-type inputs (the output of an OR gate 316) is sent to an interrupt handler status register. In an embodiment the adapter 116 includes line configurations, as shown in Table 2, which determine a line type. Other specific configurations are possible.
Level type, low active
Level type, high active
Pulse type, low active
Pulse type, high active
Various considerations may apply in different embodiments. Some of these are described below.
Accommodation is made in the interrupt handler for legacy interrupt clients that would like to remain unchanged. As previously discussed, legacy interrupts clients use level-based interrupts. When such a client generates an interrupt, it raises its interrupt line. When the ISR has serviced the interrupt, the corresponding register “ACK” bit is cleared by software, and the level goes down. The interrupt handler communicates with the host interface controller with a level-based line. The host interface controller detects the rising and falling edges of the line and generates ASSERT/DE-ASSERT signals (or an MSI message) to the system depending on whether MSI is enabled. The interrupt handler makes a logical OR among all level-based interrupt clients. The interrupt handler also makes a comparison between the read pointer and the write pointer. The interrupt line keeps its level high if any level-based interrupt client has its level high, or when the read pointer and the write pointer mismatch. The line goes low when all level-based interrupts are cleared and the read/write pointers equal. One implication for this level-based interface is that, when MSI is enabled, a “re-arm” mechanism needs to be implemented to trigger another interrupt event for any interrupts remaining unprocessed when the ISR returns to the OS. This implication is further explained in the paragraphs below.
There are two scenarios in which interrupt generation is handled in different ways because the MSI may be enabled or disabled by the system. In both cases below, the ISR is responsible to keep the read pointer register updated when servicing interrupts, and to clear level-based interrupt status registers.
When MSI is disabled, interrupts are handled by system software in the same way as level-based interrupts; that is via the INTx mechanism to check/clear interrupts. Hardware sends ASSERT signal to set INTx when there is an outstanding interrupt, and sends DE-ASSERT signal to clear INTx when there is no outstanding interrupt. The host interface controller detects the rising and falling edges from the interrupt handler. A rising edge triggers an ASSERT signal to the system, and a falling edge triggers a DE-ASSERT signal to the system.
Generation of a new interrupt will set the IH_host-interface-controller interrupt line to high, which will trigger an ASSERT. If the line is already high, a new interrupt generated will have no effect because INTx is already set, and a new ASSERT is ignored by the system. When the ISR finishes processing and returns to the caller (e.g., the OS), if there is an outstanding interrupt, the caller will call the ISR again because INTx has not been cleared.
When all interrupts are processed, the read and write pointers will be equal (and the write pointer overflow bit is cleared), and all level-based interrupts are cleared. In that case the IH→host-interface-controller interrupt line goes low, which triggers a DE-ASSERT signal to clear INTx.
In an MSI-enabled environment, interrupts are signaled by messages (as memory write requests) rather than levels. A new message needs to be sent by hardware if the ISR did not process all outstanding interrupts in its previous run. For example, there can be a second interrupt generated during the ISR processing of the first interrupt. The ISR is unaware of the second interrupt because it has passed the point of reading the write pointer, or it has passed reading the interrupt status register. When the ISR returns to the caller, the second interrupt remains unprocessed. Hardware needs to recognize this outstanding interrupt and issue another MSI event. Otherwise, unless there are subsequent interrupts, the second interrupt is effectively lost. Even if there is third interrupt coming, the ISR has to wait longer to catch the second interrupt, which may not be a good option for performance reasons.
The host interface controller detects the rising edges from the interrupt handler. A rising edge triggers an MSI message. Falling edges are ignored. If there is a second interrupt generated while the first one has not been cleared, the IH→host-interface-controller interrupt line will remain high. There will be no rising edge for the second interrupt, so there will not be a new MSI message. To solve this issue, a “re-arm” mechanism injects a temporal low-level in the IH→host-interface-controller interrupt line in order to get another rising edge. The new rising edge will then trigger a new MSI message to the system. The pulse needs to be maintained for two or more cycles to safeguard the pulse detection in the host interface controller.
In order to “re-arm,” the ISR programs a “re-arm” register every time before it returns to the caller. This gives the system an opportunity to generate a new MSI message to call the ISR again, if there is an outstanding interrupt. When the event buffer is enabled, because the ISR needs to update the read pointer each time, writing to read pointer serves as a trigger for the interrupt handler to determine if read pointer=write pointer, and if all levels from legacy clients are low. A pulse is inserted on the IH→host-interface-controller line if either of the two conditions is not met. When the event buffer is disabled, the check of read pointer=write pointer is suppressed and only levels for legacy clients are checked. For consistency, writing to the read pointer again serves as a re-arm trigger.
For pulse-based interrupts, masking new interrupts would mean their permanent loss. This is because they are temporal interrupts without a sticky status register. When the mask is turned on, an interrupt is not triggered. When the mask is turned off, the interrupts are already gone. Whether this is acceptable depends on how software will be using those interrupt masks. In some cases, all masks are on at initialization time. When an ISR client registers, the corresponding mask is turned off, and that interrupt is enabled. Of course, an ISR client can come and go dynamically, but the client would not be interested in past interrupts (before its registration time). It should be acceptable for such clients to lose older interrupts from before their lifetime. There are some exceptional interrupts which gets masked on/off from time to time without re-registering. In this case, an additional interrupt may be added after turning off the mask. Masking level-based interrupts does not cause any loss.
Aspects of the embodiments described above may be implemented as functionality programmed into any of a variety of circuitry, including but not limited to programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices, and standard cell-based devices, as well as application specific integrated circuits (ASICs) and fully custom integrated circuits. Some other possibilities for implementing aspects of the embodiments include microcontrollers with memory (such as electronically erasable programmable read only memory (EEPROM)), embedded microprocessors, firmware, software, etc. Furthermore, aspects of the embodiments may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. Of course the underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (MOSFET) technologies such as complementary metal-oxide semiconductor (CMOS), bipolar technologies such as emitter-coupled logic (ECL), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, etc.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number, respectively. Additionally, the words “herein,” “hereunder,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word, any of the items in the list, all of the items in the list, and any combination of the items in the list.
The above description of illustrated embodiments of the system and method is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the system and method are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. The teachings of the disclosure provided herein can be applied to other systems, not only for systems including graphics processing or video processing, as described above. The various operations described may be performed in a very wide variety of architectures and distributed differently than described. In addition, though many configurations are described herein, none are intended to be limiting or exclusive.
In other embodiments, some or all of the hardware and software capability described herein may exist in a printer, a camera, television, a digital versatile disc (DVD) player, a handheld device, a mobile telephone or some other device. The elements and acts of the various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the system and method in light of the above detailed description.
In general, in the following claims, the terms used should not be construed to limit the system and method to the specific embodiments disclosed in the specification and the claims, but should be construed to include any processing systems and methods that operate under the claims. Accordingly, the system and method is not limited by the disclosure, but instead the scope of the method and system is to be determined entirely by the claims.
While certain aspects of the method and system are presented below in certain claim forms, the inventors contemplate the various aspects of the method and system in any number of claim forms. For example, while only one aspect of the system and method may be recited as embodied in computer-readable medium, other aspects may likewise be embodied in computer-readable medium. Accordingly, the inventors reserve the right to add additional claims after filing the application to pursue such additional claim forms for other aspects of the system and method.
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|Classification aux États-Unis||710/261, 710/269|
|5 mai 2006||AS||Assignment|
Owner name: ATI TECHNOLOGIES, INC., CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GROSSMAN, MARK;CHENG, JEFFREY G.;CARUK, GORDON;AND OTHERS;REEL/FRAME:017871/0767;SIGNING DATES FROM 20060420 TO 20060503
Owner name: ATI TECHNOLOGIES, INC.,CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GROSSMAN, MARK;CHENG, JEFFREY G.;CARUK, GORDON;AND OTHERS;SIGNING DATES FROM 20060420 TO 20060503;REEL/FRAME:017871/0767
|4 sept. 2013||FPAY||Fee payment|
Year of fee payment: 4