US7827452B2 - Error catch RAM support using fan-out/fan-in matrix - Google Patents
Error catch RAM support using fan-out/fan-in matrix Download PDFInfo
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- US7827452B2 US7827452B2 US11/895,512 US89551207A US7827452B2 US 7827452 B2 US7827452 B2 US 7827452B2 US 89551207 A US89551207 A US 89551207A US 7827452 B2 US7827452 B2 US 7827452B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Definitions
- Automated test equipment utilizes its channels to drive signals to or receive signals from a device under test (DUT).
- DUT device under test
- Each device under test is typically comprised of address PINs, control PINs, and data PINs.
- the automated test equipment has used dedicated PIN electronics channels for the data PINS.
- the PIN electronics channels for the data lines were not shared by multiple devices under test.
- Another drawback in the past to testing multiple devices has been the lack of electrical isolation between devices in performing data reads from the devices.
- a bad device under test can unnecessarily cause the other device under test to appear damaged or of low quality.
- the lack of electrical isolation when reading from the second device under test can cause a second device under test to perform poorly.
- the second device under test might be categorized as substandard.
- an apparatus for obtaining test data from multiple devices.
- the test apparatus can be comprised of a test signal generator configured to output from the testing device a first test signal for input in parallel to at least two devices in the test.
- the testing device can also include a response signal receiver configured to input in parallel to the testing device at least two response signals, each response signal produced by one of the devices in the test in response to the first test signal.
- the testing device can include a storage device such as a memory configured to store the response signals received in parallel.
- a serial output circuit can be configured to serially output the response signals from the storage device.
- a method of obtaining test data from multiple devices can be implemented by outputting from a testing device a first test signal and inputting the test signal in parallel to at least two devices under test; inputting in parallel to the testing device at least two response signals, each response signal produced by one of the two devices under test in response to the first test signal; storing the response signal received in parallel in a storage device; and serially outputting the response signals from the storage device for use in testing analysis.
- FIG. 1 illustrates a block diagram of a parallel testing arrangement of multiple devices under test, according to one embodiment of the invention.
- FIG. 2 illustrates a block diagram of a computing device which can be utilized to implement the automated test equipment shown in FIG. 1 .
- FIG. 3 illustrates a block diagram of an automated testing device for parallel testing of multiple devices under test, according to one embodiment of the invention.
- FIG. 4 illustrates an example of a timing diagram which can be utilized with the circuit shown in FIG. 3 in accordance with one embodiment of the invention.
- FIG. 5 illustrates a flowchart demonstrating a method of parallel testing of devices under test in accordance with one embodiment of the invention.
- FIGS. 6A and 6B illustrate a flowchart demonstrating a method of parallel testing of multiple devices under test in accordance with one embodiment of the invention.
- FIG. 1 illustrates the coupling of multiple devices 1 through N for testing by automated test equipment 104 .
- FIG. 1 illustrates a circuit 100 in which automated test equipment 104 is electrically coupled with devices 108 , 112 , 116 , and 120 . These devices represent devices under test and can essentially be any number of devices that can be configured in parallel so that the automated test equipment can provide input and receive output to and from the devices, respectively.
- FIG. 2 a block diagram 200 is shown that can be utilized to implement the system requirements for the automated test device shown in FIG. 1 .
- FIG. 2 broadly illustrates how individual system elements can be implemented.
- System 200 is shown comprised of hardware elements that are electrically coupled via bus 208 , including a processor 201 , input device 202 , output device 203 , storage device 204 , computer-readable storage media reader 205 a , communications system 206 processing acceleration (e.g., DSP or special-purpose processors) 207 and memory 209 .
- Computer-readable storage media reader 205 a is further coupled to computer-readable storage media 205 b , the combination comprehensively representing remote, local, fixed and/or removable storage devices plus storage media, memory, etc.
- System 200 for temporarily and/or more permanently containing computer-readable information, which can include storage device 204 , memory 209 and/or any other such accessible system 200 resource.
- System 200 also comprises software elements (shown as being currently located within working memory 291 ) including an operating system 292 and other code 293 , such as programs, applets, data and the like.
- System 200 has extensive flexibility and configurability. Thus, for example, a single architecture might be utilized to implement one or more servers that can be further configured in accordance with currently desirable protocols, protocol variations, extensions, etc. However, it will be apparent to those skilled in the art that embodiments may well be utilized in accordance with more specific application requirements.
- one or more system elements might be implemented as sub-elements within a system 200 component (e.g. within communications system 206 ). Customized hardware might also be utilized and/or particular elements might be implemented in hardware, software (including so-called “portable software,” such as applets) or both.
- connection to other computing devices such as network input/output devices (not shown) may be employed, it is to be understood that wired, wireless, optical, modem and/or other connection or connections to other computing devices might also be utilized.
- FIG. 3 illustrates a system that can be utilized to read in parallel manner from multiples devices under test and relay the information in a high speed serial fashion across a PIN electronics channel. This permits a single channel to be utilized for driving and receiving information to data lines of multiple devices under test. Furthermore, it allows multiple devices under test to be tested concurrently (i.e., in parallel) without increasing test time overhead.
- FIG. 3 shows a testing device 304 in which a channel 305 is coupled with an intermediate circuit 308 .
- Circuit 308 is used to fan out the signals driven by device 304 to multiple devices under test, shown as devices 312 , 316 , and 320 .
- the ellipses illustrate that multiple devices can be tested.
- block 324 shows a symbolic representation of a PIN electronics channel that can drive and receive signals. Comparators are shown for purposes of testing the signals received on channel 305 .
- device 304 is also shown as including test logic block 332 that is utilized to perform data analysis once test data is received from a device under test.
- block 328 shows an error catch RAM that can be utilized to store test information for a device under test. For example, a RAM device can be tested so as to create a bit map of the RAM under test. This information can be stored in the error catch RAM so as to determine which rows or columns should be replaced due to manufacturing defects.
- the circuit shown in block 308 can be utilized in accordance with one embodiment of the invention to fan out a single PIN electronics channel 305 to multiple devices under test.
- a single PIN electronics channel would be dedicated to a data PIN of a device under test or would require serial electrical coupling to multiple devices under test.
- the circuit shown in block 308 allows the PIN electronics channel 305 to drive and receive signals from multiple devices while reading data from the devices in a parallel manner. This introduces no test time overhead. In the past, serial reads produced significant test time overhead and thus discouraged such serial testing.
- Block 308 shows that PIN electronics channel 305 can fan out a signal driven by automated test circuit 304 by utilizing buffer 347 to fan out the signal to buffers 354 , 355 , and 356 . These buffers drive the signal to devices 312 , 316 , and 320 , respectively.
- the read can be accomplished in parallel fashion.
- the data lines of devices 312 , 316 , and 320 are shown as electrically coupled with comparators 351 , 352 , and 353 in FIG. 3 .
- the comparators perform a voltage level test by comparing the input voltage signal to a reference voltage signal.
- the comparators then drive latches 346 , 345 , and 344 . These latches are clocked so as to latch the input signals at the appropriate time.
- the output of the latches are then electrically coupled with a memory device, such as serial shifter 336 .
- a parallel read of the signals can then be accomplished by the serial shifter 336 .
- the signals can be output in serial fashion by utilizing sequencer 340 to sequence out the data.
- Buffer 348 drives the signals across channel 305 to PIN electronics circuit 324 , which again performs a voltage level test on the input signals.
- the serial stream of bits output by circuit 308 can then be manipulated by the test logic 332 to associate an individual bit with its corresponding device under test.
- the signal can be compared to an expected value so as to determine whether the device is operating correctly. If the device is not operating correctly, the error can be stored in the error catch RAM circuit 328 .
- Logic tests can be performed on each bit of the serial stream so as to collect test data for each of the devices under test.
- a single PIN electronics channel can be utilized not only to drive and receive information, but also to drive and receive information from multiple devices.
- This embodiment also allows the test equipment to perform parallel reads of data from these multiple devices while not introducing test time overhead. No test time overhead is introduced because the serial data stream can convey the entire amount of collected data before a subsequent read operation is performed and loaded into the latches.
- FIG. 3 also illustrates that circuit 308 provides electrical isolation between the devices under test during read operations.
- Each device under test is coupled only to its associated comparator and is not electrically coupled with data lines of other devices being tested. Thus, if one of the devices under test fails, the other devices are not affected by that failure. Consequently, one can reliably test the other devices without worrying about the effects on those other devices caused by the failed device under test.
- the time slicing approach for sending data back to the testing device circuit 304 relies on the fact that a tester channel typically can operate much faster than a device under test at that time. For example, it is typical to be able to receive data in a PIN electronics channel at speeds of 600 or 800 Mbs, whereas a typical nonvolatile memory operates below 50 Mbs.
- serial transfer performed by sequencer 340 and serial shifter 336 can occur in the background between subsequent device under test goals. This is shown, for example, in the example timing diagram shown in FIG. 4 .
- the timing diagram shown in FIG. 4 shows that four devices under test are being utilized.
- the latches latch the results of the comparators when the STBCLK and CMPLE are true. Subsequent to this, the timing diagram shows that all four bits from the associated four devices are sequenced through using both edges of STBCLK to send error catch RAM data (ECRD) back to the testing device circuit 304 .
- ECRD error catch RAM data
- the ECRDS signal shown in FIG. 4 selects which bit is to be sent out through the high-speed serial shifter. When ECRDS is 3, this will enable the serial shifter via CMPLE such that in the next strobe, a new set of level detected outputs are latched from the comparators. The sequence will then repeat for every compare cycle.
- FIG. 3 shows the STBCLK signal as providing an initial leading edge that initiates the clocking of data out from circuit 308 to testing device 304 .
- This initial leading edge can be generated by the test circuit 304 while subsequent transitions of STBCLK clock out subsequent bits from the serial shifter.
- Signal DRV/RCV illustrates the timing signal for when the channel is operating in a drive or receive mode.
- signal ECRDS provides values to indicate which bit should be output from the serial shifter.
- Signal CMPLE provides the signal for compare latch enable.
- signal ECRD shows when the comparators A through D are latched.
- the remaining three timing signals shown in FIG. 4 illustrate the transfer of information to the testing device circuit 304 .
- the signal represented as TESTER_IO illustrates when the channel 305 is operating in a drive cycle or a receive cycle. It also illustrates a transition from the drive cycle to the receive cycle and from the receive cycle to the drive cycle. Furthermore, it illustrates the sequential transmission of data read from the devices under test as producing the following sequence of data: ECRAA, ECRAB, ECRAC, ECRAD, ECRBA, ECRBB, ECRBC, ECRBD.
- Signal PE_IO indicates the previous signal with the time delay introduced by transmission delay across channel 305 .
- signal DATA_STB indicates a data strobe signal that can be utilized to clock data capture from the PE_IO signal for use by the logic test circuitry. This data strobe signal can be adjusted so as to fall within the middle portion of the data stream so as to produce the most reliable read of the high-speed data stream of information.
- Block 504 shows that output such as a first test signal is driven from a testing device for input in parallel to multiple devices under test.
- Block 508 illustrates that parallel reads from the devices under test can be made such that each response signal produced by the device under test is read in response to the first test signal that was driven by the testing device.
- the response signals are stored in a storage device.
- the stored response signals are output serially from the storage device. For example, the serial output is transmitted to logic circuitry for use in creating of entries in the error catch RAM.
- FIGS. 6A and 6B illustrate a flowchart 600 that demonstrates another embodiment of the invention.
- a first test signal is output from a testing device for input in parallel to at least two devices under test.
- the testing device receives response signals, e.g., at least two response signals, that are input in parallel to the testing device, wherein each response signal is produced by one of the devices under test in response to the preceding test signal.
- each response signal is tested with a dedicated comparator.
- each response signal is latched with a dedicated latch.
- the response signals are received in parallel and stored in a storage device.
- block 624 shows that the response signals can be read in parallel into a serial shifter where they are stored and the serial shifter serves as the storage device.
- the response signals are output in serial fashion from the storage device.
- block 632 shows that the serial output can be accomplished by driving the stored response signals to logic circuitry that can then store error information in an error catch RAM.
- parallel reads are enabled from multiple devices under test with error catch RAM support. This significantly reduces the test time overhead in testing multiple devices using the fan out/fan in testing approach.
- one embodiment of the invention enables the user to fully share not only address and control PIN electronics across multiple devices, but also to share tester channels being used as data I/O. This can increase the parallelism of an existing tester.
- the fan out/fan in is done using active components, when a device fails, it allows for isolation of the failing device.
- the failing device can be turned off while testing of other devices continues. This can be important especially in wafer sort due to the difficulty of wafer sort not being able to retest devices that were affected by a failing device.
- one embodiment allows the sharing of a single line between a tester and the new circuit shown as circuit 308 in FIG. 3 .
- the serial communication along this line reduces the total number of lines needed between the tester and the devices under test.
- the embodiments of the invention may be embodied as code stored in a computer-readable memory of virtually any kind including, without limitation, RAM, ROM, magnetic media, optical media, or magneto-optical media. Even more generally, the embodiments of the invention could be implemented in software, or in hardware, or any combination thereof including, but not limited to, software running on a general purpose processor, microcode, PLAs, or ASICs.
- embodiments of the invention could be accomplished as computer signals embodied in a carrier wave, as well as signals (e.g., electrical and optical) propagated through a transmission medium.
- signals e.g., electrical and optical
- the various information discussed above could be formatted in a structure, such as a data structure, and transmitted as an electrical signal through a transmission medium or stored on a computer readable medium.
Abstract
Description
Claims (20)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/895,512 US7827452B2 (en) | 2007-08-24 | 2007-08-24 | Error catch RAM support using fan-out/fan-in matrix |
US12/035,378 US8384410B1 (en) | 2007-08-24 | 2008-02-21 | Parallel test circuit with active devices |
CN200880104187A CN101809883A (en) | 2007-08-24 | 2008-08-20 | Error catch RAM support using fan-out/fan-in matrix |
KR1020107006340A KR101503555B1 (en) | 2007-08-24 | 2008-08-20 | Error catch ram support using fan-out/fan-in matrix |
PCT/US2008/073740 WO2009029454A1 (en) | 2007-08-24 | 2008-08-20 | Error catch ram support using fan-out/fan-in matrix |
TW097132182A TWI490874B (en) | 2007-08-24 | 2008-08-22 | Error catch ram support using fan-out/fan-in matrix |
Applications Claiming Priority (1)
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US11/895,512 US7827452B2 (en) | 2007-08-24 | 2007-08-24 | Error catch RAM support using fan-out/fan-in matrix |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/035,378 Continuation-In-Part US8384410B1 (en) | 2007-08-24 | 2008-02-21 | Parallel test circuit with active devices |
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US20090055690A1 US20090055690A1 (en) | 2009-02-26 |
US7827452B2 true US7827452B2 (en) | 2010-11-02 |
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US11/895,512 Active 2028-10-22 US7827452B2 (en) | 2007-08-24 | 2007-08-24 | Error catch RAM support using fan-out/fan-in matrix |
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US (1) | US7827452B2 (en) |
KR (1) | KR101503555B1 (en) |
CN (1) | CN101809883A (en) |
TW (1) | TWI490874B (en) |
WO (1) | WO2009029454A1 (en) |
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CN105281713A (en) * | 2014-07-10 | 2016-01-27 | 厦门雅迅网络股份有限公司 | Simulation circuit of sensor signal |
KR20200016680A (en) * | 2018-08-07 | 2020-02-17 | 삼성전자주식회사 | Test Device and Test Method reducing peak noise and Semiconductor Device under test |
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2007
- 2007-08-24 US US11/895,512 patent/US7827452B2/en active Active
-
2008
- 2008-08-20 KR KR1020107006340A patent/KR101503555B1/en active IP Right Grant
- 2008-08-20 WO PCT/US2008/073740 patent/WO2009029454A1/en active Application Filing
- 2008-08-20 CN CN200880104187A patent/CN101809883A/en active Pending
- 2008-08-22 TW TW097132182A patent/TWI490874B/en active
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Also Published As
Publication number | Publication date |
---|---|
TWI490874B (en) | 2015-07-01 |
TW200915332A (en) | 2009-04-01 |
US20090055690A1 (en) | 2009-02-26 |
CN101809883A (en) | 2010-08-18 |
KR20100084153A (en) | 2010-07-23 |
KR101503555B1 (en) | 2015-03-17 |
WO2009029454A1 (en) | 2009-03-05 |
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