US7925030B2 - Crosstalk cancellation using load impedence measurements - Google Patents
Crosstalk cancellation using load impedence measurements Download PDFInfo
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- US7925030B2 US7925030B2 US11/482,595 US48259506A US7925030B2 US 7925030 B2 US7925030 B2 US 7925030B2 US 48259506 A US48259506 A US 48259506A US 7925030 B2 US7925030 B2 US 7925030B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04S—STEREOPHONIC SYSTEMS
- H04S1/00—Two-channel systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R5/00—Stereophonic arrangements
- H04R5/033—Headphones for stereophonic communication
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04S—STEREOPHONIC SYSTEMS
- H04S1/00—Two-channel systems
- H04S1/002—Non-adaptive circuits, e.g. manually adjustable or static, for enhancing the sound image or the spatial distribution
- H04S1/005—For headphones
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04S—STEREOPHONIC SYSTEMS
- H04S7/00—Indicating arrangements; Control arrangements, e.g. balance control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04S—STEREOPHONIC SYSTEMS
- H04S7/00—Indicating arrangements; Control arrangements, e.g. balance control
- H04S7/30—Control circuits for electronic adaptation of the sound field
Definitions
- the present invention relates to systems for amplifying electronic signals. More particularly, and not by way of limitation, the present invention is directed to a system and method for canceling crosstalk between multiple channels using load impedance measurements.
- Driving a stereo headset is a common requirement in today's mobile phones. There is a requirement to minimize the number of pins in the headset connector, and also to adhere to the standard headset connector found on most home music equipments.
- the standard headset has a three-terminal connector with left, right, and ground terminals. No DC current is allowed to flow through the headset. This requires the left and right signals to be an AC signal with a zero-volt DC offset. Such a signal may be generated using an amplifier with a positive and negative voltage supply. However, a negative supply is not readily available in a device operated by a single battery.
- FIG. 1A is a simplified schematic drawing of a common configuration of stereo amplifiers for generating a stereo signal (i.e., left signal and right signal).
- the signal, V in1 is fed into a first single-ended output amplifier (Output AMP 1 ) 11
- the signal V in2 is fed into a second single-ended output amplifier (Output AMP 2 ) 12 .
- the output amplifiers are providing the signal to a load such as headphones, speakers, etc. (not shown).
- the output amplifiers have a common-mode DC voltage equal to VDD/2.
- DC-blocking capacitors (C L1 and C L2 ) 13 and 14 are used.
- the DC-blocking capacitors are needed in the absence of a negative voltage supply.
- a drawback with the DC-blocking capacitors is that they typically are 100-200 ⁇ F, each of which occupies significant area on a printed circuit board (PCB).
- FIG. 1B is a simplified schematic drawing of another common configuration of stereo amplifiers for generating a stereo signal.
- This configuration utilizes a reference voltage supply (VMID) 15 .
- the VMID driver is implemented as a reference amplifier (Reference AMP) 16 and provides half the voltage of the power supply (VDD/2) as a reference DC voltage level.
- a first output load (R L1 ) 17 is connected between Output AMP 1 11 and the Reference AMP.
- a second output load (R L2 ) 18 is connected between Output AMP 2 12 and the Reference AMP.
- the main reason for using the Reference AMP is to eliminate the DC blocking capacitors C L1 and C L2 , thereby reducing the PCB area occupied and reducing the number of pins in the headphone jack.
- FIG. 2 illustrates a problem that arises when using the Reference AMP 16 for the output amplifier loads.
- the primary source of crosstalk is an output impedance (R int ) 19 in the Reference AMP 16 .
- the present invention improves the crosstalk figure with crosstalk cancellation.
- Other advantages include the fact that the invention can be implemented in the digital region of an ASIC while using a minumum of silicon area.
- a low cost, low performance analog input amplifier, or an amplifier already existing in the ASIC, can be used as a measuring amplifier.
- the calculations performed in the present invention also provide a load resistance figure connected to the output amplifier. This information can be used to send a warning message to the user indicating that the load is not acceptable for the system.
- the stability of the Reference AMP can indirectly be improved if the Reference AMP stability improves when adding a serial resistance between the Reference AMP and the load.
- the present invention is directed to a method of canceling crosstalk between a first stereo channel and a second stereo channel, wherein a first signal is input to a first output amplifier for the first channel, and a second signal is input to a second output amplifier for the second channel, and an output load for each output amplifier is connected between each output amplifier and a reference amplifier.
- the method includes splitting the first and second signals prior to inputting the signals to the first and second output amplifiers; and adding a split portion of each signal to the other signal on the inputs of the first and second output amplifiers.
- the step of adding a split portion of each signal to the other signal may include adjusting each split signal by a programmable gain amplifier before adding the split signal to the other signal.
- the present invention is directed to a method of canceling crosstalk between a first stereo channel and a second stereo channel, wherein a first signal is input to a first output amplifier for the first channel, and a second signal is input to a second output amplifier for the second channel, and an output load for each output amplifier is connected between each output amplifier and a reference amplifier.
- the method includes splitting the first signal onto a first path and a second path prior to an input of the second output amplifier, and adjusting the first signal on the first path by a first programmable gain amplifier.
- the second signal is split onto a third path and a fourth path prior to an input of the second output amplifier.
- the second signal on the third path is adjusted by a second programmable gain amplifier.
- the adjusted second signal on the third path is added to the first signal on the second path to create a first sum
- the adjusted first signal on the first path is added to the second signal on the fourth path to create a second sum.
- the first sum is input to the first output amplifier
- the second sum is input to the second output amplifier.
- the present invention is directed to a method of canceling crosstalk between a first stereo channel and a second stereo channel, wherein a first signal is input to a first output amplifier for the first channel, and a second signal is input to a second output amplifier for the second channel, and an output load for each output amplifier is connected between each output amplifier and a reference amplifier.
- the method includes splitting the first and second input signals into two paths each; inputting a first path of each signal to each signal's respective output amplifier; adding together a second path of the first and second signals; adjusting the sum of the first and second signals by a gain function; adding a suitable DC bias to the adjusted sum, and inputting the biased adjusted sum to the reference amplifier.
- the present invention is directed to a Mixed Signal Application Specific Integrated Circuit (ASIC) of a mobile phone platform.
- the ASIC provides a first stereo channel and a second stereo channel to a headphone jack.
- the ASIC includes first and second output amplifiers.
- the first output amplifier amplifies a first input signal for the first channel, and supplies the first amplified signal to a first load associated with the headphone jack.
- the second output amplifier amplifies a second input signal for the second channel, and supplies the second amplified signal to a second load associated with the headphone jack.
- a reference amplifier provides a reference signal between the first and second loads.
- the ASIC also includes a crosstalk cancellation unit for canceling crosstalk between the first and second channels.
- the crosstalk cancellation unit includes means for splitting the first and second signals prior to inputting the signals to the first and second output amplifiers; and means for adding a split portion of each signal to the other signal on the inputs of the first and second output amplifiers.
- the present invention is directed to a Mixed Signal ASIC of a mobile phone platform.
- the ASIC provides a first stereo channel and a second stereo channel to a headphone jack.
- the ASIC includes first and second output amplifiers.
- the first output amplifier amplifies a first input signal for the first channel, and supplies the first amplified signal to a first load associated with the headphone jack.
- the second output amplifier amplifies a second input signal for the second channel, and supplies the second amplified signal to a second load associated with the headphone jack.
- a reference amplifier provides a reference signal between the first and second loads.
- the ASIC also includes a crosstalk cancellation unit for canceling crosstalk between the first and second channels.
- the crosstalk cancellation unit includes first and second splitters for splitting the first and second input signals into two paths each; means for inputting a first path of each signal to each signal's respective output amplifier; and an adder for adding together a second path of the first and second signals.
- the crosstalk cancellation unit also includes a gain amplifier for adjusting the sum of the first and second signals and adding a suitable DC bias to the adjusted sum; and means for inputting the biased adjusted sum to the reference amplifier.
- FIG. 1B (Prior Art) is a simplified schematic drawing of another common configuration of stereo amplifiers for generating a stereo signal
- FIG. 2 (Prior Art) illustrates a problem that arises when using the Reference AMP for the output amplifier loads
- FIG. 3 is a simplified schematic drawing of an amplifier configuration in accordance with a first embodiment of the present invention.
- FIG. 4 is a simplified schematic drawing of an amplifier configuration in accordance with a second embodiment of the present invention.
- FIG. 5 is a simplified schematic drawing of an implementation of an amplifier configuration in an existing Mixed Signal ASIC of a mobile phone platform in accordance with the first embodiment of the present invention
- FIG. 6 is a flow chart illustrating the steps of a first embodiment of the method of the present invention.
- FIG. 7 is a flow chart illustrating the steps of a second embodiment of the method of the present invention.
- the present invention is directed to a system and method for canceling crosstalk between multiple channels using load impedance measurements.
- Two exemplary embodiments are described herein in the context of an exemplary two-channel system.
- the signal from each channel is added to the other channel on the input of the output amplifiers.
- the signals from both channels are added on the input of the reference amplifier.
- the amount of crosstalk can be calculated using the equation R int /R L , where R int is the Reference AMP output impedance, and R L is the load. This can be shown to be true from the following calculations. To simplify the calculations, certain assumptions regarding the amplifiers and their connected loads are made. The amplifiers are assumed to be linear and to have a flat frequency response within the audio frequency range (f ⁇ 20 kHz). It is also assumed that the amplifier loads are not frequency dependent for the audio frequency range (f ⁇ 20 kHz).
- FIG. 3 is a simplified schematic drawing of an amplifier configuration in accordance with the first embodiment of the present invention.
- the signal from each channel is added to the other channel on the input of the output amplifiers.
- the signal V 1 is converted by a digital-to-analog (D/A) converter 20 a and fed into a first single-ended output amplifier (Output AMP 1 ) 21
- the signal V 2 is converted by a D/A converter 20 b and fed into a second single-ended output amplifier (Output AMP 2 ) 22
- a reference voltage supply (VMID) 23 is implemented as an input to a reference amplifier (Reference AMP) 24 .
- the Reference AMP has an internal output impedance R 0 25 , and generates a reference signal, which may be a reference DC voltage level.
- a first output load (R A ) 26 is connected between Output AMP 1 21 and the Reference AMP.
- a voltage drop V A is associated with the first output load R A .
- a second output load (R B ) 27 is connected between Output AMP 2 22 and the Reference AMP.
- a voltage drop V B is associated with the second output load R B .
- the signal V 1 is split prior to Output AMP 1 21 , and is routed through a gain function ⁇ 28 to an adder 29 where the signal V 1 is added to the signal V 2 .
- the signal V 2 is split prior to Output AMP 2 22 , and is routed through a gain function ⁇ 30 to an adder 31 where the signal V 2 is added to the signal V 1 .
- the gain functions ⁇ and ⁇ and the adders may be implemented in the digital domain, as shown, or in the analog domain. In the digital domain, the gain functions ⁇ and ⁇ may be implemented using programable gain amplifiers (PGAs). In the analog domain, the variable amplification and summing operations may be implemented using, for example, variable and fixed resistors.
- V A and V B are the signals that will appear over the resistive loads R A and R B , respectively. Without loss of generality, all amplifiers are assumed to have 0 dB gain.
- the output signals V A and V B will be affected by the amount of added crosstalk signal on each channel as shown by:
- the first embodiment cancels out the small amount of signal level from one channel that occurs over the load resistance in the other channel by adding the same amount of inverted signal level at the input of the amplifiers.
- FIG. 4 is a simplified schematic drawing of an amplifier configuration in accordance with the second embodiment of the present invention.
- the signals from both channels are added on the input of the reference amplifier.
- the signals V 1 and V 2 are split prior to their respective Output AMPs, and are routed through an adder 33 and a gain function ⁇ 34 .
- a suitable DC bias, VMID 23 is added to the adjusted sum before voltage V 0 is applied to the Reference AMP 24 .
- the Reference AMP generates a reference signal, which may be a reference DC voltage level. Note that the added DC bias may be zero, depending on the values of V 1 and V 2 , respectively.
- the calculations below begin by showing that V A and V B are the signals that will appear over the resistive loads R A and R B , respectively. Without loss of generality, all amplifiers are assumed to have 0 dB gain.
- V 0 - V 1 ⁇ R 0 ⁇ ⁇ R B R A + R 0 ⁇ ⁇ R B - V 2 ⁇ R 0 ⁇ ⁇ R A R B + R 0 ⁇ ⁇ R A ( 8 )
- the output signals V A and V B will be affected by the amount of added crosstalk signal on each channel, as shown by:
- V A V 1 ⁇ R A - R 0 ⁇ ⁇ R B R A + R 0 ⁇ ⁇ R B
- V B V 2 ⁇ R B - R 0 ⁇ ⁇ R A R A + R 0 ⁇ ⁇ R A ( 10 )
- V A V 1 ⁇ R - R 0 R + R 0
- V B V 2 ⁇ R - R 0 R + R 0 ( 11 )
- FIGS. 3 and 4 can easily be implemented and used for crosstalk cancellation.
- only the first embodiment is chosen here to show how an implementation can be done in an existing Mixed Signal ASIC of a mobile phone platform.
- FIG. 5 is a simplified schematic drawing of an implementation of an amplifier configuration in a Mixed Signal Application Specific Integrated Circuit (ASIC) of a mobile phone platform in accordance with the first embodiment of the present invention.
- the crosstalk level increases as the load resistance decreases. For example, a 16 ⁇ headset will have larger crosstalk than a 32 ⁇ headset. If the platform cannot predict the impedance of the load, the impedance must be measured.
- the load impedance is determined by calculating the relationship between the load impedance (R L1 and R L2 ) and the resistance in serial of R L (R L1 and R L2 ) and R S (R S1 and R S2 ).
- the arrangement is implemented entirely in the analog domain, and thus the digital-to-analog (D/A) converters 20 a and 20 b , and the analog-to-digital (A/D) converter 43 are not present.
- the variable gain and summing operations performed in the crosstalk cancellation section may be performed by variable and fixed resistors.
- An analog amplifier 35 measures the impedance level and sends the information to an analog PGA gain calculator 36 . If the headset is equipped with two cords to each headphone speaker, as found in a stereo headset, the total cord impedance is included in R L1 and R L2 and can be measured.
- the crosstalk cancellation circuit and the PGA gain calculator are digital, and PGA 1 40 and PGA 2 41 are utilized in the crosstalk cancellation circuit to perform the variable gain function.
- the configuration utilizes the A/D converter 43 using a DC voltage measurement instead of the analog amplifier 35 with an AC voltage measurement.
- the crosstalk cancellation circuit and the PGA gain calculator are digital, and the configuration utilizes both the analog amplifier 35 and the A/D converter 43 , as illustrated in FIG. 5 .
- the crosstalk level also increases if the headset is equipped with one common cord to the headphone speakers.
- the common cord is not included in R L1 and R L2 .
- the common cord impedance must then be known in case crosstalk cancellation from that impedance is needed.
- the amount of PGA gain can also be calculated from an internal measurement directly from the Reference AMP output signal by using a multiplexer (MUX) 37 .
- the signal measurement may be a voltage measurement, a current measurement, or a combination of voltage and current.
- R L is known (i.e., crosstalk cancellation with pre-loaded PGA gain);
- a MUX may be utilized to select between external and internal measurements.
- the crosstalk cancellation may be implemented by using adders 38 and 39 , and programmable gain amplifiers PGA 1 40 and PGA 2 41 with negative gain settings in front of the original output amplifiers.
- step A to determine R int 42 , the R int is given by the amplifier design.
- the R int is assumed to be 1 ⁇ .
- the headset cord impedance if the headset is equipped with one common cord, can be found by measurement or from the supplier.
- step B to optimize the crosstalk cancellation for any load, the amplifier load R L (R L1 and R L2 ) must be measured. This requires that the R int and R S (R S1 and R S2 ) be known, and that the input signal level V in be known. The output impedance of R L is then measured as shown in FIG. 5 .
- V measure ⁇ ⁇ 2 V out ⁇ ⁇ 1 ⁇ R L ⁇ ⁇ 2 + R int R L ⁇ ⁇ 2 + R int + R S ⁇ ⁇ 2 ( 14 )
- R S 100 ⁇
- V out 1V
- V measure 0.767V
- step C calculate the PGA setting, when the load resistance is known, the calculation of the right amount of signal added through the PGA to each channel can be calculated as follows:
- G PGA 20 ⁇ ⁇ log ⁇ R int R L ( 15 )
- G PGA 20 ⁇ ⁇ log ⁇ R int
- the PGA gain calculator 36 can then set the correct PGA gain.
- the final scenario considered is when internal crosstalk measurements are taken on the Reference AMP output. This measurement is performed using the MUX 37 to select and measure the V MIDR voltage level. Calculation of PGA gain can be done in the following ways:
- the PGA gain calculator 36 can then set the correct PGA gain.
- digital-to-analog (D/A) converters 20 a and 20 b are implemented prior to Output AMP 1 21 and Output AMP 2 22 , respectively.
- the conversion back to digital is performed by the A/D converter 43 .
- the digital and analog domains may be defined differently by implementing the D/A and A/D converters at different locations in the circuit. For example, instead of performing the crosstalk cancellation in the digital domain, as shown, the variable amplification and summing operations could be performed in the analog domain using, for example, variable and fixed resistors.
- FIG. 6 is a flow chart illustrating the steps of a first embodiment of the method of the present invention.
- a first signal is input to a first output amplifier 21 for the first channel
- a second signal is input to a second output amplifier 22 for the second channel
- an output load 26 and 27 for each output amplifier is connected between each output amplifier and a reference amplifier 24 .
- the first signal is split prior to the input of the first output amplifier.
- the second signal is split prior to the input of the second output amplifier.
- the gain of each split signal is adjusted in gain function ⁇ 28 and gain function ⁇ 30 .
- the adjusted split portions of each signal are added to the other signal in adders 29 and 31 .
- the summed signals are input to the first and second output amplifiers.
- FIG. 7 is a flow chart illustrating the steps of a second embodiment of the method of the present invention.
- a first signal is input to a first output amplifier 21 for the first channel
- a second signal is input to a second output amplifier 22 for the second channel
- an output load 26 and 27 for each output amplifier is connected between each output amplifier and a reference amplifier 24 .
- a first input signal is split into two paths prior to the first output amplifier.
- the first path is input to the first output amplifier.
- the second path is applied to an adder 33 .
- a second input signal is split into two paths prior to the second output amplifier.
- the first path is input to the second output amplifier.
- the second path is applied to the adder.
- the second paths of each signal are added, and at step 58 the gain of the summed second paths is adjusted by the gain function a 34 .
- a suitable DC bias is added to the adjusted sum.
- the biased adjusted sum is input to the reference amplifier 24 connected in parallel with the first and second output amplifiers.
- the crosstalk figure can be improved with crosstalk cancellation.
- the present invention can be implemented in the digital region of an ASIC while using a minimum of silicon area.
- a low cost, low performance analog input amplifier, or an amplifier already existing in the ASIC, can be used as a measuring amplifier.
- the calculation also gives the load resistance figure connected to the output amplifier. This information can be used to send a warning message to the user indicating that the load is not acceptable for the platform.
- the stability of the Reference AMP can indirectly be improved if the Reference AMP stability improves when adding a serial resistance between the Reference AMP and the load.
Abstract
Description
Note that the symbol “μ” in all equations indicates that the resistors, R, on either side of the symbol are connected in parallel.
R A =R B R>>R 0 (3)
where the internal output impedance is assumed to be 1Ω and the load impedance is assumed to be 32Ω. With this result, the
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Priority Applications (7)
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US11/482,595 US7925030B2 (en) | 2006-07-08 | 2006-07-08 | Crosstalk cancellation using load impedence measurements |
JP2009517237A JP5032570B2 (en) | 2006-07-08 | 2007-07-02 | Crosstalk cancellation using load impedance measurement |
MX2009000063A MX2009000063A (en) | 2006-07-08 | 2007-07-02 | Crosstalk cancellation using load impedance measurements. |
EP07765750A EP2039221B1 (en) | 2006-07-08 | 2007-07-02 | Crosstalk cancellation using load impedence measurements |
CN2007800258558A CN101491117B (en) | 2006-07-08 | 2007-07-02 | Crosstalk cancellation using load impedence measurements |
KR1020097002265A KR20090028639A (en) | 2006-07-08 | 2007-07-02 | Crosstalk cancellation using load impedance measurements |
PCT/EP2007/056623 WO2008006724A1 (en) | 2006-07-08 | 2007-07-02 | Crosstalk cancellation using load impedence measurements |
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US11/482,595 US7925030B2 (en) | 2006-07-08 | 2006-07-08 | Crosstalk cancellation using load impedence measurements |
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US7925030B2 true US7925030B2 (en) | 2011-04-12 |
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EP (1) | EP2039221B1 (en) |
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KR (1) | KR20090028639A (en) |
CN (1) | CN101491117B (en) |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110096931A1 (en) * | 2009-10-28 | 2011-04-28 | Sony Ericsson Mobile Communications Ab | Crosstalk suppression |
CN102739176A (en) * | 2011-04-15 | 2012-10-17 | 快捷半导体(苏州)有限公司 | Amplifier crosstalk cancellation method and amplifier circuit |
US20140236589A1 (en) * | 2006-09-14 | 2014-08-21 | Symbol Technologies, Inc. | Mitigating audible cross talk |
US9161133B2 (en) | 2013-06-24 | 2015-10-13 | Sony Corporation | Crosstalk reduction in a headset |
US9380388B2 (en) | 2012-09-28 | 2016-06-28 | Qualcomm Incorporated | Channel crosstalk removal |
US9936317B2 (en) | 2014-10-31 | 2018-04-03 | Fairchild Semiconductor Corporation | Audio crosstalk calibration switch |
US10015578B2 (en) * | 2014-11-19 | 2018-07-03 | Fairchild Semiconductor Corporation | Remote ground sensing for reduced crosstalk of headset and microphone audio signals |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8391506B1 (en) * | 2006-09-14 | 2013-03-05 | Symbol Technologies, Inc. | Mitigating audible cross talk |
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CN113923564A (en) * | 2021-11-19 | 2022-01-11 | 展讯通信(上海)有限公司 | Audio processing device and terminal equipment |
US20230232155A1 (en) * | 2022-01-20 | 2023-07-20 | Qualcomm Incorporated | Audio ground switch channel crosstalk cancellation technique |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4449229A (en) * | 1980-10-24 | 1984-05-15 | Pioneer Electronic Corporation | Signal processing circuit |
US4868878A (en) * | 1984-04-09 | 1989-09-19 | Pioneer Electronic Corporation | Sound field correction system |
US5119420A (en) * | 1989-11-29 | 1992-06-02 | Pioneer Electronic Corporation | Device for correcting a sound field in a narrow space |
US5434921A (en) * | 1994-02-25 | 1995-07-18 | Sony Electronics Inc. | Stereo image control circuit |
US5774556A (en) * | 1993-09-03 | 1998-06-30 | Qsound Labs, Inc. | Stereo enhancement system including sound localization filters |
US5854847A (en) * | 1997-02-06 | 1998-12-29 | Pioneer Electronic Corp. | Speaker system for use in an automobile vehicle |
US6754350B2 (en) * | 2001-03-22 | 2004-06-22 | New Japan Radio Co., Ind. | Surround reproducing circuit |
US6870933B2 (en) * | 2000-07-17 | 2005-03-22 | Koninklijke Philips Electronics N.V. | Stereo audio processing device for deriving auxiliary audio signals, such as direction sensing and center signals |
US20050184807A1 (en) | 2002-01-24 | 2005-08-25 | Tony Doy | Single supply direct drive amplifier |
US20060023889A1 (en) | 2004-07-29 | 2006-02-02 | Masao Suzaki | Method and apparatus for processing sound signal |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3466400A (en) * | 1966-12-30 | 1969-09-09 | Zenith Radio Corp | Combined synchronous demodulator and active matrix |
JPH0422634Y2 (en) * | 1985-06-26 | 1992-05-25 | ||
JP2911131B2 (en) * | 1989-05-08 | 1999-06-23 | 三洋電機株式会社 | Integrated circuit |
JP2609943B2 (en) * | 1990-07-31 | 1997-05-14 | 三洋電機株式会社 | Amplifier circuit |
GB9610394D0 (en) * | 1996-05-17 | 1996-07-24 | Central Research Lab Ltd | Audio reproduction systems |
JP4318841B2 (en) * | 2000-07-14 | 2009-08-26 | ローランド株式会社 | Sound effect device |
JP3659349B2 (en) * | 2002-03-29 | 2005-06-15 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Audio amplifiers and notebook personal computers |
-
2006
- 2006-07-08 US US11/482,595 patent/US7925030B2/en active Active
-
2007
- 2007-07-02 MX MX2009000063A patent/MX2009000063A/en active IP Right Grant
- 2007-07-02 WO PCT/EP2007/056623 patent/WO2008006724A1/en active Application Filing
- 2007-07-02 CN CN2007800258558A patent/CN101491117B/en active Active
- 2007-07-02 EP EP07765750A patent/EP2039221B1/en active Active
- 2007-07-02 JP JP2009517237A patent/JP5032570B2/en not_active Expired - Fee Related
- 2007-07-02 KR KR1020097002265A patent/KR20090028639A/en not_active Application Discontinuation
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4449229A (en) * | 1980-10-24 | 1984-05-15 | Pioneer Electronic Corporation | Signal processing circuit |
US4868878A (en) * | 1984-04-09 | 1989-09-19 | Pioneer Electronic Corporation | Sound field correction system |
US5119420A (en) * | 1989-11-29 | 1992-06-02 | Pioneer Electronic Corporation | Device for correcting a sound field in a narrow space |
US5774556A (en) * | 1993-09-03 | 1998-06-30 | Qsound Labs, Inc. | Stereo enhancement system including sound localization filters |
US5434921A (en) * | 1994-02-25 | 1995-07-18 | Sony Electronics Inc. | Stereo image control circuit |
US5854847A (en) * | 1997-02-06 | 1998-12-29 | Pioneer Electronic Corp. | Speaker system for use in an automobile vehicle |
US6870933B2 (en) * | 2000-07-17 | 2005-03-22 | Koninklijke Philips Electronics N.V. | Stereo audio processing device for deriving auxiliary audio signals, such as direction sensing and center signals |
US6754350B2 (en) * | 2001-03-22 | 2004-06-22 | New Japan Radio Co., Ind. | Surround reproducing circuit |
US20050184807A1 (en) | 2002-01-24 | 2005-08-25 | Tony Doy | Single supply direct drive amplifier |
US20060023889A1 (en) | 2004-07-29 | 2006-02-02 | Masao Suzaki | Method and apparatus for processing sound signal |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140236589A1 (en) * | 2006-09-14 | 2014-08-21 | Symbol Technologies, Inc. | Mitigating audible cross talk |
US9112583B2 (en) * | 2006-09-14 | 2015-08-18 | Symbol Technologies, Llc | Mitigating audible cross talk |
US20110096931A1 (en) * | 2009-10-28 | 2011-04-28 | Sony Ericsson Mobile Communications Ab | Crosstalk suppression |
CN102739176A (en) * | 2011-04-15 | 2012-10-17 | 快捷半导体(苏州)有限公司 | Amplifier crosstalk cancellation method and amplifier circuit |
US20120262230A1 (en) * | 2011-04-15 | 2012-10-18 | Llewellyn William D | Amplifier crosstalk cancellation technique |
US8831230B2 (en) * | 2011-04-15 | 2014-09-09 | Fairchild Semiconductor Corporation | Amplifier crosstalk cancellation technique |
CN102739176B (en) * | 2011-04-15 | 2015-06-10 | 快捷半导体(苏州)有限公司 | Amplifier crosstalk cancellation method and amplifier circuit |
US9380388B2 (en) | 2012-09-28 | 2016-06-28 | Qualcomm Incorporated | Channel crosstalk removal |
US9161133B2 (en) | 2013-06-24 | 2015-10-13 | Sony Corporation | Crosstalk reduction in a headset |
US9936317B2 (en) | 2014-10-31 | 2018-04-03 | Fairchild Semiconductor Corporation | Audio crosstalk calibration switch |
US10015578B2 (en) * | 2014-11-19 | 2018-07-03 | Fairchild Semiconductor Corporation | Remote ground sensing for reduced crosstalk of headset and microphone audio signals |
Also Published As
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JP5032570B2 (en) | 2012-09-26 |
US20080008325A1 (en) | 2008-01-10 |
CN101491117A (en) | 2009-07-22 |
WO2008006724A1 (en) | 2008-01-17 |
MX2009000063A (en) | 2009-01-23 |
KR20090028639A (en) | 2009-03-18 |
EP2039221B1 (en) | 2013-02-20 |
JP2009543388A (en) | 2009-12-03 |
EP2039221A1 (en) | 2009-03-25 |
CN101491117B (en) | 2012-05-30 |
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