US8018067B2 - Electrically shielded through-wafer interconnect - Google Patents
Electrically shielded through-wafer interconnect Download PDFInfo
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- US8018067B2 US8018067B2 US12/063,774 US6377406A US8018067B2 US 8018067 B2 US8018067 B2 US 8018067B2 US 6377406 A US6377406 A US 6377406A US 8018067 B2 US8018067 B2 US 8018067B2
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- wafer interconnect
- interconnect structure
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- metal oxide
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- 238000000034 method Methods 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 22
- 238000002591 computed tomography Methods 0.000 claims description 18
- 230000000295 complement effect Effects 0.000 claims description 17
- 229910044991 metal oxide Inorganic materials 0.000 claims description 17
- 150000004706 metal oxides Chemical class 0.000 claims description 17
- 239000000758 substrate Substances 0.000 abstract description 11
- 230000005855 radiation Effects 0.000 description 12
- 238000001514 detection method Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 6
- 238000003384 imaging method Methods 0.000 description 5
- 238000007689 inspection Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000005670 electromagnetic radiation Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004154 testing of material Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000002600 positron emission tomography Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 238000002059 diagnostic imaging Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 239000000383 hazardous chemical Substances 0.000 description 1
- 238000010339 medical test Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003325 tomography Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
Definitions
- the present invention relates to the field of semiconductor physics.
- the present invention relates to an Electrically Shielded Through-Wafer Interconnect, to a detecting element for application in an examination apparatus, to an examination apparatus, and to a method of fabricating an Electrically Shielded Through-Wafer Interconnect.
- CMOS Complementary Metal Oxide Semiconductors
- vias may be used for transmitting signals from one side of the wafer to the other side.
- CMOS Complementary Metal Oxide Semiconductors
- a chip for example a detector chip for computed tomography application, comprises a number of low-noise high-sensitive inputs/outputs which have to be connected to the external world, the connecting signals are often susceptible to noise disturbances.
- high-frequency inputs/outputs are susceptible to external disturbances and parasitics.
- an Electrically Shielded Through-Wafer Interconnect comprising a wafer, a first through-wafer interconnect structure and a second through-wafer interconnect structure, wherein the second through-wafer interconnect structure is coaxially arranged around the first through-wafer interconnect structure.
- the susceptibility of the first through-wafer interconnect structure with respect to external components and/or internal parts may be reduced by the provision of a shielding structure in form of a second through-wafer interconnect structure in the form of a coaxial connection.
- TWI Trough Wafer Interconnection
- chips especially CMOS chips/CMOS imagers
- interconnections from the CMOS frontside (or other process) to a bump ball on the backside.
- This option avoids connection pads at the side of the chip which prevent an all side placement of these chips directly next to each other (in the same pixel pitch e.g. for imagers) which is very important for large area detectors in computed tomography for example.
- the use of this TWI technology may allow also the 3D-module design of different chips, which makes this technology interesting for all semiconductor applications.
- TWI is to etch trenches of certain geometry from the topside on a raw CMOS wafer. These trenches may be filled with doped polysilicon or any other conducting material.
- the CMOS process is placed on top. Once finished, the TWIs are opened from the back-side by thinning. The last step is back-side metallization and placement of the contacts (i.e. bumps) Other TWI methods may also benefit from the present invention.
- the wafer comprises a Complementary Metal Oxide Semiconductor structure with a first metallic region, wherein the first through-wafer interconnect structure is connected to the first metallic region of the Complementary Metal Oxide Semiconductor structure (CMOS structure).
- CMOS structure Complementary Metal Oxide Semiconductor structure
- the first through-wafer interconnect structure may be adapted for transmitting signals from or to the metallic region of the CMOS through the wafer while being at the same time electrically shielded by the second through-wafer interconnect structure.
- the second through-wafer interconnect structure is connected to a second metallic region of the CMOS structure, wherein the first through-wafer interconnect structure has a first depth and wherein the second through-wafer interconnect structure has a second depth which is smaller than the first depth.
- the second through-wafer interconnect structure may not lead all way through the wafer but may only reach to a certain depth. Consequently, the second through-wafer interconnect structure may be buried inside the wafer, whereas the first through-wafer interconnect structure may reach through the wafer to the back-side of the wafer.
- the second through-wafer interconnect structure is a closed structure.
- the Through-Wafer Interconnect further comprises a third through-wafer interconnect structure coaxially arranged around the first through-wafer interconnect structure, wherein one of the second through-wafer interconnect structure and the third through-wafer interconnect structure is connected to a first potential, which may be a ground potential.
- the other one of the second through-wafer interconnect structure and the third through-wafer interconnect structure is connected to a second potential.
- a triaxial structure based on TWIs may be provided, in which the middle ring maybe work as a guard-ring and may be connected to a specific potential. The outer ring may then be connected to ground, or vice versa. This may provide for a shielded transmission of sensible signals to the external world.
- the Through-Wafer Interconnect may further comprise a bump or a re-routing layer for connecting the second through-wafer interconnect structure to the first potential.
- a detecting element for application in an examination apparatus comprising a wafer with a sensitive region adapted for detecting radiation or energetic particles, the detected radiation or particles resulting in a detection signal, and a first through-wafer interconnect structure adapted for transmitting the detection signal from the sensitive region through the wafer to a first interface, and a second through-wafer interconnect structure adapted for shielding the detection signal during transmission of the detection signal through the wafer.
- the second through-wafer interconnect structure is coaxially arranged around the first through-wafer interconnect structure.
- the susceptibility of the inner interconnection to external components and/or internal parts may be reduced by providing a shielding structure in the form of a coaxial outer through-wafer interconnect structure.
- the detecting element is part of a large-area tile detector.
- an examination apparatus for examination of an object of interest having a detecting element comprising a wafer, a first through-wafer interconnect structure and a second through-wafer interconnect structure according to the above described detecting element.
- the examination apparatus may be applied as a baggage inspection apparatus, a medical application apparatus, a material testing apparatus or a material science analysis apparatus.
- a field of application of the invention may be baggage inspection.
- the examination apparatus may be selected from the group consisting of Computed Tomography (CT) imaging system, Coherent Scatter Computed Tomography (CSCT) imaging system, Positron Emission Tomography (PET) imaging system, and Single Photon Emission Computerized Tomography (SPECT) imaging system. Therefore, diagnostic tools for different diagnosis may be provided.
- CT Computed Tomography
- CSCT Coherent Scatter Computed Tomography
- PET Positron Emission Tomography
- SPECT Single Photon Emission Computerized Tomography
- a method of fabricating an electrically shielded Through-Wafer Interconnect comprising the steps of providing a wafer, fabricating a first through-wafer interconnect structure and fabricating a second through-wafer interconnect structure, wherein the second through-wafer interconnect structure is coaxially arranged around the first through-wafer interconnect structure.
- the susceptibility of interconnections through a wafer may be reduced by providing a shielding structure in the form of a coaxial, triaxial or other multi-axial connection.
- a shielding structure in the form of a coaxial, triaxial or other multi-axial connection.
- This may provide for an improved signal transmission of, for example, high precision analogue signals or high-frequency signals, both analogue and digital.
- the shielding geometry may suppress leakage currents, as there are several “isolation-borders” between the signal and the substrate.
- FIG. 1 shows a simplified schematic representation of an embodiment of a CT scanner according to the present invention.
- FIG. 2 shows a basic TWI structure
- FIG. 3 shows a coaxial structure based on TWI according to an exemplary embodiment of the present invention.
- FIG. 4 shows a coaxial structure based on TWI with an outer ring connected at the CMOS process side according to an exemplary embodiment of the present invention.
- FIG. 5 shows a coaxial structure based on TWI with an outer ring connected at the CMOS process side and limited in depth according to an exemplary embodiment of the present invention.
- FIG. 6 shows a triaxial structure based on TWIs according to an exemplary embodiment of the present invention.
- FIG. 1 shows an exemplary embodiment of a CT scanner system according to an exemplary embodiment of the present invention.
- the present invention will be described for the application in baggage inspection to detect hazardous materials, such as explosives, in items of baggage.
- the present invention is not limited to this application, but may also be applied in the field of medical imaging, or other industrial applications, such as material testing.
- the computer tomography apparatus 100 depicted in FIG. 1 is a cone-beam CT scanner. However, the invention may also be carried out a with a fan-beam geometry or with other scanning systems, such as CSCT, PET, SPEC or MR imaging systems.
- the CT scanner depicted in FIG. 1 comprises a gantry 101 , which is rotatable around a rotational axis 102 .
- the gantry 101 is driven by means of a motor 103 .
- Reference numeral 104 designates a source of radiation such as an X-ray source, which, according to an aspect of the present invention, emits a polychromatic radiation.
- Reference numeral 105 designates an aperture system which forms the radiation beam emitted from the radiation source to a cone-shaped radiation beam 106 .
- the cone-beam 106 is directed such that it penetrates an object of interest 107 arranged in the centre of the gantry 101 , i.e. in an examination region of the CT scanner, and impinges onto the detector 108 .
- the detector 108 is arranged on the gantry 101 opposite to the source of radiation 104 , such that the surface of the detector 108 is covered by the cone-beam 106 .
- the detector 108 which is depicted in FIG.
- the first through-wafer interconnect structure adapted for transmitting the detection signal from the sensitive region through the wafer to a first interface
- a second through-wafer interconnect structure adapted for shielding the detection signal during transmission of the detection signal through the wafer.
- the second through-wafer interconnect structure is coaxially arranged around the first through-wafer interconnect structure.
- the source of radiation 104 , the aperture system 105 and the detector 108 are rotated along the gantry 101 in the direction indicated by arrow 116 .
- the motor 103 is connected to a motor control unit 117 , which is connected to a calculation or determination unit 118 .
- the object of interest 107 is an item of baggage [or a patient] which is disposed on a conveyor belt 119 .
- the conveyor belt 119 displaces the object of interest 107 along a direction parallel to the rotational axis 102 of the gantry 101 .
- the conveyor belt 119 may also be stopped during the scans to thereby measure single slices.
- a movable table may be used instead of providing a conveyor belt 119 , for example, in medical applications where the object of interest 107 is a patient.
- the invention may be realized by a fan-beam configuration.
- the aperture system 105 may be configured as a slit collimator.
- the detector 108 may be connected to the determination unit 118 .
- the determination unit 118 may receive the detection result, i.e. the read-outs from the detector elements 123 of the detector 108 and may determine a scanning result on the basis of the read-outs. Furthermore, the determination unit 118 communicates with the motor control unit 117 in order to coordinate the movement of the gantry 101 with motors 103 and 120 with the conveyor belt 119 .
- the determination 118 may be adapted for constructing an image from read-outs of the detector 108 .
- a reconstructed image generated by the calculation unit 118 may be output to a display (not shown in FIG. 1 ) via an interface 122 .
- the determination unit 118 may be realized by a data processor to process read-outs from the detector elements 123 of the detector 108 .
- the determination unit 118 may be connected to a loudspeaker 121 , for example, to automatically output an alarm in case of the detection of suspicious material in the item of baggage 107 .
- the computer tomography apparatus 100 comprises the X-ray source 104 adapted to emit X-rays to the object of interest 107 .
- the collimator 105 provided between the electromagnetic radiation source 104 and the detecting elements 123 is adapted to collimate an electromagnetic radiation beam emitted from the electromagnetic radiation source 104 to form a cone-beam.
- a slit collimator may be used instead of collimator 105 to produce a fan-beam.
- the detecting elements 123 form a multi-slice detector array 108 .
- the computer tomography apparatus 100 is configured as a baggage inspection apparatus.
- the detector 108 may be adapted as a large-area tile detector having a plurality of detecting elements 123 .
- the detector chips 123 may be tiled in different directions.
- through-wafer interconnections may be used for transmitting signals from a sensitive region of a detecting element to the back side of the wafer.
- Both inputs and outputs of the TWI may, according to an exemplary embodiment of the present invention, be shielded against external disturbances by using coaxial or triaxial structures implemented in TWI technology. This process may be applied for a large number of semiconductor applications, not only medical or material testing systems.
- FIG. 2 shows a basic TWI structure of a chip 200 , which may be applied as a detector for computed tomography application.
- a low-noise input/output 204 has to be connected to the external world.
- Connecting signals, which are very susceptible to noise disturbances, to external components is a delicate matter.
- Connecting the signals from the metallic region 204 of the CMOS structure 202 to the external world may be performed by vias 203 or through-wafer interconnections 203 , which may be adapted in form of polysilicone TWIs.
- the TWIs 203 penetrate the substrate 201 and are connected to a bump 205 on the back side of the wafer, hence allowing to tile a number of detector elements for large area detectors.
- the front-side pre-processed TWI is contacted to the front-side metal 204 (of any layer) during the CMOS front-side process. Then, the waver is thinned from the back-side such that the TWI is left open. Then, a back-side process and bump placement 205 enable to contact the chip to any substrate (or other interfaces).
- cross-sectional shape of such a TWI seen from top or bottom, may be circular, rectangular, or of any other shape. It may even have the shape of an open structure, such as a semi-circle.
- the contacting material may be on the trenches and not between trenches as conductor. This may provide with a good electrical contact since additional conducting material is used and not the substrate.
- the TWIs 203 may be shielded according to an exemplary embodiment of the present invention.
- This shielding may be performed by an implementation of integrated coaxial, triaxial or multi-axial structures at the input and output nodes. This may improve the shielding capabilities against external disturbances and also may ensure a much lower leakage (or better leakage path). Furthermore, inter-chip disturbances among the different inputs and outputs may be prevented.
- the coaxial and triaxial structures may also prevent a specific output/input to disturb any other parts of the chip since no leakage will reach the substrate.
- the coaxial structure 203 , 206 depicted in FIG. 3 is based on TWI.
- the through-wire interconnect structure 203 of FIG. 2 is surrounded by a second through-wire interconnect structure 206 .
- This outer structure 206 may be connected to any fixed potential (ground or supply), as depicted by ground potential 208 , or to any other signal.
- the outer ring 206 may prevent any disturbance to neighbouring TWIs/chip-nodes. It may also prevent that any disturbance from other TWIs/chip-nodes may affect the inner structure 203 .
- the outer ring may be adapted in form of a closed structure surrounding completely the inner TWI.
- the back-side of the outer ring 209 may be contacted by placing an additional bump (such as bump 205 , but not depicted in the figure) or by having a re-routing layer in the back-side (which is not depicted in the figure).
- FIG. 4 Another implementation according to another exemplary embodiment of the present invention is shown in FIG. 4 , in which the outer ring 206 is electrically connected at the CMOS process side. Instead of contacting the outer ring 206 from the back-side, the CMOS process is used to provide the contact of a fixed potential 208 to the outer ring 206 .
- the second through-wafer interconnect structure 206 is connected to a second metallic region 207 of the CMOS structure 202 . It should be noted, that the first metallic region and the second metallic region may be located in the same metallic layer or in different metallic layers.
- FIG. 5 This exemplary embodiment is depicted in FIG. 5 , in which the outer ring 206 is connected at the CMOS process side and limited in depth. In other words, the outer ring 206 is buried in the substrate 201 .
- the fabrication of such a structure may be easy to control, since the depth of the TWI also depends on its width. Therefore, by reducing the width of the outer interconnect 206 with respect to inner interconnect 203 , the outer TWI 206 may not reach the depth of the inner TWI 203 .
- FIG. 6 shows the implementation of a triaxial structure according to an exemplary embodiment of the present invention.
- the triaxial structure comprises an inner TWI 203 , a middle TWI 206 and an outer TWI 210 .
- the outer TWI 210 runs all the way through the substrate 201 and is connected to ground potential 208 .
- the middle TWI 206 does not reach the back-side of the substrate 209 and may be connected to a potential in the way of TWI 206 depicted in FIG. 5 .
- the middle TWI ring 206 may be connected to a specific potential to work as a guard-ring and the outer TWI ring 210 may be connected to ground 208 , or vice versa. This may provide for a maximum shielding.
- the present invention is applied in the field of computed tomography, especially as a large-area tile detector, it may also be used for different applications in the field of baggage examination or semiconductor processing and semiconductor applications.
Abstract
Description
Claims (15)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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EP05107848 | 2005-08-26 | ||
EP05107848.3 | 2005-08-26 | ||
EP05107848 | 2005-08-26 | ||
PCT/IB2006/052809 WO2007023416A1 (en) | 2005-08-26 | 2006-08-15 | Electrically shielded through-wafer interconnect |
Publications (2)
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US20100171196A1 US20100171196A1 (en) | 2010-07-08 |
US8018067B2 true US8018067B2 (en) | 2011-09-13 |
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US12/063,774 Expired - Fee Related US8018067B2 (en) | 2005-08-26 | 2006-08-15 | Electrically shielded through-wafer interconnect |
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EP (1) | EP1922756B1 (en) |
JP (1) | JP5357543B2 (en) |
CN (1) | CN100559574C (en) |
WO (1) | WO2007023416A1 (en) |
Cited By (1)
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US9526468B2 (en) | 2014-09-09 | 2016-12-27 | General Electric Company | Multiple frame acquisition for exposure control in X-ray medical imagers |
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ATE538496T1 (en) * | 2006-03-27 | 2012-01-15 | Koninkl Philips Electronics Nv | PRODUCTION METHOD FOR A LOW-RESISTANCE SUBSTRATE CONNECTION FOR SEMICONDUCTOR CARRIER |
GB2449853B (en) | 2007-06-04 | 2012-02-08 | Detection Technology Oy | Photodetector for imaging system |
WO2009136342A1 (en) * | 2008-05-08 | 2009-11-12 | Koninklijke Philips Electronics N.V. | A microelectronic device with wafer trenches |
JP2010219425A (en) * | 2009-03-18 | 2010-09-30 | Toshiba Corp | Semiconductor device |
JP2012164702A (en) * | 2011-02-03 | 2012-08-30 | Elpida Memory Inc | Semiconductor device |
JP5842368B2 (en) * | 2011-04-11 | 2016-01-13 | ソニー株式会社 | Semiconductor device |
JP2012019228A (en) * | 2011-09-05 | 2012-01-26 | Toshiba Corp | Semiconductor device |
US9013615B2 (en) * | 2011-09-21 | 2015-04-21 | Semiconductor Components Industries, Llc | Image sensor with flexible interconnect capabilities |
JP6108671B2 (en) * | 2012-03-13 | 2017-04-05 | キヤノン株式会社 | Radiography equipment |
US20150187701A1 (en) | 2013-03-12 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Devices and Methods of Manufacture Thereof |
US9076715B2 (en) | 2013-03-12 | 2015-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for connecting dies and methods of forming the same |
US10056353B2 (en) | 2013-12-19 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US9412719B2 (en) | 2013-12-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US9425150B2 (en) | 2014-02-13 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-via interconnect structure and method of manufacture |
US9543257B2 (en) | 2014-05-29 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect devices and methods of forming same |
US9455158B2 (en) | 2014-05-30 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect devices and methods of forming same |
US9449914B2 (en) | 2014-07-17 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuits with redistribution lines |
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2006
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- 2006-08-15 US US12/063,774 patent/US8018067B2/en not_active Expired - Fee Related
- 2006-08-15 WO PCT/IB2006/052809 patent/WO2007023416A1/en active Application Filing
- 2006-08-15 CN CN200680031273.6A patent/CN100559574C/en active Active
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EP1922756A1 (en) | 2008-05-21 |
CN101253624A (en) | 2008-08-27 |
US20100171196A1 (en) | 2010-07-08 |
WO2007023416A1 (en) | 2007-03-01 |
JP5357543B2 (en) | 2013-12-04 |
EP1922756B1 (en) | 2013-05-22 |
CN100559574C (en) | 2009-11-11 |
JP2009506528A (en) | 2009-02-12 |
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