US8045353B2 - Integrated circuit capable of operating at different supply voltages - Google Patents
Integrated circuit capable of operating at different supply voltages Download PDFInfo
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- US8045353B2 US8045353B2 US11/645,815 US64581506A US8045353B2 US 8045353 B2 US8045353 B2 US 8045353B2 US 64581506 A US64581506 A US 64581506A US 8045353 B2 US8045353 B2 US 8045353B2
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- 238000000034 method Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 3
- 238000010168 coupling process Methods 0.000 claims 3
- 238000005859 coupling reaction Methods 0.000 claims 3
- 230000009977 dual effect Effects 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the instant invention relates to Integrated circuit capable of operating at different supply voltages.
- An on-chip voltage regulator is often the solution to incompatibility with board voltage.
- a regulator is used to step down the external board supply to the required chip operating voltage.
- the on-chip voltage regulators have a dropout voltage equal to the difference between the external board supply and chip operating voltage. This helps address the board supply compatibility issue for the core operating voltages.
- the regulator is operated in bypass mode, wherein all the current is passed through a fully-on NMOS/PMOS.
- This approach has an inherent problem of voltage drop across the switch, which may be unacceptable in high current consuming cores operating at low voltage levels around 1V. To avoid this, a new chip without the regulator is required to be fabricated which is very costly.
- FIG. 1 illustrates the ballast transistor ( 11 ) implementation in one I/O pad ( 10 ).
- Vg ( 14 ) is the gate control voltage coming from a control block.
- One terminal ( 15 ) of the PMOS ballast ( 11 ) is connected to the 1.8V pad ( 12 ) and other terminal to the 1.2V pad ( 13 ).
- Another object of this invention is to make a single fabricated chip for dual board voltages without the problem of IR drop in pass transistor.
- Still another object of the invention is to make testing of the core possible in case of incorrect load regulation of regulator or when regulator gives incorrect voltage.
- a digital integrated circuit having selectable supply voltage compatibility comprising:
- the arrangement being such that when one of said specific high-voltage supply input pads is connected to the input supply with all other supply input pads being left unconnected, then the corresponding ballast device is enabled and provides a supply voltage reduced to the corelogic operating voltage level to the core logic, while when the input supply is connected to said low-voltage supply input pad and all said specific high-voltage supply input pads are left unconnected then all said ballast devices are disabled and the input supply voltage is directly fed to the core logic supply bus.
- the present invention provides a method for providing a selectable supply voltage capability to an integrated circuit, comprising the steps of:
- FIG. 1 shows the ballast transistor implementation in one I/O pad.
- FIG. 2 shows the chip I/O ring implementation method.
- FIG. 3 shows the bonding diagram when 1.8V is available on board.
- FIG. 4 shows the bonding diagram when 1.2V is available on board.
- FIG. 2 illustrates the chip I/O ring implementation method.
- a control block ( 211 ) is used to step down form 1.8V to 1.2V core operating voltage.
- 8 ballast I/Os ( 212 , 213 , 214 , 215 , 216 , 217 , 218 , 219 ) are also shown.
- a VDDCO pad ( 220 ) is also inserted in the I/O ring.
- the VDDCO pad ( 220 ) core side pin ( 222 ) is connected to the enable input ( 221 ) of the control block ( 211 ).
- the control block ( 211 ) is so designed such that when enable ( 221 ) is low, the control block ( 211 ) is switched off and the ballast transistor gate control voltage Vg ( 223 ) is pulled high so that the ballast transistor is switched-off.
- the enable pin ( 221 ) is pulled high the control block ( 211 ) is activated and the voltage Vg ( 223 ) controls the load voltage and current.
- a weak pull down ( 224 ) is placed at enable signal ( 221 ) coming from VDDCO pad ( 220 ) to ensure that signal is low when VDDCO signal ( 222 ) is floating.
- FIG. 3 shows the bonding for the chip when 1.8V is available on board. All 1.8V pads ( 311 , 312 , 313 , 314 , 315 , 316 , 317 , 318 ) are connected to the package pins and the VDDCO pad ( 319 , 320 ) is double bonded with one 1.8V package pin. This ensures that the enable pin ( 320 , 221 ) is high and the regulator ( 321 , 211 ) is in operation providing 1.2V regulated supply to the core.
- FIG. 4 illustrates the bonding diagram when 1.2V is available on board. All 1.2V pads ( 411 , 412 , 413 , 414 , 415 , 416 , 417 , 418 ) are bonded to the package pins and VDDCO pad ( 419 , 319 , 220 ) is left unbonded.
- the weak pulldown ( 420 , 224 ) ensures that the enable pin ( 421 , 320 , 221 ) is not floating and is pulled down to ground. This makes the regulator ( 422 , 321 , 211 ) inoperational and gate voltage Vg ( 423 ) is pulled up.
- Now 1.2V pads ( 411 , 412 , 413 , 414 , 415 , 416 , 417 , 418 ) directly get supply from the board through package pins without suffering any IR drop.
- a chip implemented using the abovementioned I/O ring and packaging scheme has following advantages:
- the chip can support dual board voltage 1.8V for older generation boards and 1.2V for new generation.
- the abovementioned can also be of use while doing the wafer level testing. If due to some reason the regulator is unable to give correct voltage or its load regulation is not good enough, the core can be still be tested by applying 1.2V supply at 1.2V pads through probe needles. Otherwise the chip would be non-testable.
Abstract
A chip configuration for dual board voltage compatibility comprising ballast I/O pads, regulator control block and VDDCO pad. If 1.8V is available on board, all 1.8V pads are connected to the package pins and the VDDCO pad is double bonded with one 1.8V package pin. This ensures that the regulator is in operation providing 1.2V supply to the core. If 1.2V is available on board, all 1.2V pads are bonded to the package pins and VDDCO pad is left unbonded. A weak pulldown ensures that the regulator is inoperational and the gate voltage of ballast transistor is pulled up. Now 1.2V pads directly get supply from the board through package pins and is provided to the core without suffering IR drop.
Description
1. Field of the Invention
The instant invention relates to Integrated circuit capable of operating at different supply voltages.
2. Discussion of the Related Art
The trend in chip design is towards shrinking geometries. As part of this trend the gate length of a MOSFET, which is the distance between the source and the drain regions underneath the gate region, is also reducing. These shrinking digital CMOS gate lengths, necessitate corresponding reduction in the operating voltages. This change calls for lowering of board supply voltages in order to prevent punchthrough, breakdown and hot-carrier related problems. However, board supply voltages cannot be reduced easily owing to interfaces to external devices.
An on-chip voltage regulator is often the solution to incompatibility with board voltage. In this approach a regulator is used to step down the external board supply to the required chip operating voltage. The on-chip voltage regulators have a dropout voltage equal to the difference between the external board supply and chip operating voltage. This helps address the board supply compatibility issue for the core operating voltages. When the lower board voltages are made available in newer board design the regulator is operated in bypass mode, wherein all the current is passed through a fully-on NMOS/PMOS. This approach has an inherent problem of voltage drop across the switch, which may be unacceptable in high current consuming cores operating at low voltage levels around 1V. To avoid this, a new chip without the regulator is required to be fabricated which is very costly.
It is an object of the invention to obviate the above drawbacks and make a single fabricated chip operate in older boards as well as new boards without change in board configuration.
It is also an object of this invention to make a single fabricated chip operate in older boards as well as new boards without the need to re-fabricate chip.
Another object of this invention is to make a single fabricated chip for dual board voltages without the problem of IR drop in pass transistor.
Still another object of the invention is to make testing of the core possible in case of incorrect load regulation of regulator or when regulator gives incorrect voltage.
To achieve the above objects the invention provides a digital integrated circuit having selectable supply voltage compatibility comprising:
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- core logic,
- a core logic supply voltage bus connected to said core logic,
- a low-voltage supply input pad connected to said core logic supply voltage bus,
- one or more digitally switch able ballast devices having an input end connected to a specific high-voltage supply input pad and its output end connected to said core logic supply voltage bus,
- a control block associated with each said ballast device, having a control input connected to said specific high-voltage supply input pad and its output connected to the control input of the corresponding ballast device,
the arrangement being such that when one of said specific high-voltage supply input pads is connected to the input supply with all other supply input pads being left unconnected, then the corresponding ballast device is enabled and provides a supply voltage reduced to the corelogic operating voltage level to the core logic, while when the input supply is connected to said low-voltage supply input pad and all said specific high-voltage supply input pads are left unconnected then all said ballast devices are disabled and the input supply voltage is directly fed to the core logic supply bus.
Further the present invention provides a method for providing a selectable supply voltage capability to an integrated circuit, comprising the steps of:
-
- providing a low-voltage supply input pad directly connected to the internal core logic supply bus,
- providing one or more digitally-switchable ballast devices having an input connected to a specific high-voltage supply input pad and an output connected to the core logic supply,
- providing a control unit associated with each said ballast device having its control input connected to said specific high-voltage supply input pad and its output connected to the control input of said digitally-switched ballast device, and
- connecting the input supply to either a selected one of said specific high-voltage supply input pads when the input supply is higher than the core logic supply voltage or alternatively, feeding the input supply to said low-voltage supply input pad when the input supply is equal to the core logic supply voltage.
An embodiment of the present invention is described with the help of following drawings.
A chip implemented using the abovementioned I/O ring and packaging scheme has following advantages:
1. Full compatibility with existing board designs.
2. The chip can support dual board voltage 1.8V for older generation boards and 1.2V for new generation.
3. Cost of redesign and re-fabrication saved when board voltages are reduced.
4. Ability to support two different customers with different board voltages for same application.
5. No IR drop in pass transistor.
6. The abovementioned can also be of use while doing the wafer level testing. If due to some reason the regulator is unable to give correct voltage or its load regulation is not good enough, the core can be still be tested by applying 1.2V supply at 1.2V pads through probe needles. Otherwise the chip would be non-testable.
The present invention is not intended to be restricted to any particular form or arrangement, or any specific embodiment, or any specific use, disclosed herein, and may be modified in various particulars or relations without departing from the spirit or scope of the claimed invention hereinabove shown and described above. The apparatus or methods shown are intended only for illustration and disclosure of an operative embodiment and not to show all of the various forms or modifications in which this invention might be embodied or operated.
Claims (19)
1. A digital integrated circuit having selectable supply voltage compatibility comprising:
core logic,
a core logic supply voltage bus connected to said core logic,
a low-voltage supply input pad connected to said core logic supply voltage bus,
one or more digitally switch able ballast devices having an input end connected to a specific high-voltage supply input pad and its output end connected to said core logic supply voltage bus,
a control block associated with each said ballast device, having a control input connected to said specific high-voltage supply input pad and its output connected to the control input of the corresponding ballast device,
the arrangement being such that when one of said specific high-voltage supply input pads is connected to the input supply with all other supply input pads being left unconnected, then the corresponding ballast device is enabled and provides a supply voltage reduced to the corelogic operating voltage level to the core logic, while when the input supply is connected to said low-voltage supply input pad and all said specific high-voltage supply input pads are left unconnected then all said ballast devices are disabled and the input supply voltage is directly fed to the core logic supply bus.
2. A digital integrated circuit having selectable supply voltage compatibility as claimed in claim 1 , wherein said a weak pullup/pulldown is provided at the control terminal of said control block such that it disables the corresponding ballast devices when said high-voltage supply input pad is left unconnected.
3. A method for providing a selectable supply voltage capability to an integrated circuit, comprising the steps of:
providing a low-voltage supply input pad directly connected to the internal core logic supply bus,
providing one or more digitally-switchable ballast devices having an input connected to a specific high-voltage supply input pad and an output connected to the core logic supply,
providing a control unit associated with each said ballast device having its control input connected to said specific high-voltage supply input pad and its output connected to the control input of said digitally-switched ballast device, and
connecting the input supply to either a selected one of said specific high-voltage supply input pads when the input supply is higher than the core logic supply voltage or alternatively, feeding the input supply to said low-voltage supply input pad when the input supply is equal to the core logic supply voltage.
4. A circuit comprising:
a supply terminal;
at least one first power terminal;
at least one second power terminal;
at least one voltage regulator;
at least one power bus, each of the at least one power bus being coupled to the at least one first power terminal via the at least one voltage regulator and being coupled to the at least one second power terminal; and
a control circuit arranged to detect, when the circuit is provided power, whether a power supply signal is applied to the supply terminal, to enable the at least one voltage regulator when the power supply signal is applied to the supply terminal, and to disable the at least one voltage regulator when the power supply signal is not applied to the supply terminal.
5. The circuit of claim 4 , further comprising logic circuitry powered by power supplied via the at least one first power terminal or the at least one second power terminal.
6. The circuit of claim 4 , wherein the control circuit comprises an enable signal input coupled to the supply terminal and coupled to a pull-down circuit, the enable signal input receiving one of the power supply signal or a ground signal based on whether the power supply signal is applied to the supply terminal, and
wherein the control circuit enables the at least one voltage regulator if the power supply signal is applied to the enable signal input and disables the at least one voltage regulator if the ground signal is applied to the enable signal input.
7. The circuit of claim 4 , wherein each of the at least one power bus is connected to one of the at least one voltage regulator and one of the at least one second power terminal.
8. The circuit of claim 4 , wherein the at least one power bus is a single power bus connected to each of the at least one voltage regulator and each of the at least one second power terminal.
9. The circuit of claim 4 , further comprising a control bus coupled to an output of the control signal and coupled to each of the at least one voltage regulator.
10. The circuit of claim 4 , wherein the at least one voltage regulator comprises a ballast transistor.
11. The circuit of claim 4 , wherein the supply terminal and the at least one first power terminal are coupled to a source of a 1.8V power supply signal, and the at least one voltage regulator supplies a 1.2V power supply signal to the at least one power bus.
12. The circuit of claim 4 , wherein the at least one second power terminal is coupled to a source of a 1.2V power supply signal.
13. The circuit of claim 6 , wherein the pull-down circuit comprises a transistor.
14. A method of operating a control circuit to supply power to circuitry, the method comprising:
while power is being applied to the control circuit:
determining whether a first power supply signal is applied to a supply terminal; and
operating the control circuit to, based on a result of the determining:
when the first power supply signal is applied to the supply terminal, enable at least one voltage regulator to supply a lower-voltage form of the first power supply signal to the circuitry; and
when the first power supply signal is not applied to the supply terminal, disable the at least one voltage regulator.
15. The method of claim 14 , further comprising:
when the first power supply signal is not applied to the supply terminal, allowing a second power supply signal to be supplied to the circuitry.
16. The method of claim 14 , wherein determining whether the first power supply signal is applied to the supply terminal comprises detecting whether the first power supply or a ground signal is applied to an enable signal input of the control circuit.
17. A method of manufacturing an integrated circuit having two possible power supply inputs, the method comprising:
forming the integrated circuit with a supply terminal for the integrated circuit;
forming the integrated circuit with at least one first power supply terminal;
forming the integrated circuit with at least one second power supply terminal;
forming the integrated circuit with at least one voltage regulator;
forming the integrated circuit with at least one power bus;
coupling the at least one first power supply terminal to the at least one power bus via the at least one voltage regulator and coupling the at least one second power supply signal to the at least one power bus; and
forming the integrated circuit with at least one control circuit having a control signal output coupled to the at least one voltage regulator and having an enable signal input coupled to the supply terminal, the at least one control circuit being arranged to detect, when the integrated circuit is provided power, whether a power supply signal is applied to the supply terminal, to enable the at least one voltage regulator when the power supply signal is applied to the supply terminal, and to disable the at least one voltage regulator when the power supply signal is not applied to the supply terminal.
18. The method of claim 17 , further comprising:
forming the integrated circuit with a pull-down circuit; and
coupling the pull-down circuit to the enable signal input coupled to the supply terminal.
19. The method of claim 17 , wherein forming the integrated circuit with the at least one control circuit comprises forming the integrated circuit with a control circuit adapted to enable the at least one voltage regulator when the enable signal input indicates that a power supply signal is applied to the supply terminal and disable the at least one voltage regulator when the enable signal input does not indicate that the power supply signal is applied to the supply terminal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IN3535/DEL/2005 | 2005-12-30 | ||
| IN3535DE2005 | 2005-12-30 |
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| Publication Number | Publication Date |
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| US20070170451A1 US20070170451A1 (en) | 2007-07-26 |
| US8045353B2 true US8045353B2 (en) | 2011-10-25 |
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| US11/645,815 Expired - Fee Related US8045353B2 (en) | 2005-12-30 | 2006-12-26 | Integrated circuit capable of operating at different supply voltages |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20130127512A1 (en) * | 2010-05-28 | 2013-05-23 | Sharad Murari | Multi-level chip input |
| US20130193590A1 (en) * | 2012-01-31 | 2013-08-01 | Elpida Memory, Inc. | Semiconductor device including voltage converter circuit, and method of making the semiconductor device |
| US9000808B2 (en) | 2010-05-28 | 2015-04-07 | Nxp B.V. | Input pin state detection circuit and method therefor |
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| US8347251B2 (en) * | 2007-12-31 | 2013-01-01 | Sandisk Corporation | Integrated circuit and manufacturing process facilitating selective configuration for electromagnetic compatibility |
| US7724023B1 (en) | 2009-05-11 | 2010-05-25 | Agere Systems Inc. | Circuit apparatus including removable bond pad extension |
| US9128771B1 (en) * | 2009-12-08 | 2015-09-08 | Broadcom Corporation | System, method, and computer program product to distribute workload |
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| US7568177B1 (en) * | 2005-10-31 | 2009-07-28 | Cadence Design Systems, Inc. | System and method for power gating of an integrated circuit |
| US7411853B2 (en) * | 2005-11-17 | 2008-08-12 | Altera Corporation | Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits |
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| US20130127512A1 (en) * | 2010-05-28 | 2013-05-23 | Sharad Murari | Multi-level chip input |
| US8674726B2 (en) * | 2010-05-28 | 2014-03-18 | Nxp B.V. | Multi-level chip input circuit |
| US9000808B2 (en) | 2010-05-28 | 2015-04-07 | Nxp B.V. | Input pin state detection circuit and method therefor |
| US9667253B2 (en) | 2010-05-28 | 2017-05-30 | Nxp B.V. | Input pin state detection circuit and method therefor |
| US20130193590A1 (en) * | 2012-01-31 | 2013-08-01 | Elpida Memory, Inc. | Semiconductor device including voltage converter circuit, and method of making the semiconductor device |
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| US20070170451A1 (en) | 2007-07-26 |
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