US8194887B2 - System and method for dynamic bass frequency control in association with a dynamic low frequency control circuit having compression control - Google Patents
System and method for dynamic bass frequency control in association with a dynamic low frequency control circuit having compression control Download PDFInfo
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- US8194887B2 US8194887B2 US12/342,754 US34275408A US8194887B2 US 8194887 B2 US8194887 B2 US 8194887B2 US 34275408 A US34275408 A US 34275408A US 8194887 B2 US8194887 B2 US 8194887B2
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- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G9/00—Combinations of two or more types of control, e.g. gain control and tone control
- H03G9/02—Combinations of two or more types of control, e.g. gain control and tone control in untuned amplifiers
- H03G9/025—Combinations of two or more types of control, e.g. gain control and tone control in untuned amplifiers frequency-dependent volume compression or expansion, e.g. multiple-band systems
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- the present invention relates to a system and method for dynamic bass frequency control.
- Fletcher-Munson curves are indicative of the natural inclination of an average person to perceive constant loudness when presented with pure steady tones at various audible frequencies. Based on the curves, an average user would perceive a low frequency note having the same signal strength as a note in high frequency to be softer than the latter. As such, in order to compensate for this irregularity in human hearing within the audible range, it is necessary to boost the output signal in the low frequency region.
- a system for dynamic bass frequency control comprising: a bandwidth filter coupled to a plurality of switchable electronic components for filtering a frequency range of an input signal; an amplifier coupled to the bandwidth filter and the plurality of switchable electronic components, the amplifier being configured for adjusting amplitude of the filtered frequency range of the input signal based on a configuration of the plurality of switchable electronic components; and a signal level detector coupled to the switchable electronic components for determining signal strength of the input signal, the signal level detector being configured to switch the plurality of switchable electronic components between more than one configuration based on the signal strength of the input signal, each configuration determining the frequency range of the input signal to be filtered by the bandwidth filter and the amplitude adjustment to be made to the filtered frequency range of the input signal by the amplifier.
- the system may further comprise a zero crossing detector coupled to the signal level detector for determining zero crossing points in the input signal and generating a zero crossing signal upon determining a zero crossing point, the signal level detector being configured to send a switching signal to switch the switchable electronic components between the more than one configuration based on the zero crossing signal.
- the system may further comprise a buffer device coupled to the zero crossing detector and the signal level detector, the buffer device being configured to store the switching signal and forward the stored switching signal to the switchable electronic components to switch the switchable electronic components between the more than one configuration upon receiving the zero crossing signal from the zero crossing detector.
- the amplifier may be part of the bandwidth filter.
- the plurality of switchable electronic components may comprise two or more separate capacitor banks.
- the banks may comprise switches for connecting up one or more capacitors to form a configuration.
- At least one of the capacitor banks may have a fixed capacitance value and the capacitance value of at least one of the capacitor banks can be varied.
- the signal level detector may determine that the input signal strength is above a threshold level.
- the plurality of switchable electronic components may be switched to a configuration that configures the bandwidth filter to filter a bass frequency range of the input signal and configures the amplifier to attenuate the amplitude of the filtered bass frequency range of the input signal.
- the signal level detector may determine that the input signal strength is below a threshold level.
- the plurality of switchable electronic components may be switched to a configuration that configures the bandwidth filter to filter a bass frequency range of the input signal and configures the amplifier to amplify the amplitude of the filtered bass frequency range of the input signal.
- the switching resolution of the plurality of switchable electronic components between different configurations may be progressively increased as the input signal is progressively increased.
- a method for dynamic bass frequency control comprising: filtering a frequency range of an input signal; adjusting amplitude of the filtered frequency range of the input signal; determining signal strength of the input signal; switching a plurality of switchable electronic components between more than one configuration based on the signal strength of the input signal; and determining based on the configuration the frequency range of the input signal to filter and the amplitude adjustment to be made to the filtered frequency range of the input signal.
- the method may further comprise determining a zero crossing point in the input signal, generating a zero crossing signal upon determining a zero crossing point, and switching the plurality of switchable electronic components between the more than one configuration based on the zero crossing signal.
- the method may further comprise storing a switching signal to switch the switchable electronic components between the more than one configuration, and forwarding the stored switching signal to switch the switchable electronic components between the more than one configuration on receiving the zero crossing signal.
- the method may further comprise switching the plurality of switchable electronic components to a configuration that causes the filtering of a bass frequency range of the input signal and attenuation of the amplitude of the filtered bass frequency range of the input signal if the input signal strength is determined to be above a threshold level.
- the method may further comprise switching the plurality of switchable electronic components to a configuration that causes the filtering of a bass frequency range of the input signal and amplification of the amplitude of the filtered bass frequency range of the input signal if the input signal strength is determined to be below a threshold level.
- FIG. 1 shows Fletcher-Munson curves.
- FIG. 2 shows a schematic drawing of a dynamic low frequency control circuit according to an example embodiment of the present invention.
- FIG. 3 shows a schematic drawing of a dynamic low frequency control circuit according to an example embodiment of the present invention.
- FIG. 4 shows a schematic drawing of a signal level detector according to an example embodiment of the present invention.
- FIG. 5 shows a schematic drawing of a zero crossing detector according to an example embodiment of the present invention.
- FIG. 6 shows frequency response curves of an example embodiment of the present invention.
- FIG. 7 shows frequency response curves of an example embodiment of the present invention.
- FIG. 8 shows frequency response curves of an example embodiment of the present invention.
- FIG. 9 shows a schematic drawing of a dynamic low frequency control circuit according to an example embodiment of the present invention.
- FIG. 10 shows a flowchart illustrating a method according to an example embodiment of the present invention
- FIG. 2 An example embodiment of the present invention is illustrated in FIG. 2 .
- a system for dynamic bass frequency control in the form of a dynamic low frequency control circuit 200 having compression control.
- the circuit 200 is used generally for dynamic loudness compensation. It comprises a feed-forward control topology for dynamically adjusting the low frequency range of an input signal 202 based on the input signal level detected. During low input signal level, low frequency components of the input signal 202 would be boosted, while during high input signal level, low frequency components of the input signal 202 would be maintained or compressed. In this manner, loudness compensation is achieved to counter the effects of irregularity in human hearing, which is derived based on the Fletcher-Munson Curves shown in FIG. 1 . Additionally, the circuit 200 also limits distortion of extremely high input signal level in the low frequency range.
- the circuit 200 includes a signal level detector 206 , a zero crossing detector 208 , a buffer device 214 with trigger detection, a bandwidth filter 210 and a plurality of switchable electronic components 212 .
- the function of the circuit 200 is to receive input signal 202 and adjust the input signal 202 automatically using its components to produce a desired output signal 204 .
- the input signal 202 and output signal 204 in the example embodiment are electrical audio signals.
- the plurality of switchable electronic components may include resistors, inductors, capacitors, or a mix of resistors, capacitors and/or inductors that are connected up and switchable between various configurations for adjusting a bandwidth filter 210 and an amplifier (incorporated as part of the bandwidth filter 210 in the example embodiment and not shown in FIG. 2 ) to achieve dynamic loudness compensation.
- the capacitors, inductors and/or resistors could be placed in parallel and/or in series connection with one another, along with switches located at appropriate locations, to obtain various switchable configurations.
- the various configurations cause the circuitry of the bandwidth filter 210 and the amplifier to change and compensate loudness according to the changes.
- the signal level detector 206 is used firstly to retrieve the RMS (root mean square) voltage of the input signal 202 , which is representative of the signal strength of the input signal 202 . Next, the signal level detector 206 compares the root mean square voltage with a threshold voltage. If the signal strength of the input signal 202 is beyond the threshold voltage. The signal level detector will generate a switching signal to be sent to the switchable electronic components 212 .
- RMS root mean square
- the zero crossing detector 208 receives the input signal 202 to determine instances where the input signal 202 crosses zero voltage. At those instances, the zero crossing detector 208 would generate a zero crossing signal. The switching of the switchable electronic components 212 is enabled only when the input signal 202 crosses zero voltage.
- the buffer device 214 buffers signals from the signal level detector 206 and sends the buffered signals on a first in first out basis to the plurality of switchable electronic components 212 upon receiving a zero crossing signal (i.e. a triggering signal) from the zero crossing detector 208 .
- a zero crossing signal i.e. a triggering signal
- the bandwidth filter 210 receives the input signal 202 and provides the necessary signal level boost (i.e. amplifies) or compression, and widening or reduction of a filtered frequency range of the input signal 202 .
- the bandwidth filter 210 of the example embodiment includes an amplifier (e.g. 316 in FIG. 3 ; not shown in FIG. 2 ).
- the amplifier is part of the bandwidth filter 210 and is used for performing the signal level boost or compression.
- the bandwidth filter 210 is operatively connected to the switchable electronic components 212 and the frequency response of the bandwidth filter 210 is adjustable by changing the configuration of the switchable electronic components of the switchable electronic components 212 .
- the plurality of switchable electronic components 212 refers to multiple capacitors in parallel connection.
- the switchable electronic components 212 are switchable between various capacitor configurations to provide different capacitance values.
- the plurality of switchable electronic components may include two or more separate capacitor banks (e.g. 302 and 304 in FIG. 3 ) where the banks include switches for connecting up one or more capacitors to form a capacitor configuration.
- the input signal 202 is fed to the bandwidth filter 210 , the signal level detector 206 and the zero crossing detector 208 .
- the signal level detector 206 and the zero crossing detector 208 operate together with the buffer device 214 to switch the configuration of the switchable electronic components 212 according to current input signal strength.
- Each configuration may be associated with, for instance, a specific capacitance value (e.g. in the case of 1 capacitor bank) or a specific set of capacitance values (e.g. in the case of 2 or more capacitor banks where each bank may have different capacitance values).
- the number of switches to close or open in the switchable electronic components 212 to achieve a particular capacitance value is determined by the root mean square voltage of the input signal 202 .
- switching signals are sent to the buffer device 214 , which will forward the switching signals to the switchable electronic components 212 to change configuration upon receiving a zero crossing signal from the zero crossing detector 208 .
- the switches are opened or closed only at the zero crossing points in the input signal 202 , which are detected by the zero crossing detector 208 . If the switches are allowed to be triggered or toggled beyond zero crossing points in the input signal 202 , the resulting distortions may be heard as abrupt jumps in the sound output.
- each configuration determines the frequency range of the input signal to be filtered by the bandwidth filter 210 and the amplitude adjustment to be made to the filtered frequency range of the input signal 202 by the amplifier, which is part of the bandwidth filter 210 .
- the configuration of the switchable electronic components By adjusting the configuration of the switchable electronic components, output signals 204 with different characteristics in terms of the gain and the centre frequency could be produced.
- the input signal 202 is adjusted by tuning the bandwidth filter 210 , i.e. changing the configuration of the switchable electronic components to a configuration such that the amplitude of the low frequency range of the input signal 202 is increased, maintained or reduced to compensate for the effects of the irregularity in human hearing, which is illustrated in the Fletcher-Munson Curves shown in FIG. 1 .
- the bandwidth filter 210 is adjusted to provide signal boost for the low frequency range of the input signal 202 .
- input signal with high signal strength i.e.
- the input signal strength is maintained and the bandwidth filter 210 would not be adjusted to boost the low frequency range.
- the low frequency range of the input signal 202 has to be controlled such that the output signal 204 does not suffer from undue distortion due to clipping of the audio signal as its signal strength goes beyond the supported range of signal levels of the circuit 200 .
- the bandwidth filter 210 is adjusted to reduce the signal strength of the low frequency range of the input signal 202 to a level not exceeding the supported range of signal levels of the circuit 200 .
- a feed-forward control topology is used in the circuit 200 of the example embodiment as it has several advantages.
- a feed-forward control topology reacts to signal changes and alters the output signal 204 much faster than a feedback topology. Hence, to an average user, he or she would find the transition between soft sounds (where low frequency range of the input signal 202 is boosted by the circuit 200 ) and loud sounds (where distortion due to clipping in the low frequency range of the input signal 202 is limited by the circuit 200 ), to be smoother and less glaring.
- the circuit 200 of the example embodiment can be incorporated in a multimedia speaker system to obtain dynamic bass boost and compression control of the audio signal as the input signal level changes.
- loudness compensation is introduced, such that the low frequency components are boosted.
- loudness compensation would be halted, such that the low frequency components are not expanded or boosted.
- the low frequency components are compressed to prevent clipping of signal. It is noted that low frequency audible clipping would result in unpleasant listening.
- FIG. 3 shows a non-limiting example of a specific implementation of the dynamic low frequency control circuit 200 described earlier with reference to FIG. 2 .
- the bandwidth filter 210 is constructed based on a first order operational amplifier bandpass filter circuit 306 .
- the switchable electronic components 212 comprise two capacitor banks 302 and 304 .
- the first capacitor bank 302 is connected adjacent to the source of the input signal, V i , 202 .
- the second capacitor bank 304 is connected along the feedback loop 318 of an operational amplifier 316 linking the output point having the output signal, V o , 204 to the inverting input 320 of the operational amplifier 316 .
- the operational amplifier 316 provides a gain, G, which is dependent on the capacitance values of the switchable electronic components 212 .
- the first capacitor bank 302 has four capacitors, C 1 308 , C 2 334 , C 3 336 and C 4 338 .
- C 1 308 is the default capacitance of the first capacitor bank.
- C 2 334 , C 3 336 and C 4 338 are in series connection with three switches, SW 1 312 , SW 2 340 and SW 3 342 respectively.
- the individual series connections of C 2 334 and SW 1 312 , C 3 336 and SW 2 340 , and C 4 338 and SW 3 342 respectively are in parallel connection with one another and with C 1 308 .
- the second capacitor bank 304 has four capacitors, C 21 310 , C 22 344 , C 23 346 , and C 24 348 .
- C 21 310 is the default capacitance of the first capacitor bank.
- C 22 344 , C 23 346 and C 24 348 are in series connection with three switches, SW 21 350 , SW 22 352 and SW 23 354 respectively.
- the individual series connections of C 22 344 and SW 21 350 , C 23 346 and SW 22 352 , and C 24 348 and SW 23 354 respectively are in parallel connection with one another and with C 21 310 .
- resistors 322 , 324 , 326 and 328 are connected to the operational amplifier 316 and the capacitor banks 302 and 304 .
- the first resistor, R 1 , 324 is connected between the inverting input 320 and the first capacitor bank 302 .
- the second resistor, R 2 , 326 is connected along the feedback loop 318 and is in parallel connection with a series connection comprising of the third resistor, R 3 , 328 and the second capacitor bank 304 .
- the fourth resistor, R 4 , 322 is connected between a reference voltage source 330 and the non-inverting input 332 of the operational amplifier 316 .
- G Z 1 Z 2
- Z 1 R ⁇ ⁇ 2 ⁇ ( 1 + w c ⁇ C 2 ⁇ R ⁇ ⁇ 3 ) 1 + w c ⁇ C 2 ⁇ R ⁇ ⁇ 2 + w c ⁇ C 2 ⁇ R ⁇ ⁇ 3
- Z 2 1 + w c ⁇ C 1 ⁇ R ⁇ ⁇ 1 w c ⁇ C 1 where, total second capacitor bank capacitance
- f c w c 2 ⁇ ⁇ ⁇
- f c the centre frequency of the boosted signal in the low frequency component.
- f c is selected to be in the range of 80 Hz-100 Hz.
- the buffer device 214 coupled to the signal level detector 206 and zero crossing detector 208 has three buffers with triggering edge detectors 314 , 356 and 358 .
- the buffer device 214 receives signals from both the signal level detector 206 and the zero crossing detector 208 .
- the signals from the signal level detector 206 direct the switching, i.e. opening or closing of the switches in the first and second capacitor banks 302 and 304 , whereas the signals from the zero crossing detector 208 determine when to switch the switches.
- the buffer device 214 buffers or stores switching signals from the signal level detector 206 in buffers 314 , 356 and 358 .
- the buffer device 214 waits for the receipt of a pulse signal from the zero crossing circuit 208 and forwards the switching signals to the first and second capacitor banks 302 and 304 to change the configuration of the first and/or second capacitor banks 302 and 304 on detecting the triggering edge of the pulse signal.
- switchable capacitor banks could be coupled to the higher order bandpass filter circuit for adjusting the filtering and/or amplitude adjustment performance of the circuit.
- FIG. 4 is a non-limiting example of the signal level detector 206 shown in FIGS. 2 and 3 that is used for toggling switches SW 1 312 , SW 2 340 and SW 3 342 of the first capacitor bank 302 , and switches SW 21 350 , SW 22 352 and SW 23 354 of the second capacitor bank 304 .
- Each of the switches SW 1 312 , SW 2 340 and SW 3 342 of the first capacitor bank 302 may be normally closed and require an electrical signal to open if analogue electronic switches are used, or require overcoming a biasing force, from a spring, magnetic force, or other biasing means, to open if electromechanical switches are used.
- the switches SW 21 350 , SW 22 352 and SW 23 354 of the second capacitor bank 304 may be normally opened and require an electrical signal to close if analogue electronic switches are used, or require overcoming a biasing force, from a spring, magnetic force, or other biasing means, to close if electromechanical switches are used.
- all the switches SW 1 312 , SW 2 340 , SW 3 342 , SW 21 350 , SW 22 352 and SW 23 354 are analogue electronic switches, which can be switched on or off through an applied electrical voltage.
- a first, a second and a third operational amplifier 402 , 404 and 406 respectively.
- Each of these amplifiers 402 , 404 and 406 is used as a voltage comparator.
- the inverting inputs 408 , 410 and 412 of the operational amplifiers 402 , 404 and 406 are each held at three threshold levels with voltage values, V 3 , V 2 and V 1 respectively.
- a reference Voltage, V ref is proportioned by a series connection of four resistors, R 1 420 , R 2 422 , R 3 424 and R 4 426 so as to provide the threshold voltages V 3 , V 2 and V 1 .
- R 1 420 is connected adjacent to the reference Voltage source, V ref .
- R 2 422 is connected adjacent to R 1 420 and R 3 424 is connected adjacent to R 2 422 .
- R 4 426 is connected adjacent to R 3 424 .
- R 4 426 is connected to ground.
- the threshold voltage, V 3 is available between R 1 420 and R 2 422
- V 2 is available between R 2 422 and R 3 424
- V 1 is available between R 3 424 and R 4 426 .
- the values of the threshold voltages are in the relationship, V 3 >V 2 >V 1 .
- V 3 is for detecting high input signal level
- V 2 is for detecting medium input signal level
- V 1 is for detecting low input signal level.
- the outputs of each amplifier 402 , 404 and 406 would be HIGH when the input signal 202 reaches their individual threshold voltages, otherwise the outputs would be LOW.
- the outputs of the amplifiers 402 , 404 and 406 control the opening of specific switches in the first capacitor bank 302 , which are normally closed, and the closing of specific switches in the second capacitor bank 304 , which are normally opened.
- the output of amplifier 402 is coupled to buffer 314 in FIG. 3 and it is the switching signal for controlling switches, SW 3 342 and SW 21 350 .
- the output of amplifier 404 is coupled to buffer 356 in FIG. 3 and it is the switching signal for controlling switches SW 2 340 and SW 22 352 .
- the output of amplifier 406 is coupled to buffer 358 in FIG. 3 and it is the switching signal for controlling SW 1 312 and SW 23 354 . It is noted that the switches are only triggered by switching signals stored at the buffers 314 , 356 and 358 . The stored switching signals are forwarded to the switches at the time when the buffer device ( 214 in FIGS. 2 and 3 ) detects the triggering edge of a pulse signal generated by the zero crossing detector ( 208 in FIGS. 2 ,
- the non-inverting inputs 414 , 416 and 418 of the operational amplifiers 402 , 404 and 406 respectively are connected to resistors R 10 428 , R 11 430 and R 12 432 respectively at one end.
- the other end of the resistors R 10 428 , R 11 430 and R 12 432 is connected to an output end of a rectifier diode 436 .
- the input end (i.e. p-type material end) of the rectifier diode 436 i.e. a p-n junction diode) is connected to receive the input signal 202 from its source (not shown in the figures).
- a capacitor, C 41 434 is connected between the output end (i.e.
- the rectifier diode 436 and the capacitor C 41 434 are utilised in the rectification of the alternating input signal 202 to provide a Direct Current (DC) signal with a root mean square voltage, V rms , to the non-inverting inputs 414 , 416 and 418 .
- the DC signal received at the non-inverting inputs 414 , 416 , and 418 is then compared with the three threshold values to determine its signal level.
- V rms is in a very low voltage range, i.e. 0 ⁇ V rms ⁇ V 1
- none of the amplifiers 402 , 406 and 408 would produce any output and none of the switches will be toggled.
- the switches will remain in its normal configuration, that is, SW 1 312 , SW 2 340 and SW 3 342 would be closed, and SW 21 350 , SW 22 352 and SW 23 354 would be opened.
- the capacitance value of the first capacitor bank 302 is equal to the capacitance value of C 1 308 +C 2 334 +C 3 336 +C 4 338 and the capacitance value of the second capacitor bank 304 is equal to the capacitance value of C 21 310 .
- the third operational amplifier 406 would output a switching signal to open SW 3 342 and close SW 21 350 .
- the capacitance value of the first capacitor bank 302 is equal to the capacitance value of C 1 308 +C 2 334 +C 3 336 and the capacitance value of the second capacitor bank 304 is the capacitance of C 21 310 +C 22 344 .
- the second operational amplifier 404 would output a switching signal to open SW 2 340 and close SW 22 352 .
- the capacitance value of the first capacitor bank 302 is equal to the capacitance value of C 1 308 +C 2 334 and the capacitance value of the second capacitor bank 304 is the capacitance of C 21 310 +C 22 344 +C 23 346 .
- the first operational amplifier 402 would output a switching signal to open SW 1 312 and close SW 23 354 .
- the capacitance value of the first capacitor bank 302 is equal to the capacitance value of C 1 308 and the capacitance value of the second capacitor bank 304 is the capacitance of C 21 310 +C 22 344 +C 23 346 +C 24 348 .
- each one of the analogue electronic switches SW 1 312 , SW 2 340 , SW 3 342 , SW 21 350 , SW 22 352 and SW 23 354 described with reference to FIGS. 3 and 4 could be for instance, an electronic component that behaves in a similar way to a relay switch but has no moving parts.
- the switching element could be a MOSFET.
- the control input to the analogue electronic switch could be a CMOS or TTL logic input, which is shifted by internal circuitry to a suitable voltage for switching the MOSFET. The result is that logic 0 on the control input would cause the MOSFET to have a high resistance, so that the switch is off, and logic 1 on the control input causes the MOSFET to have a low resistance, so that the switch is on.
- FIG. 5 shows a non-limiting example of an implementation of the zero crossing detector 208 .
- the zero crossing detector 208 is a device for detecting the instant where an input signal voltage crosses zero voltage and generates a zero crossing pulse, i.e. a square wave or pulse of short time duration, at that instant.
- a diode 502 i.e. a p-n junction diode arranged to receive the input signal 202 described with reference to FIG. 2 at its input end (i.e. p-type material end).
- Located downstream of the diode 502 is an NPN transistor 504 having a base terminal 508 , an emitter terminal 510 and a carrier terminal 512 .
- the emitter terminal 510 is grounded.
- a capacitor, C 51 506 is connected across the base terminal 508 and the emitter terminal 510 of the NPN transistor 504 .
- the carrier terminal 512 is connected to one end of a resistor, R 51 514 .
- the other end of the resistor R 51 514 is connected to a reference voltage point 516 with voltage, V ref .
- the output point of the zero crossing detector 208 which provides the output voltage and emits the zero crossing pulse, is at the carrier terminal 512 .
- the capacitor, C 51 506 charges up to a voltage level, V c , on receiving the input signal 202 through the diode 502 and is used to minimize ripples when providing a Direct Current (DC) signal to the base terminal 508 of the NPN transistor 504 .
- the NPN transistor 504 remains OFF until a Cut-in voltage V BE between the Base terminal 508 and the emitter terminal 510 , is reached. During the OFF period of the NPN transistor 504 , the output voltage at the carrier terminal 512 will be high and approximately equal to the voltage at the reference voltage point 516 , V ref .
- the NPN transistor 504 moves towards saturation where the output at the carrier terminal 512 reduces to the saturation voltage of the NPN transistor 504 , which is nearly equal to zero.
- V BE is set to be equal to the cut-in or ON voltage of the diode 502 .
- the capacitor, C 51 506 will charge through the diode 502 at approximately V m , where V m is the maximum amplitude of the DC signal generated to the base terminal 508 .
- the base current I B would flow and the NPN transistor 504 would be turned ON.
- the NPN transistor 504 is ON, the voltage at the carrier terminal 512 becomes nearly equal to zero.
- base current, I B would cease to flow.
- base current, I B ceases to flow, the NPN transistor 504 switches to OFF and the voltage at the carrier terminal 512 becomes about V ref .
- an output square wave or pulse is produced at the carrier terminal 512 whenever the voltage of the input signal 202 crosses zero, thereby providing the effect of a zero crossing detector.
- FIG. 6 shows the frequency response of the dynamic low frequency control circuit 200 described with reference to FIGS. 2 and 3 when the capacitance of the second capacitor bank 304 is fixed at one value and the capacitance of the first capacitor bank 302 is varied.
- the dynamic low frequency control circuit 200 produces an output having frequency response, as illustrated by curve 602 , which provides lesser or no gain to the filtered range of frequencies in the low audible frequency range. Decreasing the capacitance of the first capacitor bank 302 would result in bass signal attenuation in the low audible frequency range and the centre frequency, f c will shift towards the higher frequency range.
- the dynamic low frequency control circuit 200 produces an output having frequency response, as illustrated by curve 604 , which has an increase in gain to the filtered range of frequencies in the lower audible frequency range.
- Increasing the capacitance of the first capacitor bank 302 would result in bass boost or increased bass boost in the low audible frequency range and the centre frequency, f c will shift towards the lower frequency range.
- the High capacitance frequency response curve 604 appears to shift upwards and spreads wider to the left of the Low capacitance frequency response curve 602 , therefore indicating a lower centre frequency in the low audible frequency range.
- the High capacitance frequency response curve 604 also appears further away from the frequency axis, indicating an increase in the gain of the filtered range of frequencies of the output signal of the dynamic low frequency control circuit 200 .
- FIG. 7 shows the frequency response of the dynamic low frequency control circuit 200 described with reference to FIGS. 2 and 3 when the capacitance of the first capacitor bank 302 is fixed at one value and the capacitance of the second capacitor bank 304 is varied.
- the dynamic low frequency control circuit 200 produces an output having frequency response, as illustrated by curve 702 , which has an increase in gain to the filtered range of frequencies for the output signal in the low audible frequency range. Decreasing the capacitance of the second capacitor bank 304 would result in bass boost or increased bass boost in the low audible frequency range and the centre frequency, f c will shift towards the higher frequency range.
- the dynamic low frequency control circuit 200 produces an output having frequency response, as illustrated by curve 704 , which provides lesser gain to the filtered range of frequencies in the low audible frequency range.
- Increasing the capacitance of the second capacitor bank 304 would result in bass signal attenuation in the low audible frequency range and the centre frequency, f c will shift towards the lower frequency range.
- the Low capacitance frequency response curve 702 appears to shift and move upwards to the right of the High capacitance frequency response curve 704 , therefore indicating a higher centre frequency in the low audible frequency range.
- the Low capacitance frequency response curve 702 also appears further away from the frequency axis, indicating an increase in the gain of the filtered range of frequencies of the output signal of the dynamic low frequency control circuit 200 .
- FIGS. 8 and 9 illustrate a dynamic low frequency control circuit 900 of another example embodiment of the present invention.
- FIG. 8 illustrates the frequency response of a dynamic low frequency control circuit 900 .
- the dynamic low frequency control circuit 900 is substantially similar to the dynamic low frequency control circuit 200 described with reference to FIGS. 2 and 3 .
- the only differences between the dynamic low frequency control circuit 900 and the circuit 200 illustrated in FIGS. 2 and 3 are as follow. Firstly, the first capacitor bank 302 of the circuit 200 illustrated by FIGS. 2 and 3 is replaced by one capacitor, C 1 902 . Secondly, the second capacitor bank 304 of the circuit 200 illustrated by FIGS. 2 and 3 is replaced by a capacitor bank 904 having seven capacitors, C 21 906 , C 22 908 , C 23 910 , C 24 912 , C 25 914 , C 26 916 and C 27 918 , connected in parallel with one another. Of the seven capacitors, six of the capacitors, i.e.
- C 22 to C 27 ( 908 , 910 , 912 , 914 , 916 and 918 ), are each connected in series with a switch, i.e. SW 1 920 , SW 2 922 , SW 3 924 , SW 4 926 , SW 5 928 and SW 6 930 .
- a switch i.e. SW 1 920 , SW 2 922 , SW 3 924 , SW 4 926 , SW 5 928 and SW 6 930 .
- Each of these switches is used for connecting or disconnecting the corresponding capacitor in accordance with the switching signals from a signal level detector 932 (or level detector circuit), which operates together with the connected zero crossing detector 934 (or zero crossing detector circuit) and a buffer device 948 .
- the signal level detector 932 , zero crossing detector 934 and the buffer device 948 operates in the same manner as the signal level detector 206 , zero crossing detector 208 and the buffer device 214 described with reference to FIGS. 2 and 3 .
- the dynamic low frequency control circuit 900 has six switchable resolutions and a default resolution.
- the component values for the dynamic low frequency control circuit 900 are shown in the table as follow. Resistors of the dynamic low frequency control circuit 900 , R 1 936 , R 2 938 , R 3 940 and R 4 942 correspond with resistors R 1 324 , R 2 326 , R 3 328 and R 4 322 in the circuit 200 of FIGS. 2 and 3 .
- the capacitance value of the capacitor bank 904 is varied based on the input signal 944 in a manner as follow. That is, low capacitance value is set during low input signal level, and high capacitance value is set during high input signal level.
- the switches SW 1 920 , SW 2 922 , SW 3 924 , SW 4 926 , SW 5 928 and SW 6 930 connected in series with the respective capacitors C 22 to C 27 ( 908 , 910 , 912 , 914 , 916 and 918 ) are connected/disconnected based on the input signal strength accordingly to increase or decrease the capacitance value of the capacitor bank 904 .
- waveform 814 represents the frequency response of the output signal 946 when the output signal level is ⁇ 16 dB and the capacitor bank 904 is configured to have the capacitance of C 21 only, i.e. 17.2 nF.
- Waveform 812 represents the frequency response of the output signal 946 when the output signal level is ⁇ 13 dB and the capacitor bank 904 is configured to have the capacitance of C 21 +C 22 , i.e. 27.2 nF.
- Waveform 810 represents the frequency response of the output signal 946 when the output signal level is ⁇ 10 dB and the capacitor bank 904 is configured to have the capacitance of C 21 +C 22 +C 23 , i.e. 42.2 nF.
- Waveform 808 represents the frequency response of the output signal 946 when the output signal level is ⁇ 8 dB and the capacitor bank 904 is configured to have the capacitance of C 21 +C 22 +C 23 +C 24 , i.e. 57.2 nF.
- Waveform 806 represents the frequency response of the output signal 946 when the output signal level is ⁇ 6 dB and the capacitor bank 904 is configured to have the capacitance of C 21 +C 22 +C 23 +C 24 +C 25 , i.e. 72.2 nF.
- Waveform 804 represents the frequency response of the output signal 946 when the output signal level is ⁇ 4 dB and the capacitor bank 904 is configured to have the capacitance of C 21 +C 22 +C 23 +C 24 +C 25 +C 26 , i.e. 94.2 nF.
- Waveform 802 represents the frequency response of the output signal 946 when the output signal level is ⁇ 2 dB and the capacitor bank 904 is configured to have the capacitance of C 21 +C 22 +C 23 +C 24 +C 25 +C 26 +C 27 , i.e. 141.2 nF.
- Waveform 814 is desired when the entire audible sound input 944 is required to be amplified, such as in cases where the input signal strength is low.
- Waveform 802 is desired when the low frequency audible sound input 944 , comprising the bass sound, is required to be compressed or attenuated, such as in cases where the input signal strength is high.
- step 1002 filtering a frequency range of an input signal (e.g. 202 in FIGS. 2 to 5 ).
- step 1004 adjusting amplitude of the filtered frequency range of the input signal (e.g. 202 in FIGS. 2 to 5 ).
- step 1006 determining signal strength of the input signal (e.g. 202 in FIGS. 2 to 5 ).
- step 1008 switching a plurality of switchable electronic components (e.g. 212 in FIG. 2 ) between more than one configuration based on the signal strength of the input signal (e.g. 202 in FIGS. 2 to 5 ).
- step 1010 determining based on the capacitor configuration the frequency range of the input signal (e.g. 202 in FIGS. 2 to 5 ) to filter and the amplitude adjustment to be made to the filtered frequency range of the input signal (e.g. 202 in FIGS. 2 to 5 ).
- the switching resolution may be increased further by adding more switches and capacitors in the capacitor banks (e.g. 302 and 304 in FIG. 3 ) or by adding more capacitor banks to provide more signal compensation states for seamless audio transition in the audio output of the dynamic low frequency control circuit.
- the outputs of the signal level detector 206 described with reference to FIGS. 2 , 3 and 4 may be directly connected to the switchable electronic components ( 212 in FIG. 2 ), or the first and/or second capacitor banks ( 302 and 304 in FIG. 3 ).
- the zero signal detector 206 and buffer device 214 are bypassed. While there may be distortion due to jumps because of adjustment transitions at non-zero crossing junctures, the distortion may be bearable (if not negligible) if the switching resolution is very high and responsive (e.g. in terms of hardware processing speed). Also, the distortion would not matter in certain applications not requiring a high degree of signal quality in the output signal ( 204 in FIGS. 2 and 3 ).
- the bandwidth filter 210 described with reference to FIG. 2 may be solely used for filtering frequency range and does not provide signal amplification.
- an amplifier (not shown in FIG. 2 ) which is not part of the bandwidth filter 210 could be connected at the input or output stage of the bandwidth filter 210 to provide the necessary signal level boost or compression.
- the switchable electronic components 212 would be coupled to both the amplifier and the bandwidth filter 210 and similar to the example embodiments herein described, changing the capacitance of the switchable electronic components 212 would cause the overall frequency response of the combined circuitry of the amplifier and bandwidth filter 210 to be adjusted.
- switching resolution of the plurality of switchable electronic components between different configurations could be progressively increased as the input signal is progressively increased.
- that means having progressively more configurations to compensate loudness as the input signal gets louder and progressively lesser configurations to compensate loudness as the input signal gets softer.
- the reason for doing so is because the human ear is not so sensitive to audio transitions due to loudness compensation at softer input signals.
- Some modifications to the dynamic low frequency control circuit could be to include circuitry in the signal level detector to compare more threshold voltages of higher amplitudes.
- more capacitor configurations could be implemented for loudness compensation when each of the threshold voltages is reached.
Abstract
Description
- The capacitances of
C1 308,C2 334,C3 336,C4 338,C21 310,C22 344,C23 346, andC24 348 are represented by C1, C2, C3, C4, C22, C23 and C24 respectively in the equations. The resistance ofR1 322,R2 324,R3 326 and R4 328 are represented by R1, R2, R3 and R4 respectively in the equations.
where, total second capacitor bank capacitance,
the value of n being 1 if the corresponding switch is closed and 0 if the corresponding switch is opened.
where, total first capacitor bank capacitance,
the value of n being 1 if the corresponding switch is closed and 0 if the corresponding switch is opened.
where, fc is the centre frequency of the boosted signal in the low frequency component. In the example embodiment, fc is selected to be in the range of 80 Hz-100 Hz.
Component | Value | ||
R1 | 10K | ohm | ||
R2 | 100K | ohm | ||
R3 | 10K | ohm | ||
R4 | 10K | ohm | ||
C1 | 330 | nF (nano-Farad) | ||
C21 | 17.2 | nF (nano-Farad) | ||
| 10 | nF (nano-Farad) | ||
C23 | 15 | nF (nano-Farad) | ||
C24 | 15 | nF (nano-Farad) | ||
C25 | 15 | nF (nano-Farad) | ||
C26 | 22 | nF (nano-Farad) | ||
C27 | 47 | nF (nano-Farad) | ||
By varying the capacitor configuration of the capacitor bank 904 of the
Claims (13)
Priority Applications (3)
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US12/342,754 US8194887B2 (en) | 2008-12-23 | 2008-12-23 | System and method for dynamic bass frequency control in association with a dynamic low frequency control circuit having compression control |
EP09835360.0A EP2368373B1 (en) | 2008-12-23 | 2009-11-23 | System and method for dynamic bass frequency control |
PCT/SG2009/000440 WO2010074658A1 (en) | 2008-12-23 | 2009-11-23 | System and method for dynamic bass frequency control |
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US12/342,754 US8194887B2 (en) | 2008-12-23 | 2008-12-23 | System and method for dynamic bass frequency control in association with a dynamic low frequency control circuit having compression control |
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US8194887B2 true US8194887B2 (en) | 2012-06-05 |
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EP (1) | EP2368373B1 (en) |
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US11202149B1 (en) | 2020-09-11 | 2021-12-14 | Ford Global Technologies, Llc | Vehicle audio control |
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US9247342B2 (en) | 2013-05-14 | 2016-01-26 | James J. Croft, III | Loudspeaker enclosure system with signal processor for enhanced perception of low frequency output |
US9590580B1 (en) * | 2015-09-13 | 2017-03-07 | Guoguang Electric Company Limited | Loudness-based audio-signal compensation |
US10483931B2 (en) | 2017-03-23 | 2019-11-19 | Yamaha Corporation | Audio device, speaker device, and audio signal processing method |
GB2563687B (en) * | 2017-06-19 | 2019-11-20 | Cirrus Logic Int Semiconductor Ltd | Audio test mode |
CN113131888A (en) * | 2020-01-10 | 2021-07-16 | 微龛(广州)半导体有限公司 | Bandwidth-adjustable amplifier circuit, method, medium, terminal and optical receiver |
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Publication number | Publication date |
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EP2368373A1 (en) | 2011-09-28 |
EP2368373A4 (en) | 2013-04-03 |
WO2010074658A1 (en) | 2010-07-01 |
EP2368373B1 (en) | 2016-01-27 |
US20100158273A1 (en) | 2010-06-24 |
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