US8222152B2 - Method for fabricating hole pattern - Google Patents

Method for fabricating hole pattern Download PDF

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US8222152B2
US8222152B2 US12/774,644 US77464410A US8222152B2 US 8222152 B2 US8222152 B2 US 8222152B2 US 77464410 A US77464410 A US 77464410A US 8222152 B2 US8222152 B2 US 8222152B2
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hard mask
layer
pattern
mask layer
photoresist pattern
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US20110159693A1 (en
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Jun-Hyeub Sun
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

  • the present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a hole pattern using a double patterning process.
  • a double patterning technology is used to form a hole.
  • the double patterning technology forms a hole by forming a line in a crossing direction, where such technology is adapted for patterning rather than creating holes.
  • a dual hard mask of a Plasma Enhanced Tetra Ethyl Ortho Silicate (PETEOS) oxide layer and a silicon oxide nitride layer is used for patterning.
  • PETEOS Plasma Enhanced Tetra Ethyl Ortho Silicate
  • the silicon oxide nitride layer which is an upper layer of the dual hard mask, is etched first
  • the PETEOS oxide layer which is a lower layer of the dual hard mask, is etched using the etched silicon oxide nitride layer and a photoresist pattern as an etch barrier.
  • FIGS. 1A to 1D are perspective views illustrating a conventional method for forming a hole pattern.
  • an amorphous carbon layer 12 , a PETEOS oxide layer 13 , a silicon oxide nitride layer 14 , and an anti-reflective coating (ARC) layer 15 are sequentially formed over an etch-target layer 11 .
  • the amorphous carbon layer 12 is used as a hard mask to etch the etch-target layer 11
  • the PETEOS oxide layer 13 is used as a basic hard mask during a double patterning process
  • the silicon oxide nitride layer 14 is used as a hard mask to etch the PETEOS oxide layer 13 .
  • a first photoresist pattern 16 is formed over the ARC layer 15 .
  • the first photoresist pattern 16 is formed as a line type in a first direction.
  • the ARC layer 15 and the silicon oxide nitride layer 14 are etched using the first photoresist pattern 16 as an etch barrier. Since the first photoresist pattern 16 is the line type, the ARC layer 15 and the silicon oxide nitride layer 14 are also formed as a line type in the first direction.
  • a silicon oxide nitride pattern 14 A is formed by removing the first photoresist pattern 16 and the ARC layer 15 (shown in FIG. 1A ).
  • a second photoresist pattern 17 is formed over a resultant structure including the silicon oxide nitride pattern 14 A.
  • the second photoresist pattern 17 may be formed as a line type in a second direction which is perpendicular to the first direction. Accordingly, a hole pattern is defined by the second photoresist pattern 17 and the silicon oxide nitride pattern 14 A.
  • the PETEOS oxide layer 13 is etched using the second photoresist pattern 17 and the silicon oxide nitride pattern 14 A as an etch barrier (shown in FIG. 1C ), thereby forming a PETEOS oxide pattern 13 A.
  • the PETEOS oxide pattern 13 A defines the hole pattern.
  • the hole pattern is defined by the second photoresist pattern 17 and the silicon oxide nitride pattern 14 A.
  • etch characteristics may differ between the different masks, e.g., a Critical Dimension (CD) bias.
  • CD Critical Dimension
  • a wiggling can occur due to characteristics of an etch process for an oxide layer, which has a high ion energy.
  • FIG. 2 is a picture showing a wiggling of the conventional method for forming the hole pattern.
  • the wiggling 100 occurs in the second photoresist pattern used as an etch barrier during etching the PETEOS oxide layer.
  • Embodiments of the present invention are directed to providing a method for fabricating a hole pattern, which can prevent a wiggling due to etch barriers having etch characteristics different from each other during a double patterning process.
  • a method for fabricating a hole pattern including: forming a first hard mask layer over an etch target layer; forming a second hard mask pattern over the first hard mask layer, the second hard mask pattern being patterned to be a line type in a first direction and having a selective etch ratio to the first hard mask layer; forming a third hard mask layer over the first hard mask layer including the second hard mask pattern to bury a space between adjacent ones of the second hard mask pattern; forming a photoresist pattern over the third hard mask layer, the photoresist pattern being patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern; removing the photoresist pattern; and etching the first hard mask layer using the second and third hard mask patterns.
  • the first hard mask layer may comprise a poly silicon layer
  • the second hard mask pattern may comprise a nitride layer or a silicon nitride oxide layer
  • the third hard mask layer may comprise an oxide layer
  • the third hard mask layer may comprise a step coverage to bury the space between the adjacent ones of the second hard mask pattern, thereby having a minimum thickness to bury all the space between the adjacent ones of the second hard mask pattern and to not protrude greatly over the second hard mask pattern in height.
  • the third hard mask layer may be formed by Atomic Layer Deposition (ALD) or a Chemical Mechanical Deposition (CMD) using a furnace.
  • ALD Atomic Layer Deposition
  • CMD Chemical Mechanical Deposition
  • the first direction may be symmetrical to the second direction.
  • the first direction may have a tilt angle of approximately 45 degree while the second direction may have a tilt angle of approximately ⁇ 45 degree.
  • the first direction may have a tilt angle of approximately 45 degree to approximately 60 degree.
  • the etching of the third hard mask layer may be performed by a self-aligned contact (SAC) etch process by using a selective etch ratio of a nitride layer and an oxide layer, and may use a CxFy-based gas, where x and y are positive integers and y divided by x is smaller than or equal to three.
  • the CxFy-based gas may comprise C 4 F 6 or C 4 F 8 gas.
  • the etching of the third hard mask may be performed by using an oxygen (O 2 ) gas in addition to the CxFy-based gas.
  • the method may further comprise forming a stacked layer of a multi-function hard mask (MFHM) layer and one of an amorphous carbon layer and a Spin-on Coating (SoC) layer over the third hard mask layer.
  • the removing of the photoresist pattern may be performed by a dry strip process using oxygen (O 2 ) plasma.
  • the stacked layer may be removed by using oxygen (O 2 ) plasma during removing the photoresist pattern.
  • FIGS. 1A to 1D are perspective views illustrating a conventional method for forming a hole pattern.
  • FIG. 2 is a picture showing a wiggling of the conventional method for forming the hole pattern.
  • FIGS. 3A to 8B are cross-sectional views and plane views illustrating a method for fabricating a hole pattern in accordance with an embodiment of the present invention.
  • FIGS. 3A to 8B are cross-sectional views and plane views illustrating a method for fabricating a hole pattern in accordance with an embodiment of the present invention.
  • Each of FIGS. 3A , 4 A, 5 A, 6 A, 7 A and 8 A is a cross-sectional view illustrating the method for fabricating the hole pattern while each of FIGS. 3B , 4 B, 5 B, 6 B, 7 B and 8 B is a plane view illustrating the method for fabricating the hole pattern.
  • FIGS. 3A to 8B are explained in pairs.
  • a first hard mask layer 20 is formed over an etch target layer (not shown).
  • the first hard mask layer 20 may be formed of a poly silicon to etch the etch target layer.
  • a second hard mask layer 21 , a first mask layer 22 , and a second mask layer 23 are sequentially formed over the first hard mask layer 20 .
  • the second hard mask layer 21 may be used to etch the first hard mask layer 20 and have a selective etch ratio to the first hard mask layer 20 (for example, a ratio of etch rates).
  • the first hard mask layer 20 is formed of a poly silicon
  • the second hard mask layer 21 may be formed of a nitride layer or a silicon nitride oxide layer.
  • the nitride layer includes a silicon nitride.
  • the first mask layer 22 may be used to etch the second hard mask layer 21 and have a selective ratio to the first hard mask layer 20 as well as the second hard mask layer 21 .
  • the first mask layer 22 may be formed of an amorphous carbon.
  • the second mask layer 23 is used to etch the first mask layer 22 .
  • the second mask layer 23 may be formed of a silicon oxide nitride (SiON) layer.
  • a first photoresist pattern 24 is formed over the second mask layer 23 .
  • the first photoresist pattern 24 is patterned to have a line type in a first direction.
  • an anti-reflective coating (ARC) layer (not shown) may be formed over the second mask layer 23 .
  • the first photoresist pattern 24 has a tilt angle which is determined based on a target shape of the hole pattern.
  • the first photoresist pattern 24 may be formed to have a tilt angle of approximately 45 degree.
  • the first photoresist pattern 24 may be formed to have a tilt angle ranging from approximately 45 degree to approximately 60 degree.
  • the second mask layer 23 and the first mask layer 22 are etched using the first photoresist pattern 24 as an etch barrier.
  • the etch process is performed using Tetrafluoromethane (CF 4 ) gas, or a mixed gas of CF 4 gas and Fluoroform (CHF 3 ) gas.
  • the second hard mask layer 21 (shown in FIGS. 3A and 3B ) is etched by using the first mask layer 22 (shown in FIGS. 3A and 3B ) as an etch barrier, thereby forming a second hard mask pattern 21 A.
  • the second hard mask pattern 21 A is patterned to be a line type in the same direction as the first photoresist pattern 24 , i.e., in the first direction.
  • the second hard mask pattern 21 A it is preferable to remove the first photoresist pattern 24 , the second mask layer 23 and the first mask layer 22 (shown in FIGS. 3A and 3B ).
  • a dry strip process may be performed to remove the remaining photoresist pattern and hard mask layer after forming the second hard mask pattern 21 A.
  • the dry strip process may be performed using oxygen plasma.
  • a third hard mask layer 25 is formed over the first hard mask layer 20 including the second hard mask pattern 21 A.
  • the third hard mask layer 25 may have a selective etch ratio to the second hard mask pattern 21 A and the first hard mask layer 20 .
  • the third hard mask layer 25 may be formed of an oxide layer.
  • the third hard mask layer 25 has a step coverage to bury a space between adjacent ones of the second hard mask pattern 21 A.
  • the third hard mask layer 25 may be formed by Atomic Layer Deposition (ALD) or a Chemical Mechanical Deposition (CMD) using a furnace.
  • the third hard mask layer 25 has a minimum thickness to bury all the spaces between the adjacent ones of the second hard mask pattern 21 A to not protrude greatly over the second hard mask pattern 21 A in height.
  • a second photoresist pattern 26 is formed over the third hard mask layer 25 .
  • a tilting photolithography is performed to make the second photoresist pattern 26 to have a tilt angle symmetrical to that of the second hard mask pattern 21 A based on a target shape of the hole pattern.
  • the target shape of the hole pattern is a circle shape
  • the second photoresist pattern 26 may be formed to have a tilt angle of approximately ⁇ 45 degree while the second hard mask pattern 21 A has a tilt angle of approximately 45 degree.
  • the second photoresist pattern 26 is patterned to have a line type in a second direction crossing the first direction of the second hard mask pattern 21 A. According to an exemplary embodiment of the present invention, since the third hard mask layer 25 is formed to bury the space between the adjacent ones of the second hard mask pattern 21 A, a height difference is alleviated during forming the second photoresist pattern 26 .
  • a stacked layer of a multi-function hard mask (MFHM) layer and one of an amorphous carbon layer and a Spin-on Coating (SoC) layer may be formed over the third hard mask layer 25 to secure an etch margin.
  • MFHM multi-function hard mask
  • SoC Spin-on Coating
  • the third hard mask layer 25 is etched by using the second photoresist pattern 26 as an etch barrier (shown in FIGS. 6A and 6B ), thereby forming a third hard mask pattern 25 A.
  • the etch process is performed by a self-aligned contact (SAC) etch process in order to minimize loss of the second hard mask pattern 21 A.
  • SAC self-aligned contact
  • CxFy-based gas is used to etch the oxide layer, where x and y are positive integers and y divided by x is smaller than or equal to three.
  • the CxFy-based gas may include C 4 F 6 or C 4 F 8 gas, and a mixed gas including an oxygen (O 2 ) gas in addition to the CxFy-based gas may be used to etch the oxide layer.
  • the second photoresist pattern 26 (shown in FIGS. 6A and 6B ) is removed.
  • a dry strip process may be performed to remove the second photoresist pattern 26 , and the dry strip process may be performed using oxygen (O 2 ) plasma.
  • oxygen (O 2 ) plasma In a case where the stacked layer of the MFHM layer and one of the amorphous carbon layer and the SoC layer is formed before forming the second photoresist pattern 26 , all the stacked layer may be removed by using oxygen (O 2 ) plasma.
  • the hole pattern is defined by the second hard mask pattern 21 A formed to be a line type in the first direction and the third hard mask pattern 25 A formed to be a line type in the second direction.
  • the first hard mask layer 20 is etched using the second hard mask pattern 21 A and the third hard mask pattern 25 A as etch barriers (shown in FIGS. 7A and 7B ), thereby forming a first hard mask pattern 20 A.
  • the etch process may be performed using a mixed gas of hydrogen bromide (HBr) and chlorine (Cl 2 ) in addition to a mixed gas of a nitrogen (N 2 ) gas and an oxygen (O 2 ) gas.
  • the etch process to form the first hard mask pattern 20 A uses the second hard mask pattern 21 A of a nitride layer and the third hard mask pattern 25 A of an oxide layer as the etch barriers, a wiggling occurring during an etch process using a photoresist pattern may be prevented/reduced. Furthermore, since etch characteristics of the nitride layer and the oxide layer during the etch process of the first hard mask layer 20 of a poly silicon are similar, an asymmetry to the first hard mask pattern 20 A may be minimized.
  • the first hard mask layer is formed of the poly silicon
  • the second hard mask layer is formed of the nitride layer
  • the third hard mask layer is formed of the oxide layer
  • the second hard mask layer when an amorphous carbon is used as the first hard mask layer, the second hard mask layer may be selected from a group consisting of a nitride layer, a poly silicon layer and an oxide layer.
  • the third hard mask layer when one of the nitride layer and the oxide layer is used as the second hard mask layer, the third hard mask layer may be formed of a poly silicon layer.
  • the third hard mask layer is formed of one of the nitride layer and the oxide layer.
  • a method for fabricating a hole pattern of the present invention can prevent/reduce a wiggling since a photoresist layer is not used as a hard mask layer for forming the hole pattern. Furthermore, it is possible to finely fabricate a hole pattern using a double patterning process.

Abstract

A method for fabricating a hole pattern includes forming a first hard mask layer over an etch target layer, forming a second hard mask pattern over the first hard mask layer, which are patterned to be a line type in a first direction and have a selective etch ratio to the first hard mask layer, forming a third hard mask layer over the first hard mask layer to bury a space between adjacent ones of the second hard mask pattern, forming a photoresist pattern over the third hard mask layer, which is patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern, removing the photoresist pattern, and etching the first hard mask layer using the second and third hard mask patterns.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
The present invention claims priority of Korean patent application number 10-2009-0133388, filed on Dec. 29, 2009, the disclosure of which is incorporated by reference herein in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a hole pattern using a double patterning process.
In a fabricating process for a DRAM smaller than a 50 nm process DRAM, it is difficult to fabricate a hole pattern due to limitations on a resolution of a photolithography apparatus. In such a fabrication of a hole pattern, a double patterning technology is used to form a hole. The double patterning technology forms a hole by forming a line in a crossing direction, where such technology is adapted for patterning rather than creating holes.
Recently, in a case where a low-temperature carbon is used as a hard mask, a dual hard mask of a Plasma Enhanced Tetra Ethyl Ortho Silicate (PETEOS) oxide layer and a silicon oxide nitride layer is used for patterning. At this time, the silicon oxide nitride layer, which is an upper layer of the dual hard mask, is etched first, and the PETEOS oxide layer, which is a lower layer of the dual hard mask, is etched using the etched silicon oxide nitride layer and a photoresist pattern as an etch barrier.
FIGS. 1A to 1D are perspective views illustrating a conventional method for forming a hole pattern.
Referring to FIG. 1A, an amorphous carbon layer 12, a PETEOS oxide layer 13, a silicon oxide nitride layer 14, and an anti-reflective coating (ARC) layer 15 are sequentially formed over an etch-target layer 11. The amorphous carbon layer 12 is used as a hard mask to etch the etch-target layer 11, the PETEOS oxide layer 13 is used as a basic hard mask during a double patterning process, and the silicon oxide nitride layer 14 is used as a hard mask to etch the PETEOS oxide layer 13.
A first photoresist pattern 16 is formed over the ARC layer 15. The first photoresist pattern 16 is formed as a line type in a first direction.
Subsequently, the ARC layer 15 and the silicon oxide nitride layer 14 are etched using the first photoresist pattern 16 as an etch barrier. Since the first photoresist pattern 16 is the line type, the ARC layer 15 and the silicon oxide nitride layer 14 are also formed as a line type in the first direction.
Referring to FIG. 1B, a silicon oxide nitride pattern 14A is formed by removing the first photoresist pattern 16 and the ARC layer 15 (shown in FIG. 1A).
Referring to FIG. 1C, a second photoresist pattern 17 is formed over a resultant structure including the silicon oxide nitride pattern 14A. The second photoresist pattern 17 may be formed as a line type in a second direction which is perpendicular to the first direction. Accordingly, a hole pattern is defined by the second photoresist pattern 17 and the silicon oxide nitride pattern 14A.
Referring to FIG. 1D, the PETEOS oxide layer 13 is etched using the second photoresist pattern 17 and the silicon oxide nitride pattern 14A as an etch barrier (shown in FIG. 1C), thereby forming a PETEOS oxide pattern 13A. The PETEOS oxide pattern 13A defines the hole pattern.
As described above, in the conventional method for forming the double hole pattern, the hole pattern is defined by the second photoresist pattern 17 and the silicon oxide nitride pattern 14A. However, since the conventional method uses different masks subject to the same etch conditions, etch characteristics may differ between the different masks, e.g., a Critical Dimension (CD) bias. Furthermore, when the PETEOS oxide layer is etched using the second photoresist pattern, a wiggling can occur due to characteristics of an etch process for an oxide layer, which has a high ion energy.
FIG. 2 is a picture showing a wiggling of the conventional method for forming the hole pattern.
Referring to FIG. 2, the wiggling 100 occurs in the second photoresist pattern used as an etch barrier during etching the PETEOS oxide layer.
SUMMARY OF THE INVENTION
Embodiments of the present invention are directed to providing a method for fabricating a hole pattern, which can prevent a wiggling due to etch barriers having etch characteristics different from each other during a double patterning process.
In accordance with an aspect of the present invention, there is provided a method for fabricating a hole pattern, including: forming a first hard mask layer over an etch target layer; forming a second hard mask pattern over the first hard mask layer, the second hard mask pattern being patterned to be a line type in a first direction and having a selective etch ratio to the first hard mask layer; forming a third hard mask layer over the first hard mask layer including the second hard mask pattern to bury a space between adjacent ones of the second hard mask pattern; forming a photoresist pattern over the third hard mask layer, the photoresist pattern being patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern; removing the photoresist pattern; and etching the first hard mask layer using the second and third hard mask patterns.
The first hard mask layer may comprise a poly silicon layer, the second hard mask pattern may comprise a nitride layer or a silicon nitride oxide layer, and the third hard mask layer may comprise an oxide layer.
The third hard mask layer may comprise a step coverage to bury the space between the adjacent ones of the second hard mask pattern, thereby having a minimum thickness to bury all the space between the adjacent ones of the second hard mask pattern and to not protrude greatly over the second hard mask pattern in height.
The third hard mask layer may be formed by Atomic Layer Deposition (ALD) or a Chemical Mechanical Deposition (CMD) using a furnace.
The first direction may be symmetrical to the second direction. The first direction may have a tilt angle of approximately 45 degree while the second direction may have a tilt angle of approximately −45 degree. The first direction may have a tilt angle of approximately 45 degree to approximately 60 degree.
The etching of the third hard mask layer may be performed by a self-aligned contact (SAC) etch process by using a selective etch ratio of a nitride layer and an oxide layer, and may use a CxFy-based gas, where x and y are positive integers and y divided by x is smaller than or equal to three. The CxFy-based gas may comprise C4F6 or C4F8 gas. The etching of the third hard mask may be performed by using an oxygen (O2) gas in addition to the CxFy-based gas.
The method may further comprise forming a stacked layer of a multi-function hard mask (MFHM) layer and one of an amorphous carbon layer and a Spin-on Coating (SoC) layer over the third hard mask layer. The removing of the photoresist pattern may be performed by a dry strip process using oxygen (O2) plasma. The stacked layer may be removed by using oxygen (O2) plasma during removing the photoresist pattern.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A to 1D are perspective views illustrating a conventional method for forming a hole pattern.
FIG. 2 is a picture showing a wiggling of the conventional method for forming the hole pattern.
FIGS. 3A to 8B are cross-sectional views and plane views illustrating a method for fabricating a hole pattern in accordance with an embodiment of the present invention.
 DESCRIPTION OF SPECIFIC EMBODIMENTS
Other objects and advantages of the present invention can be understood by the following description, and become apparent with reference to the embodiments of the present invention.
FIGS. 3A to 8B are cross-sectional views and plane views illustrating a method for fabricating a hole pattern in accordance with an embodiment of the present invention. Each of FIGS. 3A, 4A, 5A, 6A, 7A and 8A is a cross-sectional view illustrating the method for fabricating the hole pattern while each of FIGS. 3B, 4B, 5B, 6B, 7B and 8B is a plane view illustrating the method for fabricating the hole pattern. For conciseness, each cross-sectional view and plane view of FIGS. 3A to 8B are explained in pairs.
Referring to FIGS. 3A and 3B, a first hard mask layer 20 is formed over an etch target layer (not shown). The first hard mask layer 20 may be formed of a poly silicon to etch the etch target layer.
Subsequently, a second hard mask layer 21, a first mask layer 22, and a second mask layer 23 are sequentially formed over the first hard mask layer 20. The second hard mask layer 21 may be used to etch the first hard mask layer 20 and have a selective etch ratio to the first hard mask layer 20 (for example, a ratio of etch rates). When the first hard mask layer 20 is formed of a poly silicon, the second hard mask layer 21 may be formed of a nitride layer or a silicon nitride oxide layer. According to an embodiment, the nitride layer includes a silicon nitride.
The first mask layer 22 may be used to etch the second hard mask layer 21 and have a selective ratio to the first hard mask layer 20 as well as the second hard mask layer 21. When the first hard mask layer 20 is formed of a poly silicon and the second hard mask layer 21 is formed of a nitride layer, the first mask layer 22 may be formed of an amorphous carbon. The second mask layer 23 is used to etch the first mask layer 22. The second mask layer 23 may be formed of a silicon oxide nitride (SiON) layer.
Subsequently, a first photoresist pattern 24 is formed over the second mask layer 23. The first photoresist pattern 24 is patterned to have a line type in a first direction. Before forming the first photoresist pattern 24, an anti-reflective coating (ARC) layer (not shown) may be formed over the second mask layer 23.
The first photoresist pattern 24 has a tilt angle which is determined based on a target shape of the hole pattern. Preferably, in a case where the target shape of the hole pattern is a circle shape, the first photoresist pattern 24 may be formed to have a tilt angle of approximately 45 degree. In case where the target shape of the hole pattern is an oval shape, the first photoresist pattern 24 may be formed to have a tilt angle ranging from approximately 45 degree to approximately 60 degree.
Subsequently, the second mask layer 23 and the first mask layer 22 are etched using the first photoresist pattern 24 as an etch barrier. At this time, when the second mask layer 23 is formed of a silicon oxide nitride (SiON) layer, the etch process is performed using Tetrafluoromethane (CF4) gas, or a mixed gas of CF4 gas and Fluoroform (CHF3) gas.
Referring to FIGS. 4A and 4B, the second hard mask layer 21 (shown in FIGS. 3A and 3B) is etched by using the first mask layer 22 (shown in FIGS. 3A and 3B) as an etch barrier, thereby forming a second hard mask pattern 21A. The second hard mask pattern 21A is patterned to be a line type in the same direction as the first photoresist pattern 24, i.e., in the first direction.
When the second hard mask pattern 21A is formed, it is preferable to remove the first photoresist pattern 24, the second mask layer 23 and the first mask layer 22 (shown in FIGS. 3A and 3B). For this, a dry strip process may be performed to remove the remaining photoresist pattern and hard mask layer after forming the second hard mask pattern 21A. The dry strip process may be performed using oxygen plasma.
Referring to FIGS. 5A and 5B, a third hard mask layer 25 is formed over the first hard mask layer 20 including the second hard mask pattern 21A. The third hard mask layer 25 may have a selective etch ratio to the second hard mask pattern 21A and the first hard mask layer 20. When the first hard mask layer 20 is formed of a poly silicon layer and the second hard mask pattern 21A is formed of a nitride layer, the third hard mask layer 25 may be formed of an oxide layer.
In particular, the third hard mask layer 25 has a step coverage to bury a space between adjacent ones of the second hard mask pattern 21A. The third hard mask layer 25 may be formed by Atomic Layer Deposition (ALD) or a Chemical Mechanical Deposition (CMD) using a furnace. The third hard mask layer 25 has a minimum thickness to bury all the spaces between the adjacent ones of the second hard mask pattern 21A to not protrude greatly over the second hard mask pattern 21A in height.
Referring to FIGS. 6A and 6B, a second photoresist pattern 26 is formed over the third hard mask layer 25. At this time, a tilting photolithography is performed to make the second photoresist pattern 26 to have a tilt angle symmetrical to that of the second hard mask pattern 21A based on a target shape of the hole pattern. Preferably, in a case where the target shape of the hole pattern is a circle shape, the second photoresist pattern 26 may be formed to have a tilt angle of approximately −45 degree while the second hard mask pattern 21A has a tilt angle of approximately 45 degree.
Accordingly, the second photoresist pattern 26 is patterned to have a line type in a second direction crossing the first direction of the second hard mask pattern 21A. According to an exemplary embodiment of the present invention, since the third hard mask layer 25 is formed to bury the space between the adjacent ones of the second hard mask pattern 21A, a height difference is alleviated during forming the second photoresist pattern 26.
Before forming the second photoresist pattern 26, a stacked layer of a multi-function hard mask (MFHM) layer and one of an amorphous carbon layer and a Spin-on Coating (SoC) layer may be formed over the third hard mask layer 25 to secure an etch margin.
Referring to FIGS. 7A and 7B, the third hard mask layer 25 is etched by using the second photoresist pattern 26 as an etch barrier (shown in FIGS. 6A and 6B), thereby forming a third hard mask pattern 25A. The etch process is performed by a self-aligned contact (SAC) etch process in order to minimize loss of the second hard mask pattern 21A.
At this time, by using a selective etch ratio of a nitride layer and an oxide layer, only the oxide layer is selectively etched. For this, CxFy-based gas is used to etch the oxide layer, where x and y are positive integers and y divided by x is smaller than or equal to three. The CxFy-based gas may include C4F6 or C4F8 gas, and a mixed gas including an oxygen (O2) gas in addition to the CxFy-based gas may be used to etch the oxide layer.
Subsequently, the second photoresist pattern 26 (shown in FIGS. 6A and 6B) is removed. A dry strip process may be performed to remove the second photoresist pattern 26, and the dry strip process may be performed using oxygen (O2) plasma. In a case where the stacked layer of the MFHM layer and one of the amorphous carbon layer and the SoC layer is formed before forming the second photoresist pattern 26, all the stacked layer may be removed by using oxygen (O2) plasma.
Accordingly, the hole pattern is defined by the second hard mask pattern 21A formed to be a line type in the first direction and the third hard mask pattern 25A formed to be a line type in the second direction.
Referring to FIGS. 8A and 8B, the first hard mask layer 20 is etched using the second hard mask pattern 21A and the third hard mask pattern 25A as etch barriers (shown in FIGS. 7A and 7B), thereby forming a first hard mask pattern 20A. When the first hard mask layer 20 is formed of a poly silicon, the etch process may be performed using a mixed gas of hydrogen bromide (HBr) and chlorine (Cl2) in addition to a mixed gas of a nitrogen (N2) gas and an oxygen (O2) gas.
According to an exemplary embodiment of the present invention, since the etch process to form the first hard mask pattern 20A uses the second hard mask pattern 21A of a nitride layer and the third hard mask pattern 25A of an oxide layer as the etch barriers, a wiggling occurring during an etch process using a photoresist pattern may be prevented/reduced. Furthermore, since etch characteristics of the nitride layer and the oxide layer during the etch process of the first hard mask layer 20 of a poly silicon are similar, an asymmetry to the first hard mask pattern 20A may be minimized.
While, in the exemplary embodiment of the present invention, the first hard mask layer is formed of the poly silicon, the second hard mask layer is formed of the nitride layer, and the third hard mask layer is formed of the oxide layer, materials having a selective etch ratio can be selectively used for the first to third hard mask layers without limitations on materials of the first to third hard mask layers.
In another embodiment, when an amorphous carbon is used as the first hard mask layer, the second hard mask layer may be selected from a group consisting of a nitride layer, a poly silicon layer and an oxide layer. At this time, when one of the nitride layer and the oxide layer is used as the second hard mask layer, the third hard mask layer may be formed of a poly silicon layer. On the contrary, when a poly silicon layer is used as the second hard mask layer, the third hard mask layer is formed of one of the nitride layer and the oxide layer.
As described above, a method for fabricating a hole pattern of the present invention can prevent/reduce a wiggling since a photoresist layer is not used as a hard mask layer for forming the hole pattern. Furthermore, it is possible to finely fabricate a hole pattern using a double patterning process.
While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims (17)

1. A method for fabricating a hole pattern, comprising:
forming a first hard mask layer over an etch target layer;
forming a second hard mask pattern over the first hard mask layer, the second hard mask pattern being patterned to be a line type in a first direction and having a selective etch ratio to the first hard mask layer;
forming a third hard mask layer over a top surface of the first hard mask layer including the second hard mask pattern to bury a space between adjacent ones of the second hard mask pattern;
forming a photoresist pattern over the third hard mask layer, the photoresist pattern being patterned to be a line type in a second direction;
etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern;
removing the photoresist pattern; and
etching the first hard mask layer using the second and third hard mask patterns.
2. The method of claim 1, wherein the first hard mask layer comprises a poly silicon layer.
3. The method of claim 1, wherein the second hard mask pattern comprises a nitride layer or a silicon nitride oxide layer.
4. The method of claim 1, wherein the third hard mask layer comprises an oxide layer.
5. The method of claim 1, wherein the third hard mask layer comprises a step coverage to bury the space between the adjacent ones of the second hard mask pattern.
6. The method of claim 1, wherein the third hard mask layer has a minimum thickness to bury all the space between the adjacent ones of the second hard mask pattern and to not protrude greatly over the second hard mask pattern in height.
7. The method of claim 1, wherein the third hard mask layer is formed by Atomic Layer Deposition (ALD) or a Chemical Mechanical Deposition (CMD) using a furnace.
8. The method of claim 1, wherein the first direction is symmetrical to the second direction.
9. The method of claim 8, wherein the first direction has a tilt angle of approximately 45 degree while the second direction has a tilt angle of approximately −45 degree.
10. The method of claim 8, wherein the first direction has a tilt angle of approximately 45 degree to approximately 60 degree.
11. The method of claim 1, wherein the etching of the third hard mask layer is performed by a self-aligned contact (SAC) etch process by using a selective etch ratio of a nitride layer and an oxide layer.
12. The method of claim 11, wherein the etching of the third hard mask layer is performed by using a CxFy-based gas, where x and y are positive integers and y divided by x is smaller than or equal to three.
13. The method of claim 12, wherein the CxFy-based gas comprises C4F6 or C4F8 gas.
14. The method of claim 12, wherein the etching of the third hard is mask layer is performed by using an oxygen (O2) gas in addition to the CxFy-based gas.
15. The method of claim 1, further comprising:
forming a stacked layer of a multi-function hard mask (MFHM) layer and one of an amorphous carbon layer and a Spin-on Coating (SoC) layer over the third hard mask layer.
16. The method of claim 15, wherein the removing of the photoresist pattern is performed by a dry strip process using oxygen (O2) plasma.
17. The method of claim 16, wherein the stacked layer is removed by using oxygen (O2) plasma during removing the photoresist pattern.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8658532B2 (en) 2006-03-22 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method and material for forming a double exposure lithography pattern
US9099403B2 (en) 2012-12-06 2015-08-04 Samsung Electronics Co., Ltd. Methods for forming a semiconductor device including fine patterns
US9219007B2 (en) 2013-06-10 2015-12-22 International Business Machines Corporation Double self aligned via patterning
US10176289B2 (en) 2017-02-24 2019-01-08 United Microelectronics Corp. Method for decomposing semiconductor layout pattern

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130107628A (en) 2012-03-22 2013-10-02 삼성디스플레이 주식회사 Method of manufacturing trench, metal wire, and thin film transistor array panel
US8647981B1 (en) * 2012-08-31 2014-02-11 Micron Technology, Inc. Methods of forming patterns, and methods of forming integrated circuitry
JP6097652B2 (en) 2013-07-31 2017-03-15 富士フイルム株式会社 PATTERN FORMING METHOD, PATTERN, ETCHING METHOD USING THEM, AND ELECTRONIC DEVICE MANUFACTURING METHOD
KR102018215B1 (en) * 2017-11-28 2019-09-04 한국세라믹기술원 Microscale and nanoscale pattern and that method for controlling the shape
CN109870876B (en) * 2017-12-05 2022-05-10 长鑫存储技术有限公司 Alignment pattern manufacturing method
US10181401B1 (en) * 2018-01-08 2019-01-15 Nanya Technology Corporation Method for manufacturing a semiconductor device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060231900A1 (en) * 2005-04-19 2006-10-19 Ji-Young Lee Semiconductor device having fine contacts and method of fabricating the same
US20080124931A1 (en) * 2006-03-06 2008-05-29 Samsung Electronics Co., Ltd. Method for forming fine patterns of a semiconductor device using a double patterning process
US20080253160A1 (en) * 2007-04-13 2008-10-16 Qimonda Ag Integrated circuit having a memory cell array and method of forming an integrated circuit
US20090169832A1 (en) * 2007-12-28 2009-07-02 Thomas John Aton Simplified double mask patterning system
US20100048024A1 (en) * 2008-08-25 2010-02-25 Elpida Memory, Inc. Manufacturing method of semiconductor device
US20100130011A1 (en) * 2008-11-26 2010-05-27 Tokyo Electron Limited Semiconductor device fabrication method
US7727899B2 (en) * 2006-04-06 2010-06-01 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device and semiconductor storage device including fine contact holes

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100858877B1 (en) 2007-08-13 2008-09-17 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060231900A1 (en) * 2005-04-19 2006-10-19 Ji-Young Lee Semiconductor device having fine contacts and method of fabricating the same
US20080124931A1 (en) * 2006-03-06 2008-05-29 Samsung Electronics Co., Ltd. Method for forming fine patterns of a semiconductor device using a double patterning process
US7727899B2 (en) * 2006-04-06 2010-06-01 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device and semiconductor storage device including fine contact holes
US20080253160A1 (en) * 2007-04-13 2008-10-16 Qimonda Ag Integrated circuit having a memory cell array and method of forming an integrated circuit
US20090169832A1 (en) * 2007-12-28 2009-07-02 Thomas John Aton Simplified double mask patterning system
US20100048024A1 (en) * 2008-08-25 2010-02-25 Elpida Memory, Inc. Manufacturing method of semiconductor device
US20100130011A1 (en) * 2008-11-26 2010-05-27 Tokyo Electron Limited Semiconductor device fabrication method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8658532B2 (en) 2006-03-22 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method and material for forming a double exposure lithography pattern
US9099403B2 (en) 2012-12-06 2015-08-04 Samsung Electronics Co., Ltd. Methods for forming a semiconductor device including fine patterns
US9219007B2 (en) 2013-06-10 2015-12-22 International Business Machines Corporation Double self aligned via patterning
US9257334B2 (en) 2013-06-10 2016-02-09 International Business Machines Corporation Double self-aligned via patterning
US9330965B2 (en) 2013-06-10 2016-05-03 International Business Machines Corporation Double self aligned via patterning
US10176289B2 (en) 2017-02-24 2019-01-08 United Microelectronics Corp. Method for decomposing semiconductor layout pattern

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