US8245112B2 - Flash memory organization - Google Patents
Flash memory organization Download PDFInfo
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- US8245112B2 US8245112B2 US12/478,013 US47801309A US8245112B2 US 8245112 B2 US8245112 B2 US 8245112B2 US 47801309 A US47801309 A US 47801309A US 8245112 B2 US8245112 B2 US 8245112B2
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- 230000015654 memory Effects 0.000 title claims abstract description 63
- 230000008520 organization Effects 0.000 title description 6
- 238000012937 correction Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 28
- 230000008569 process Effects 0.000 description 14
- 238000004891 communication Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000013500 data storage Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000013519 translation Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/40—Specific encoding of data in memory or cache
- G06F2212/403—Error protection encoding, e.g. using parity or ECC codes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7207—Details relating to flash memory management management of metadata or control data
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
Claims (21)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/478,013 US8245112B2 (en) | 2009-06-04 | 2009-06-04 | Flash memory organization |
US12/952,202 US9063561B2 (en) | 2009-05-06 | 2010-11-23 | Direct memory access for loopback transfers in a media controller architecture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/478,013 US8245112B2 (en) | 2009-06-04 | 2009-06-04 | Flash memory organization |
Publications (2)
Publication Number | Publication Date |
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US20100313100A1 US20100313100A1 (en) | 2010-12-09 |
US8245112B2 true US8245112B2 (en) | 2012-08-14 |
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Family Applications (1)
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US12/478,013 Active 2031-02-13 US8245112B2 (en) | 2009-05-06 | 2009-06-04 | Flash memory organization |
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US (1) | US8245112B2 (en) |
Cited By (26)
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US8694849B1 (en) | 2011-12-19 | 2014-04-08 | Pmc-Sierra Us, Inc. | Shuffler error correction code system and method |
US8694855B1 (en) * | 2011-11-02 | 2014-04-08 | Pmc-Sierra Us, Inc. | Error correction code technique for improving read stress endurance |
US8935598B1 (en) | 2013-03-12 | 2015-01-13 | Pmc-Sierra Us, Inc. | System and method for adaptive check node approximation in LDPC decoding |
US8984376B1 (en) | 2013-03-14 | 2015-03-17 | Pmc-Sierra Us, Inc. | System and method for avoiding error mechanisms in layered iterative decoding |
US8984365B1 (en) | 2013-03-14 | 2015-03-17 | Pmc-Sierra Us, Inc. | System and method for reduced memory storage in LDPC decoding |
US8990661B1 (en) | 2013-03-05 | 2015-03-24 | Pmc-Sierra Us, Inc. | Layer specific attenuation factor LDPC decoder |
US8995302B1 (en) | 2013-01-16 | 2015-03-31 | Pmc-Sierra Us, Inc. | Method and apparatus for translated routing in an interconnect switch |
US9092353B1 (en) | 2013-01-29 | 2015-07-28 | Pmc-Sierra Us, Inc. | Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system |
US9128858B1 (en) | 2013-01-29 | 2015-09-08 | Pmc-Sierra Us, Inc. | Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values |
US9218281B2 (en) | 2012-05-04 | 2015-12-22 | Seagate Technology Llc | Maintaining ordering via a multi-level map of a solid-state media |
US9235467B2 (en) | 2013-03-15 | 2016-01-12 | Pmc-Sierra Us, Inc. | System and method with reference voltage partitioning for low density parity check decoding |
US9397701B1 (en) | 2013-03-11 | 2016-07-19 | Microsemi Storage Solutions (Us), Inc. | System and method for lifetime specific LDPC decoding |
US9417804B2 (en) | 2014-07-07 | 2016-08-16 | Microsemi Storage Solutions (Us), Inc. | System and method for memory block pool wear leveling |
US9450610B1 (en) | 2013-03-15 | 2016-09-20 | Microsemi Storage Solutions (Us), Inc. | High quality log likelihood ratios determined using two-index look-up table |
US9454414B2 (en) | 2013-03-15 | 2016-09-27 | Microsemi Storage Solutions (Us), Inc. | System and method for accumulating soft information in LDPC decoding |
US9590656B2 (en) | 2013-03-15 | 2017-03-07 | Microsemi Storage Solutions (Us), Inc. | System and method for higher quality log likelihood ratios in LDPC decoding |
US9799405B1 (en) | 2015-07-29 | 2017-10-24 | Ip Gem Group, Llc | Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction |
US9813080B1 (en) | 2013-03-05 | 2017-11-07 | Microsemi Solutions (U.S.), Inc. | Layer specific LDPC decoder |
US9886214B2 (en) | 2015-12-11 | 2018-02-06 | Ip Gem Group, Llc | Nonvolatile memory system with erase suspend circuit and method for erase suspend management |
US9892794B2 (en) | 2016-01-04 | 2018-02-13 | Ip Gem Group, Llc | Method and apparatus with program suspend using test mode |
US9899092B2 (en) | 2016-01-27 | 2018-02-20 | Ip Gem Group, Llc | Nonvolatile memory system with program step manager and method for program step management |
US10157677B2 (en) | 2016-07-28 | 2018-12-18 | Ip Gem Group, Llc | Background reference positioning and local reference positioning using threshold voltage shift read |
US10230396B1 (en) | 2013-03-05 | 2019-03-12 | Microsemi Solutions (Us), Inc. | Method and apparatus for layer-specific LDPC decoding |
US10236915B2 (en) | 2016-07-29 | 2019-03-19 | Microsemi Solutions (U.S.), Inc. | Variable T BCH encoding |
US10291263B2 (en) | 2016-07-28 | 2019-05-14 | Ip Gem Group, Llc | Auto-learning log likelihood ratio |
US10332613B1 (en) | 2015-05-18 | 2019-06-25 | Microsemi Solutions (Us), Inc. | Nonvolatile memory system with retention monitor |
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US20140089561A1 (en) * | 2012-09-26 | 2014-03-27 | Kiran Pangal | Techniques Associated with Protecting System Critical Data Written to Non-Volatile Memory |
US10417090B2 (en) | 2013-12-23 | 2019-09-17 | Cnex Labs, Inc. | Computing system with data protection mechanism and method of operation thereof |
WO2015134262A1 (en) * | 2014-03-01 | 2015-09-11 | CNEXLABS, Inc. | Computing system with data protection mechanism and method of operation thereof |
FR3089317A1 (en) * | 2018-12-03 | 2020-06-05 | Stmicroelectronics (Rousset) Sas | Method for managing the memory space of a memory device and corresponding system |
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