US8300754B2 - Clock and data recovery with a data aligner - Google Patents

Clock and data recovery with a data aligner Download PDF

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US8300754B2
US8300754B2 US12/510,199 US51019909A US8300754B2 US 8300754 B2 US8300754 B2 US 8300754B2 US 51019909 A US51019909 A US 51019909A US 8300754 B2 US8300754 B2 US 8300754B2
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recovered
data
clock
input
stream
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US20100104057A1 (en
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Nikola Nedovic
Nestor Tzartzanis
William W. Walker
Hirotaka Tamura
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

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  • the present disclosure relates generally to clock and data recovery (CDR).
  • a phase-locked loop (PLL)-based CDR circuit is a conventional type of CDR circuit.
  • a phase detector compares the phase between input data bits from a serial input data stream and a clock signal from a voltage-controlled oscillator (VCO). In response to the phase difference between the input data and the clock, the phase detector generates signals UP and DN.
  • a charge pump drives a current to or from a loop filter according to the UP and DN signals.
  • the loop filter generates a control voltage V CTRL for the VCO based on the UP and DN signals.
  • the loop acts as a feedback control system that tracks the phase of input data stream with the phase of the clock that the loop generates.
  • the dynamics of the loop are generally determined by the open loop gain and the location of open loop zeroes and poles (predominantly in the loop filter).
  • a problem in systems employing conventional CDR architectures utilizing two CDRs for use in demodulated differential quadrature phase shift keying (DQPSK) modulated data streams is that they are suitable only for full-rate CDRs without data demultiplexing, when the frequencies of the clocks within each CDR are the same as the data rate of the input data bit streams. Otherwise, there exists an uncertainty of relative clock and data phases from the two CDRs and the circuit may operate erroneously.
  • many practical CDRs in high speed optical communications use either half-rate or quarter-rate architectures; that is, each CDR may use a clock whose frequency is half (half-rate), a quarter (quarter-rate), or a smaller fraction of the rate of input data stream, in order to cope with high input data rates.
  • FIG. 1 illustrates an example system employing a CDR architecture that includes two independent CDRs and a data aligner.
  • FIG. 2 illustrates an example DQPSK modulation scheme.
  • FIG. 3 illustrates example phase relationships among recovered clocks and data streams.
  • FIG. 4 illustrates an example data aligner
  • FIG. 5 illustrates another example of a data aligner.
  • FIG. 6 illustrates another example of a data aligner.
  • FIG. 7 illustrates an example method for CDR with a data aligner.
  • Particular embodiments relate to an electronic circuit for clock and data recovery (CDR) for a two or more bits per symbol serial communication system. More particularly, the present disclosure provides examples of a CDR architecture that takes two input data bit streams and produces one or more output data bit streams in which the bits from the two input data bit streams are interleaved. In particular embodiments, the two input bit streams have the same data rate and limited relative phase (e.g., within limits of ⁇ UI/2).
  • An example CDR architecture may include two independent CDRs, one for each of two input data streams, as well as a data aligner, which combines the data outputs from the two CDRs into one or more output data streams using the clock recovered by one of the CDRs.
  • one stream may refer to one wire, and vice versa, where appropriate).
  • Particular embodiments further relate to the use of CDRs having less than full-rate architecture. More specifically, particular embodiments utilize CDRs that employ half-rate or quarter-rate architecture. Generally, particular embodiments can be used for any two-input CDR application.
  • particular embodiments relate to the use of a CDR architecture within a deserializer utilized in optical communication.
  • particular embodiments may be utilized in a DQPSK transponder.
  • alternative embodiments may be utilized in other specific applications and for non-optical communication (e.g., hard-wired communication using electrons), where appropriate.
  • Particular embodiments may be utilized in high speed communication systems (e.g., data rates greater than 10 Gb/s) and in even more particular embodiments, in communication systems having data rates at or exceeding 40 Gb/s.
  • Particular embodiments may be implemented with a complementary metal oxidesemiconductor (CMOS) architecture.
  • CMOS complementary metal oxidesemiconductor
  • Particular embodiments may also provide reduced power consumption.
  • FIG. 1 illustrates an example CDR architecture 100 .
  • CDR architecture 100 includes a first CDR circuit 102 and a second CDR circuit 104 each of which may include one or more modules or subcircuits.
  • CDR circuit 102 is configured to receive first input data bits from a first input data bit stream d in1 while CDR circuit 104 is configured to receive second input data bits from a second input data bit stream d in2 .
  • each of the first and second input data bit streams d in1 and d in2 is sampled from a symbol stream and each includes input data bits sampled at an input frequency.
  • each CDR is a half-rate 20 Gb/s CDR.
  • a single channel CDR block may consist of a 10 GHz quadrature VCO, four 10 Gb/s samplers, a 10 Gb/s synchronizer, a 4:8 10 Gb/s-to-5 Gb/s DEMUX, a clock divider that supplies 4-phase 5 GHz clock, a phase detector (PD), and charge pump (CP) that run at 5 Gb/s, a loop filter, and a frequency acquisition circuit.
  • the samplers operate at half data rate and produce four 10 Gb/s samples, each synchronized to the VCO phase used to clock the sampler.
  • the Synchronizer block may operate at 10 Gb/s and generally serves two purposes: to synchronize the 10 Gb/s samples to the common reference (VCO phase 0), and to generate static 10 Gb/s signals from the sampler outputs, which are invalid (reset) half of the cycle due to a particular implementation of the preceding sampler.
  • the clock frequency divider and the 10 Gb/s-to-5 Gb/s DEMUX generate the 8 ⁇ 5 Gb/s static CMOS bits from the 4 ⁇ 10 Gb/s CML bits from the Synchronizer.
  • the PD runs at 5 Gb/s, and generates up and dn signals for the CP, which drives the loop filter and generates the control voltage Vctrl to the VCO.
  • the symbol stream is a differential quadrature phase shift keying (DQPSK) modulated data stream.
  • DQPSK differential quadrature phase shift keying
  • the first input data bits from the first input data bit stream d in1 may be even-numbered bits from the symbol stream while the second input data bits from the second input data bit stream d in2 may be odd-numbered bits from the symbol stream.
  • DQPSK is a modulation scheme in which two bits at a time are grouped and used to phase-modulate an output.
  • 2 bits per symbol are encoded in the phases of light.
  • the modulation is differential, which means that the input symbol (two bits) corresponds not to a particular phase of the output, but to the change of the phase relative to the phase of the previous symbol.
  • FIG. 2 illustrates an example DQPSK modulation scheme.
  • symbol 00 causes zero change in the output phase
  • symbol 01 causes a phase change of ⁇ /2
  • symbol 11 causes a phase change of ⁇
  • symbol 10 causes a phase change of 3 ⁇ /2.
  • the demodulation may be made insensitive to a phase shift in the communication medium.
  • a DQPSK receiver demodulates the DQPSK symbol stream to obtain two bits per symbol, and thus two streams of binary data, d in1 and d in2 , which may then be amplified and sent to CDRs 102 and 04 , respectively.
  • the two input data streams d in1 and d in2 have the same data rate, but the exact phase relationship is unknown (within limits of ⁇ UI/2 where UI is the unit interval) due to mismatches in the paths from the demodulator to respective CDR 102 or 104 .
  • a proper clock and data recovery circuit should not only recover the clock and individual data, but also correctly recombine the two streams.
  • CDR 102 generates a first recovered clock clk 1 based on the first input data stream d in1 .
  • CDR 104 generates a second recovered clock clk 2 based on the second input data stream d in2 .
  • one or both of the recovered clocks clk 1 and clk 2 are then transmitted to a data aligner 106 , which may include one or more modules or subcircuits.
  • CDR 102 also retimes and demultiplexes the data bits from the first input data bit stream d in1 .
  • Demultiplexing is advantageous in particular embodiments utilized in high speed communication systems. By demultiplexing the input data bit stream d in1 , the data is easier to handle. Conventionally, it is difficult to design a circuit that can recover a full-rate clock at high speed.
  • a high speed data rate may be considered a data rate greater than or equal to 1 Gb/s, or greater than 10 Gb/s, or greater than 20 Gb/s, or greater than 40 Gb/s.
  • n is greater than or equal to 2 and the data bits in each first recovered data bit stream d rec1 are output from CDR 102 at a first demultiplexed frequency that is the same for each first recovered data bit stream d rec1 and that is less than the input frequency.
  • CDR 104 also retimes and demultiplexes the data bits from the second input data bit stream d in2 to generate m second recovered data bit streams d rec2 each output at a second demultiplexed frequency that is less than the input frequency.
  • the value of m is equal to the value of n and the first demultiplexed frequency equals the second demultiplexed frequency.
  • the value of m is assumed to equal the value of n and the first demultiplexed frequency is assumed to be equal to the second demultiplexed frequency (and thus FIG. 1 illustrates n second recovered streams d rec2 ).
  • each CDR operates independently of the other and demultiplexes the recovered data to 5 Gb/s.
  • the first and second recovered data bit streams d rec1 and d rec1 are then sent to data aligner 106 .
  • data aligner 106 operates off one, and only one, of the clocks, clk 1 or clk 2 , recovered from one of the input streams d in1 or d in2 , respectively, by corresponding CDR 102 or 104 .
  • data aligner 106 detects/determines a phase difference between the first and second recovered clocks c in1 and c lk2 .
  • Data aligner 106 may then retime and align the first recovered bits d rec1 [n-1:0] from the n first recovered data bit streams d rec1 with the second recovered bits d rec2 [n-1:0] from the n second recovered data bit streams d rec2 based at least in part on the value of n and the determined phase difference.
  • data aligner 106 then combines the first recovered bits d rec1 [n-1:0] from the n first recovered data bit streams d rec1 with the second recovered bits d rec1 [n-1:0] from the n second recovered data bit streams d rec2 to generate at least one or more output data bit streams.
  • data aligner 106 generates 2n output data bit streams d out [2n-1:0]. It should be appreciated that the foregoing may be performed on a continuous basis during operation of CDR architecture 100 .
  • demultiplexing makes the data in the input data bit streams easier to handle
  • demultiplexing also results in a new problem as evidenced in the following.
  • data aligner 106 only needs to synchronize the bits from the two recovered streams d rec1 and d rec2 recovered by CDRs 102 and 104 to the common chosen clock, clk 1 or clk 2 , and interleave these data bits from the two recovered streams to produce output streams d out [2n-1:0].
  • the recovered clocks, clk 1 and clk 2 may be either approximately in phase (case 1 , disregarding non-idealities for the moment), or approximately out of phase (case 2 , ⁇ 180° phase difference), as shown in FIG.
  • FIG. 3 which illustrates phase relationships among recovered clocks c lk1 and c lk2 and data streams d in1 , d in2 , d rec1 [0] (first first recovered data bit stream), d rec1 [1] (second first recovered data bit stream), d rec2 [0] (first second recovered data bit stream), and d rec2 [1] (second second recovered data bit stream).
  • the recovered bits from the first recovered data bit streams d rec1 from CDR 102 may be in phase or out of phase with the recovered bits from the second recovered data bit streams d rec2 from CDR 104 .
  • Either of the two cases (case 1 or case 2 ) may happen due to, by way of example, differences between the initial states of CDRs 102 and 104 , mismatches between the CDR components, or different input patterns at d in1 and d in2 .
  • LSB least significant bit
  • MSB most significant bit
  • data aligner 106 To correctly combine the recovered data streams d rec1 and d rec2 from CDRs 102 and 104 , data aligner 106 must detect which of the two cases (n cases in general) occurred. Data aligner 106 determines which of the n cases occurred or is occurring by detecting the phase difference between the recovered clocks clk 1 and clk 2 .
  • data aligner 106 inserts (into the output streams) a first bit of the first first recovered data bit stream d rec1 [0,0] followed by a first bit of the first second recovered data bit stream d rec2 [0,0] followed by a first bit of the second first recovered data bit stream d rec1 [1,0] followed by a first bit of the second second recovered data bit stream d rec2 [1,0], which would then be followed by a second bit of the first first recovered data bit stream d rec1 [0,1] followed by a second bit of the first second recovered data bit stream d rec2 [0,1] followed by a second bit of the second first recovered data bit stream d rec1 [1,1] followed by a second bit of the second first recovered data bit stream d rec1 [1,1] followed by a second bit of the second first recovered data bit stream d rec1 [1,1] followed by
  • data aligner 106 inserts (into the output streams) a first bit of the first first recovered data bit stream d rec1 [0,0] followed by a delayed first bit of the first second recovered data bit stream d rec2 [0,0] followed by a first bit of the second first recovered data bit stream d rec1 [1,0] followed by a first bit of the second second recovered data bit stream d rec2 [1,0], which would then be followed by a second bit of the first first recovered data bit stream d rec1 [0,1] followed by a delayed second bit of the first second recovered data bit stream d rec2 [0,1] followed by a second bit of the second first recovered data bit stream d rec1 [1,1] followed by a second bit of the second second recovered data bit stream d rec2 [1,1], and so on.
  • FIG. 4 illustrates a schematic of an example data aligner 106 .
  • Data aligner 106 includes a shifter 408 that generates delay recovered data from CDR 104 , a selector 410 , which in particular embodiments is a time-to-digital converter that converts the phase offset between the recovered clocks clk 1 and clk 2 to a digital code, and a multiplexer (MUX) 412 that selects the appropriate shift/delay combination of the input.
  • the output of MUX 412 in FIG. 4 is in phase with clk 2 , and thus it should be synchronized with clk 1 . Any suitable method for the required synchronization may be used. In particular embodiments, additional manipulation is performed on d rec2 [n-1:0] and d p [n-1:0] prior to multiplexing, such as demultiplexing with divided clk 1 or clk 2 .
  • Selector (e.g., time-to-digital converter) 410 may be implemented in various ways.
  • time-to-digital converter 410 may be implemented as a Vernier Delay Line (VDL) or a delay locked loop (DLL).
  • VDL Vernier Delay Line
  • DLL delay locked loop
  • Table 1 The conversion table assumed for FIG. 4 is shown in Table 1 provided below. In particular embodiments, the conversion table may be constructed differently than that shown in Table 1 as long as the one-to-one correspondence between the input phase difference and the selected data is preserved.
  • FIG. 5 illustrates another example data aligner.
  • the data aligner may be similar to data aligner 106 described with reference to FIG. 4 , except for the generation of the multiplexer select signal.
  • the output of time-to-digital converter 510 is brought to a low-pass filter 512 , which averages the decision on which data order is selected.
  • This structure is generally useful when the offset between the inputs to CDRs 102 and 104 , d in1 and d in2 respectively, is comparable to UI/2, such that the output of time-to-digital converter 510 can be corrupted by noise or circuit non-idealities.
  • low pass filter 512 reduces the effect of jitter peaking, which may cause the instantaneous phase difference between the recovered clocks clk 1 and clk 2 to be considerably different than the phase difference between the data inputs d in1 and d in2 .
  • the bandwidth of filter 512 must be lower than the bandwidth of CDR 102 and CDR 104 .
  • low pass filter 512 may be either analog or digital.
  • FIG. 6 illustrates another example data aligner.
  • a time-to-digital converter 610 is implemented as a mixer 609 followed by a comparator 611 (1-bit A/D converter), and low-pass filter 612 is implemented as a saturation counter.
  • data from CDR 102 and/or 104 may be demultiplexed using clk 1 frequency-divided by two as a reference.
  • the demultiplexers also serve to retime d rec2 [1:0] to clk 1 .
  • DEMUX 614 retimes and demultiplexes d rec2 [1:0] assuming that the recovered clocks clk 1 and clk 2 are in phase (case 1 in FIG. 3 ).
  • DEMUX 616 retimes and demultiplexes d rec2 [1:0] assuming that the recovered clocks clk 1 and clk 2 are out of phase (case 2 in FIG. 3 ).
  • DEMUXes 614 and 616 also retime d rec2 to the clock clk 1 , and appropriately delay bits of d rec2 in case 0 (DEMUX 0 ).
  • the output of CDR 104 is synchronized to the phase 90/270 of divided-by-2 clock clk 1 .
  • the detection of which case occurred and selection between the outputs of DEMUX 614 and DEMUX 616 is based on selector block 618 .
  • the phase difference is detected with mixer 609 , which, driven by the signals of equal frequency, outputs a positive value (m + >m ⁇ ) when the inputs are in-phase within ⁇ /2, and outputs a negative value (m + ⁇ m ⁇ ) when the inputs are out of phase within ⁇ /2.
  • the output of mixer 609 is taken to comparator 611 (1-bit A/D converter) and then to an up/dn input to saturation counter 612 , as shown in FIG. 6 .
  • the counter 612 is sized so that it takes more time to flip its MSB output than the reciprocal of the jitter peaking frequency (around loop bandwidth of CDR 102 and CDR 104 ).
  • the MSB output of the counter 612 is the select signal for the multiplexer 620 .
  • the output of CDR 102 , d rec1 [1:0] is demultiplexed with a 1:2 demultiplexer 624 .
  • the clock input to this 1:2 demultiplexer 624 may be received from frequency divider 626 .
  • the output of this 1:2 demultiplexer 624 , d 1 [3:0] may then be interleaved with the output of the multiplexer 620 , d 2 [3:0].
  • FIG. 7 illustrates an example method for CDR with a data aligner.
  • the method begins at step 702 , where first and second input streams comprising first and second input data bits, respectively, are received at an input frequency at first and second independent CDRs, respectively.
  • the first and second CDRs generate first and second recovered clocks based on the first and second input streams, respectively.
  • the first and second CDRs retime and demultiplex the first and second input data bits to generate n first recovered streams and m (where n is generally equal to m) second recovered streams, respectively, each comprising first and second recovered data bits, respectively.
  • a data aligner determines a phase difference between the first and second recovered clocks.
  • the data aligner aligns the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference.
  • the data aligner combines the first and second recovered data bits to generate 2n output streams.
  • the data aligner retimes the first and second recovered data bits in the output stream based on either the first or second recovered clock, at which point the method ends.
  • Particular embodiments may continuously repeat the steps of the method of FIG. 7 , according to particular needs.
  • the present disclosure describes and illustrates particular steps of the method of FIG. 7 as occurring in a particular order, the present disclosure contemplates any suitable steps of the method of FIG. 7 occurring in any suitable order.
  • the present disclosure describes and illustrates particular components carrying out particular steps of the method of FIG. 7
  • the present disclosure contemplates any suitable combination of any suitable components carrying out any suitable steps of the method of FIG. 7 .
  • the data aligner may combine recovered streams from three, four, or more CDRs using, for example, one clock recovered from one of the CDRs.

Abstract

In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.

Description

RELATED APPLICATION
This application claims the benefit, under 35 U.S.C. §119(e), of U.S. Provisional Patent Application No. 61/084,425, entitled Clock and Data Recovery Circuit with Data Aligner, filed 29 Jul. 2008.
TECHNICAL FIELD
The present disclosure relates generally to clock and data recovery (CDR).
BACKGROUND
CDR circuits (or systems) are generally used to sample an incoming data signal, extract the clock from the incoming data signal, and retime the sampled data. A phase-locked loop (PLL)-based CDR circuit is a conventional type of CDR circuit. By way of example, in a conventional PLL based CDR, a phase detector compares the phase between input data bits from a serial input data stream and a clock signal from a voltage-controlled oscillator (VCO). In response to the phase difference between the input data and the clock, the phase detector generates signals UP and DN. A charge pump drives a current to or from a loop filter according to the UP and DN signals. The loop filter generates a control voltage VCTRL for the VCO based on the UP and DN signals. The loop acts as a feedback control system that tracks the phase of input data stream with the phase of the clock that the loop generates. The dynamics of the loop are generally determined by the open loop gain and the location of open loop zeroes and poles (predominantly in the loop filter).
A problem in systems employing conventional CDR architectures utilizing two CDRs for use in demodulated differential quadrature phase shift keying (DQPSK) modulated data streams is that they are suitable only for full-rate CDRs without data demultiplexing, when the frequencies of the clocks within each CDR are the same as the data rate of the input data bit streams. Otherwise, there exists an uncertainty of relative clock and data phases from the two CDRs and the circuit may operate erroneously. However, many practical CDRs in high speed optical communications use either half-rate or quarter-rate architectures; that is, each CDR may use a clock whose frequency is half (half-rate), a quarter (quarter-rate), or a smaller fraction of the rate of input data stream, in order to cope with high input data rates.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an example system employing a CDR architecture that includes two independent CDRs and a data aligner.
FIG. 2 illustrates an example DQPSK modulation scheme.
FIG. 3 illustrates example phase relationships among recovered clocks and data streams.
FIG. 4 illustrates an example data aligner.
FIG. 5 illustrates another example of a data aligner.
FIG. 6 illustrates another example of a data aligner.
FIG. 7 illustrates an example method for CDR with a data aligner.
 DESCRIPTION OF EXAMPLE EMBODIMENTS
Particular embodiments relate to an electronic circuit for clock and data recovery (CDR) for a two or more bits per symbol serial communication system. More particularly, the present disclosure provides examples of a CDR architecture that takes two input data bit streams and produces one or more output data bit streams in which the bits from the two input data bit streams are interleaved. In particular embodiments, the two input bit streams have the same data rate and limited relative phase (e.g., within limits of ±UI/2). An example CDR architecture may include two independent CDRs, one for each of two input data streams, as well as a data aligner, which combines the data outputs from the two CDRs into one or more output data streams using the clock recovered by one of the CDRs. (In particular embodiments, one stream may refer to one wire, and vice versa, where appropriate). Particular embodiments further relate to the use of CDRs having less than full-rate architecture. More specifically, particular embodiments utilize CDRs that employ half-rate or quarter-rate architecture. Generally, particular embodiments can be used for any two-input CDR application.
By way of example, particular embodiments relate to the use of a CDR architecture within a deserializer utilized in optical communication. By way of example, particular embodiments may be utilized in a DQPSK transponder. However, alternative embodiments may be utilized in other specific applications and for non-optical communication (e.g., hard-wired communication using electrons), where appropriate. Particular embodiments may be utilized in high speed communication systems (e.g., data rates greater than 10 Gb/s) and in even more particular embodiments, in communication systems having data rates at or exceeding 40 Gb/s. Particular embodiments may be implemented with a complementary metal oxidesemiconductor (CMOS) architecture. Particular embodiments may also provide reduced power consumption.
FIG. 1 illustrates an example CDR architecture 100. CDR architecture 100 includes a first CDR circuit 102 and a second CDR circuit 104 each of which may include one or more modules or subcircuits. CDR circuit 102 is configured to receive first input data bits from a first input data bit stream din1 while CDR circuit 104 is configured to receive second input data bits from a second input data bit stream din2. In particular embodiments, each of the first and second input data bit streams din1 and din2 is sampled from a symbol stream and each includes input data bits sampled at an input frequency.
The present disclosure contemplates the use of any suitable CDR to implement CDR 102 or CDR 104. Furthermore, in particular embodiments, CDRs 102 and 104 may perform independently from one another. In particular embodiments, each CDR is a half-rate 20 Gb/s CDR. A single channel CDR block may consist of a 10 GHz quadrature VCO, four 10 Gb/s samplers, a 10 Gb/s synchronizer, a 4:8 10 Gb/s-to-5 Gb/s DEMUX, a clock divider that supplies 4-phase 5 GHz clock, a phase detector (PD), and charge pump (CP) that run at 5 Gb/s, a loop filter, and a frequency acquisition circuit. In particular embodiments, the samplers operate at half data rate and produce four 10 Gb/s samples, each synchronized to the VCO phase used to clock the sampler. The Synchronizer block may operate at 10 Gb/s and generally serves two purposes: to synchronize the 10 Gb/s samples to the common reference (VCO phase 0), and to generate static 10 Gb/s signals from the sampler outputs, which are invalid (reset) half of the cycle due to a particular implementation of the preceding sampler. The clock frequency divider and the 10 Gb/s-to-5 Gb/s DEMUX generate the 8×5 Gb/s static CMOS bits from the 4×10 Gb/s CML bits from the Synchronizer. The PD runs at 5 Gb/s, and generates up and dn signals for the CP, which drives the loop filter and generates the control voltage Vctrl to the VCO.
In particular embodiments, the symbol stream is a differential quadrature phase shift keying (DQPSK) modulated data stream. By way of example and not by way of limitation, the first input data bits from the first input data bit stream din1 may be even-numbered bits from the symbol stream while the second input data bits from the second input data bit stream din2 may be odd-numbered bits from the symbol stream. By way of reference, DQPSK is a modulation scheme in which two bits at a time are grouped and used to phase-modulate an output. By way of example, in an example implementation, 2 bits per symbol are encoded in the phases of light. The modulation is differential, which means that the input symbol (two bits) corresponds not to a particular phase of the output, but to the change of the phase relative to the phase of the previous symbol. FIG. 2 illustrates an example DQPSK modulation scheme. In the example illustrated in FIG. 2, symbol 00 causes zero change in the output phase, symbol 01 causes a phase change of π/2, symbol 11 causes a phase change of π, and symbol 10 causes a phase change of 3π/2. In this way the demodulation may be made insensitive to a phase shift in the communication medium.
A DQPSK receiver demodulates the DQPSK symbol stream to obtain two bits per symbol, and thus two streams of binary data, din1 and din2, which may then be amplified and sent to CDRs 102 and 04, respectively. The two input data streams din1 and din2 have the same data rate, but the exact phase relationship is unknown (within limits of ±UI/2 where UI is the unit interval) due to mismatches in the paths from the demodulator to respective CDR 102 or 104. A proper clock and data recovery circuit should not only recover the clock and individual data, but also correctly recombine the two streams.
CDR 102 generates a first recovered clock clk1 based on the first input data stream din1. Similarly, CDR 104 generates a second recovered clock clk2 based on the second input data stream din2. In particular embodiments, one or both of the recovered clocks clk1 and clk2 are then transmitted to a data aligner 106, which may include one or more modules or subcircuits.
In particular embodiments, CDR 102 also retimes and demultiplexes the data bits from the first input data bit stream din1. By way of example, CDR 102 may perform 1:n demultiplexing (n≧1, usually n=2k, where k=0, 1, 2 . . . ). That is, CDR 102 may demultiplex corresponding input data bit stream din1 into n recovered streams. Demultiplexing is advantageous in particular embodiments utilized in high speed communication systems. By demultiplexing the input data bit stream din1, the data is easier to handle. Conventionally, it is difficult to design a circuit that can recover a full-rate clock at high speed. By way of example, a high speed data rate may be considered a data rate greater than or equal to 1 Gb/s, or greater than 10 Gb/s, or greater than 20 Gb/s, or greater than 40 Gb/s.
In particular embodiments, n is greater than or equal to 2 and the data bits in each first recovered data bit stream drec1 are output from CDR 102 at a first demultiplexed frequency that is the same for each first recovered data bit stream drec1 and that is less than the input frequency. Likewise, in particular embodiments, CDR 104 also retimes and demultiplexes the data bits from the second input data bit stream din2 to generate m second recovered data bit streams drec2 each output at a second demultiplexed frequency that is less than the input frequency. In particular embodiments, the value of m is equal to the value of n and the first demultiplexed frequency equals the second demultiplexed frequency. In the following description, the value of m is assumed to equal the value of n and the first demultiplexed frequency is assumed to be equal to the second demultiplexed frequency (and thus FIG. 1 illustrates n second recovered streams drec2).
In a particular embodiment, each CDR operates independently of the other and demultiplexes the recovered data to 5 Gb/s. The first and second recovered data bit streams drec1 and drec1 are then sent to data aligner 106. In particular embodiments, data aligner 106 operates off one, and only one, of the clocks, clk1 or clk2, recovered from one of the input streams din1 or din2, respectively, by corresponding CDR 102 or 104. In particular embodiments, data aligner 106 detects/determines a phase difference between the first and second recovered clocks cin1 and clk2. Data aligner 106 may then retime and align the first recovered bits drec1[n-1:0] from the n first recovered data bit streams drec1 with the second recovered bits drec2[n-1:0] from the n second recovered data bit streams drec2 based at least in part on the value of n and the determined phase difference. In particular embodiments, data aligner 106 then combines the first recovered bits drec1[n-1:0] from the n first recovered data bit streams drec1 with the second recovered bits drec1 [n-1:0] from the n second recovered data bit streams drec2 to generate at least one or more output data bit streams. In particular embodiments, data aligner 106 generates 2n output data bit streams dout[2n-1:0]. It should be appreciated that the foregoing may be performed on a continuous basis during operation of CDR architecture 100.
While demultiplexing makes the data in the input data bit streams easier to handle, demultiplexing also results in a new problem as evidenced in the following. In the general case in which n=1 (full rate CDR), data aligner 106 only needs to synchronize the bits from the two recovered streams drec1 and drec2 recovered by CDRs 102 and 104 to the common chosen clock, clk1 or clk2, and interleave these data bits from the two recovered streams to produce output streams dout[2n-1:0]. However, when the input data bit streams din1 and din2 are demultiplexed (e.g., n=2, 4, 8, 16, . . . ), there exists an uncertainty in the relative phase of the recovered clocks, clk1 and clk2, and the recovered data bit streams, drec1 and drec2, output from CDRs 102 and 104 due at least in part to the random nature of the process of CDR phase locking and/or clock frequency division typically used for the demultiplexing.
By way of example, if the input phases are identical and the CDRs utilize half-rate architecture (the frequency of the internally generated clocks used to sample the input data bit streams din1 and din2 is half of the data rate), the recovered clocks, clk1 and clk2, may be either approximately in phase (case 1, disregarding non-idealities for the moment), or approximately out of phase (case 2, ±180° phase difference), as shown in FIG. 3, which illustrates phase relationships among recovered clocks clk1 and clk2 and data streams din1, din2, drec1 [0] (first first recovered data bit stream), drec1[1] (second first recovered data bit stream), drec2[0] (first second recovered data bit stream), and drec2[1] (second second recovered data bit stream).
Accordingly, the recovered bits from the first recovered data bit streams drec1 from CDR 102 may be in phase or out of phase with the recovered bits from the second recovered data bit streams drec2 from CDR 104. Either of the two cases (case 1 or case 2) may happen due to, by way of example, differences between the initial states of CDRs 102 and 104, mismatches between the CDR components, or different input patterns at din1 and din2. Without loss of generality, it is assumed that the least significant bit (LSB) (bit 0) in a demultiplexed data stream corresponds to the earliest bit in the input stream, and that the most significant bit (MSB) corresponds to the latest bit. To correctly combine the recovered data streams drec1 and drec2 from CDRs 102 and 104, data aligner 106 must detect which of the two cases (n cases in general) occurred. Data aligner 106 determines which of the n cases occurred or is occurring by detecting the phase difference between the recovered clocks clk1 and clk2.
In particular embodiments, in which n=2, only two phases (one from each CDR) are compared. Assuming for sake of eased visualization that the bits in the original symbol stream are ordered according to the alphabet, e.g., a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, . . . , and the bits in each input data bit stream din1 and din2 are as shown in FIG. 3, then the bits in each of the streams drec1[0], drec1[1], drec2[0], and drec2[1] are as shown in FIG. 3 for each of the two cases: case 1 (clk1 in phase with clk2) and case 2 (clk1 out of phase with respect to clk2). Assuming case 1, to generate 2n output streams dout that together are a proper reconstruction of the original symbol stream, data aligner 106 inserts (into the output streams) a first bit of the first first recovered data bit stream drec1[0,0] followed by a first bit of the first second recovered data bit stream drec2[0,0] followed by a first bit of the second first recovered data bit stream drec1[1,0] followed by a first bit of the second second recovered data bit stream drec2[1,0], which would then be followed by a second bit of the first first recovered data bit stream drec1[0,1] followed by a second bit of the first second recovered data bit stream drec2[0,1] followed by a second bit of the second first recovered data bit stream drec1[1,1] followed by a second bit of the second second recovered data bit stream drec2[1,1], and so on.
Assuming case 2, in particular embodiments, to generate the 2n output streams dout that together are a proper reconstruction of the original symbol stream, data aligner 106 inserts (into the output streams) a first bit of the first first recovered data bit stream drec1[0,0] followed by a delayed first bit of the first second recovered data bit stream drec2[0,0] followed by a first bit of the second first recovered data bit stream drec1[1,0] followed by a first bit of the second second recovered data bit stream drec2[1,0], which would then be followed by a second bit of the first first recovered data bit stream drec1[0,1] followed by a delayed second bit of the first second recovered data bit stream drec2[0,1] followed by a second bit of the second first recovered data bit stream drec1 [1,1] followed by a second bit of the second second recovered data bit stream drec2[1,1], and so on.
FIG. 4 illustrates a schematic of an example data aligner 106. Data aligner 106 includes a shifter 408 that generates delay recovered data from CDR 104, a selector 410, which in particular embodiments is a time-to-digital converter that converts the phase offset between the recovered clocks clk1 and clk2 to a digital code, and a multiplexer (MUX) 412 that selects the appropriate shift/delay combination of the input. The output of MUX 412 in FIG. 4 is in phase with clk2, and thus it should be synchronized with clk1. Any suitable method for the required synchronization may be used. In particular embodiments, additional manipulation is performed on drec2[n-1:0] and dp[n-1:0] prior to multiplexing, such as demultiplexing with divided clk1 or clk2.
Selector (e.g., time-to-digital converter) 410 may be implemented in various ways. By way of example, in particular embodiments, time-to-digital converter 410 may be implemented as a Vernier Delay Line (VDL) or a delay locked loop (DLL). The conversion table assumed for FIG. 4 is shown in Table 1 provided below. In particular embodiments, the conversion table may be constructed differently than that shown in Table 1 as long as the one-to-one correspondence between the input phase difference and the selected data is preserved.
TABLE 1
Conversion table of the time-to-digital converter
Input phase differenceΔφ = φ(c1k2) − (φ(c1k1)[rad] Digital code
−2π/n ≦ Δφ < 2π/n 0
2π/n ≦ Δφ < 6π/n 1
6π/n ≦ Δφ < 10π/n 2
. . . . . .
−2π*(n − 3)/n ≦ Δφ < 2π*(n − 1)/n n − 1
FIG. 5 illustrates another example data aligner. The data aligner may be similar to data aligner 106 described with reference to FIG. 4, except for the generation of the multiplexer select signal. In FIG. 5, the output of time-to-digital converter 510 is brought to a low-pass filter 512, which averages the decision on which data order is selected. This structure is generally useful when the offset between the inputs to CDRs 102 and 104, din1 and din2 respectively, is comparable to UI/2, such that the output of time-to-digital converter 510 can be corrupted by noise or circuit non-idealities. In particular embodiments, low pass filter 512 reduces the effect of jitter peaking, which may cause the instantaneous phase difference between the recovered clocks clk1 and clk2 to be considerably different than the phase difference between the data inputs din1 and din2. In particular embodiments, to prevent jitter peaking from causing erroneous data alignment, the bandwidth of filter 512 must be lower than the bandwidth of CDR 102 and CDR 104.
In particular embodiments, low pass filter 512 may be either analog or digital. In particular embodiments, an analog filter generally requires an A/D converter at the output and, depending on the interface between time-to-digital converter 510 and low-pass filter 512, possibly a D/A converter at the input. If n=2, the D/A converter at the input is generally not necessary, and an A/D converter may be implemented as a 1-bit comparator. Note that A/D and D/A converters have modest performance requirements as they operate at a speed comparable to the loop bandwidth; that is, by way of example, a few tens of megahertz even for the fastest gigabit links.
FIG. 6 illustrates another example data aligner. The embodiment illustrated in FIG. 6 may be considered a special case of the embodiment illustrated in FIG. 5 in which n=2, a time-to-digital converter 610 is implemented as a mixer 609 followed by a comparator 611 (1-bit A/D converter), and low-pass filter 612 is implemented as a saturation counter. Prior to multiplexing, data from CDR 102 and/or 104 may be demultiplexed using clk1 frequency-divided by two as a reference. The demultiplexers also serve to retime drec2[1:0] to clk1. DEMUX 614 retimes and demultiplexes drec2[1:0] assuming that the recovered clocks clk1 and clk2 are in phase (case 1 in FIG. 3). DEMUX 616 retimes and demultiplexes drec2[1:0] assuming that the recovered clocks clk1 and clk2 are out of phase (case 2 in FIG. 3). In addition to demultiplexing, DEMUXes 614 and 616 also retime drec2 to the clock clk1, and appropriately delay bits of drec2 in case 0 (DEMUX 0). The output of CDR 104 is synchronized to the phase 90/270 of divided-by-2 clock clk1.
The detection of which case occurred and selection between the outputs of DEMUX 614 and DEMUX 616 is based on selector block 618. The phase difference is detected with mixer 609, which, driven by the signals of equal frequency, outputs a positive value (m+>m−) when the inputs are in-phase within ±π/2, and outputs a negative value (m+<m−) when the inputs are out of phase within ±π/2. The output of mixer 609 is taken to comparator 611 (1-bit A/D converter) and then to an up/dn input to saturation counter 612, as shown in FIG. 6. The counter 612 is sized so that it takes more time to flip its MSB output than the reciprocal of the jitter peaking frequency (around loop bandwidth of CDR 102 and CDR 104). The MSB output of the counter 612 is the select signal for the multiplexer 620.
In one particular embodiment, the output of CDR 102, drec1[1:0], is demultiplexed with a 1:2 demultiplexer 624. The clock input to this 1:2 demultiplexer 624 may be received from frequency divider 626. The output of this 1:2 demultiplexer 624, d1[3:0] may then be interleaved with the output of the multiplexer 620, d2[3:0]. Interleaver 622 shown in FIG. 6 involves no physical circuit, and it only designates that drec1 and drec2 are combined in the output bus dout in the way that drec1[0] becomes dout[0], drec2[0] becomes dout[1], drec1[1] becomes dout[2], . . . drec2[3] becomes dout[7]. As noted earlier, it was assumed that bit 0 (LSB) is a demultiplexed version of the earliest input bit to the CDR, and MSB is the demultiplexed version of the latest bit.
FIG. 7 illustrates an example method for CDR with a data aligner. The method begins at step 702, where first and second input streams comprising first and second input data bits, respectively, are received at an input frequency at first and second independent CDRs, respectively. At step 704, the first and second CDRs generate first and second recovered clocks based on the first and second input streams, respectively. At step 706, the first and second CDRs retime and demultiplex the first and second input data bits to generate n first recovered streams and m (where n is generally equal to m) second recovered streams, respectively, each comprising first and second recovered data bits, respectively. At step 708, a data aligner determines a phase difference between the first and second recovered clocks. At step 710, the data aligner aligns the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference. At step 712, the data aligner combines the first and second recovered data bits to generate 2n output streams. At 714, the data aligner retimes the first and second recovered data bits in the output stream based on either the first or second recovered clock, at which point the method ends. Particular embodiments may continuously repeat the steps of the method of FIG. 7, according to particular needs. Although the present disclosure describes and illustrates particular steps of the method of FIG. 7 as occurring in a particular order, the present disclosure contemplates any suitable steps of the method of FIG. 7 occurring in any suitable order. Moreover, although the present disclosure describes and illustrates particular components carrying out particular steps of the method of FIG. 7, the present disclosure contemplates any suitable combination of any suitable components carrying out any suitable steps of the method of FIG. 7.
The present disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend.
By way of example, although a data aligner that combines recovered streams from two independent CDRs based on one clock recovered from one of the CDRs has been described, it should be appreciated that, in alternate embodiments, the data aligner may combine recovered streams from three, four, or more CDRs using, for example, one clock recovered from one of the CDRs.

Claims (23)

1. A method comprising:
at a first clock and data recovery (CDR) circuit:
receiving a first input data stream comprising first input data bits at an input frequency, the first input data stream having been sampled from a symbol stream;
generating a first recovered clock based on the first input data stream; and
retiming and demultiplexing the first input data bits from the first input data stream to generate n first recovered data streams each comprising first recovered data bits at a first divided clock having a first divided clock frequency that is less than the input frequency;
at a second CDR circuit:
receiving a second input data stream comprising second input data bits at the input frequency, the second input data stream having been sampled from the symbol stream;
generating a second recovered clock based on the second input data stream; and
retiming and demultiplexing the second input data bits from the second input stream to generate n second recovered data streams each comprising second recovered data bits at a second divided clock having a second divided clock frequency that is less than the input frequency;
determining a phase difference between the first recovered clock and the second recovered clock;
aligning the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams based at least in part on:
a value of n; and
the phase difference;
combining the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams to generate one or more output data streams; and
retiming the first and second recovered data bits in the one or more output data streams based on either the first recovered clock or the second recovered clock.
2. The method of claim 1, wherein:
generating the first recovered clock at the first CDR circuit is independent from generating the second recovered clock at the second CDR circuit; and
generating the second recovered clock at the second CDR circuit is independent from generating the first recovered clock at the first CDR circuit.
3. The method of claim 1, wherein:
retiming and demultiplexing at the first CDR is independent from retiming and demultiplexing at the second CDR; and
retiming and demultiplexing at the second CDR is independent from retiming and demultiplexing at the first CDR circuit.
4. The method of claim 1, wherein there are 2n output data streams.
5. The method of claim 1, wherein:
the value of n is 2;
there being two first recovered data streams and two second recovered data streams:
the two first recovered data streams comprising a first first recovered data stream of first first recovered data bits and a second first recovered data stream of second first recovered data bits; and
the two second recovered data streams comprising a first second recovered data stream of first second recovered data bits and a second second recovered data stream of second second recovered data bits;
there being a total of four recovered data streams.
6. The method of claim 5, wherein:
the first recovered clock comprises a first recovered clock frequency;
the second recovered clock comprises a second recovered clock frequency;
the first recovered clock frequency is approximately half the input frequency; and
the second recovered clock frequency is approximately half the input frequency.
7. The method of claim 5, wherein:
there are 4 output data streams;
determining the phase difference comprises determining whether the first recovered clock is in phase or out of phase with the second recovered clock, the first recovered clock being out of phase with the second recovered clock if the first recovered clock is approximately 180° from the second recovered clock; and
combining the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams to generate the one output data stream comprises:
if the first recovered clock is in phase with the second recovered clock inserting into the output data streams a first first recovered data bit, immediately followed by a first second recovered data bit, immediately followed by a second first recovered data bit, immediately followed by a second second recovered data bit, and so on without delaying the insertion of any of the recovered data bits into the output data stream;
if the first recovered clock is out of phase with the second recovered clock, inserting into the output data streams a first first recovered data bit, immediately followed by a first second recovered data bit, immediately followed by a second first recovered data bit, immediately followed by a second second recovered data bit, and so on with the insertion of one or more of the recovered data bits into the output data stream being delayed to ensure insertion of the recovered data bits into the output data stream in an order corresponding to the symbol stream.
8. The method of claim 1, wherein:
the first input data bits are even-numbered bits from the symbol stream; and
the second input data bits are odd-numbered bits from the symbol stream.
9. The method of claim 1, wherein the symbol stream is a differential quadrature phase shift keying (DQPSK) modulated data stream.
10. The method of claim 1, wherein the first and second input data streams comprise differential data streams.
11. The method of claim 1, further comprising one or more additional CDR circuits in addition to the first and second CDR circuits.
12. A system comprising:
a first clock and data recovery (CDR) circuit configured to:
receive a first input data stream comprising first input data bits at an input frequency, the first input data stream having been sampled from a symbol stream;
generate a first recovered clock based on the first input data stream; and
retime and demultiplex the first input data bits from the first input data stream to generate n first recovered data streams each comprising first recovered data bits at a first divided clock having a first divided clock frequency that is less than the input frequency;
a second CDR circuit configured to:
receive a second input data stream comprising second input data bits at the input frequency, the second input data stream having been sampled from the symbol stream;
generate a second recovered clock based on the second input data stream; and
retime and demultiplex the second input data bits from the second input stream to generate n second recovered data streams each comprising second recovered data bits at a second divided clock having a second divided clock frequency that is less than the input frequency; and
a data aligner configured to:
determine a phase difference between the first recovered clock and the second recovered clock;
align the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams based at least in part on:
a value of n; and
the phase difference;
combine the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams to generate one or more output data streams; and
retime the first and second recovered data bits in the one or more output data streams based on either the first recovered clock or the second recovered clock.
13. The system of claim 12, wherein:
the first CDR circuit is configured to generate the first recovered clock independent from the second CDR circuit; and
the second CDR circuit is configured to generate the second recovered clock independent from the first CDR circuit.
14. The system of claim 12, wherein:
the first CDR circuit is configured to retime and demultiplex the first input data bits independent from the second CDR; and
the second CDR circuit is configured to retime and demultiplex the second input data bits independent from the first CDR.
15. The system of claim 12, wherein there are 2n output data streams.
16. The system of claim 12, wherein:
the value of n is 2;
there being two first recovered data streams and two second recovered data streams:
the two first recovered data streams comprising a first first recovered data stream of first first recovered data bits and a second first recovered data stream of second first recovered data bits; and
the two second recovered data streams comprising a first second recovered data stream of first second recovered data bits and a second second recovered data stream of second second recovered data bits;
there being a total of four recovered data streams.
17. The system of claim 16, wherein:
the first recovered clock comprises a first recovered clock frequency;
the second recovered clock comprises a second recovered clock frequency;
the first recovered clock frequency is approximately half the input frequency; and
the second recovered clock frequency is approximately half the input frequency.
18. The system of claim 16, wherein:
there 4 output data streams;
in order to determine the phase difference, the data aligner is configured to determine whether the first recovered clock is in phase or out of phase with the second recovered clock, the first recovered clock being out of phase with the second recovered clock if the first recovered clock is approximately 180° from the second recovered clock; and
in order to combine the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams to generate the one output data stream, the data aligner is configured to:
if the first recovered clock is in phase with the second recovered clock insert into the output data streams a first first recovered data bit, immediately followed by a first second recovered data bit, immediately followed by a second first recovered data bit, immediately followed by a second second recovered data bit, and so on without delaying the insertion of any of the recovered data bits into the output data stream;
if the first recovered clock is out of phase with the second recovered clock, insert into the output data streams a first first recovered data bit, immediately followed by a first second recovered data bit, immediately followed by a second first recovered data bit, immediately followed by a second second recovered data bit, and so on with the insertion of one or more of the recovered data bits into the output data stream being delayed to ensure insertion of the recovered data bits into the output data stream in an order corresponding to the symbol stream.
19. The system of claim 12, wherein:
the first input data bits are even-numbered bits from the symbol stream; and
the second input data bits are odd-numbered bits from the symbol stream.
20. The system of claim 12, wherein the symbol stream is a differential quadrature phase shift keying (DQPSK) modulated data stream.
21. The system of claim 12, wherein the first and second input data streams comprise differential data streams.
22. The system of claim 12, further comprising one or more additional CDR circuits in addition to the first and second CDR circuits.
23. A system comprising:
means for:
receiving a first input data stream comprising first input data bits at an input frequency, the first input data stream having been sampled from a symbol stream;
generating a first recovered clock based on the first input data stream; and
retiming and demultiplexing the first input data bits from the first input data stream to generate n first recovered data streams each comprising first recovered data bits at a first divided clock having a first divided clock frequency that is less than the input frequency;
at a second CDR circuit:
receiving a second input data stream comprising second input data bits at the input frequency, the second input data stream having been sampled from the symbol stream;
generating a second recovered clock based on the second input data stream; and
retiming and demultiplexing the second input data bits from the second input stream to generate n second recovered data streams each comprising second recovered data bits at a second divided clock having a second divided clock frequency that is less than the input frequency;
means for determining a phase difference between the first recovered clock and the second recovered clock;
means for aligning the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams based at least in part on:
a value of n; and
the phase difference;
means for combining the first recovered data bits from the first recovered data streams with the second recovered data bits from the second recovered data streams to generate one or more output data streams; and
means for retiming the first and second recovered data bits in the one or more output data streams based on either the first recovered clock or the second recovered clock.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120250738A1 (en) * 2011-03-30 2012-10-04 Fujitsu Limited Radio apparatus, radio apparatus controller, and synchronization establishing method
US20130249612A1 (en) * 2012-03-26 2013-09-26 Rambus Inc. Method and apparatus for source-synchronous signaling
US20140111256A1 (en) * 2012-10-24 2014-04-24 SK Hynix Inc. Deserializers
US9548855B2 (en) 2013-08-21 2017-01-17 Silab Tech Pvt. Ltd. Method and apparatus for managing estimation and calibration of non-ideality of a phase interpolator (PI)-based clock and data recovery (CDR) circuit
CN107563020A (en) * 2017-08-17 2018-01-09 郑州云海信息技术有限公司 A kind of clock frequency division module design method based on CPLD/FPGA
US10236897B1 (en) * 2018-07-26 2019-03-19 Texas Instruments Incorporated Loss of lock detector

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US8705596B2 (en) * 2010-04-19 2014-04-22 Broadcom Corporation System and method for physical layer device enabled clock diagnostics
US8929500B2 (en) 2012-01-24 2015-01-06 Texas Instruments Incorporated Clock data recovery with out-of-lock detection
JP6032082B2 (en) * 2013-03-25 2016-11-24 富士通株式会社 Reception circuit and semiconductor integrated circuit
US9385859B2 (en) * 2013-12-27 2016-07-05 Realtek Semiconductor Corp. Multi-lane serial data link receiver and method thereof
KR20180125827A (en) 2017-05-16 2018-11-26 에스케이하이닉스 주식회사 Semiconductor device
KR20200082918A (en) 2018-12-31 2020-07-08 에스케이하이닉스 주식회사 Clock generating circuit and memroy device including the same

Citations (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920278A (en) 1987-05-26 1990-04-24 Nec Corporation Phase comparator
US5039889A (en) 1989-08-19 1991-08-13 U.S. Philips Corp. Phase comparison circuit
US5343097A (en) 1991-09-13 1994-08-30 Nec Corporation Phase comparator circuit and phase locked loop (PLL) circuit using the same
US6377575B1 (en) 1998-08-05 2002-04-23 Vitesse Semiconductor Corporation High speed cross point switch routing circuit with word-synchronous serial back plane
US6381291B1 (en) 1998-09-28 2002-04-30 Harris Corporation Phase detector and method
US6426662B1 (en) 2001-11-12 2002-07-30 Pericom Semiconductor Corp. Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays
US20020131539A1 (en) 2000-10-27 2002-09-19 Li Hung Sung Clock and data recovery method and apparatus
US6496077B2 (en) 2000-11-23 2002-12-17 Samsung Electronics Co., Ltd. Phase detector for automatically controlling offset current and phase locked loop including the same
US6545507B1 (en) 2001-10-26 2003-04-08 Texas Instruments Incorporated Fast locking CDR (clock and data recovery circuit) with high jitter tolerance and elimination of effects caused by metastability
US20030189464A1 (en) 2002-04-04 2003-10-09 Oleg Drapkin Spurious-free fractional-n frequency synthesizer with multi-phase network circuit
US20030198311A1 (en) 2002-04-19 2003-10-23 Wireless Interface Technologies, Inc. Fractional-N frequency synthesizer and method
US20030198105A1 (en) 2002-04-15 2003-10-23 Fujitsu Limited Clock recovery circuit and data receiving circuit
US20040022339A1 (en) 2002-03-27 2004-02-05 Takehiko Nakao Clock recovery circuit
US7012474B2 (en) 2003-08-07 2006-03-14 Broadcom Corporation System and method generating a delayed clock output
US7057435B2 (en) 2003-05-30 2006-06-06 Regents Of The University Of California Distributed delay-locked-based clock and data recovery systems
US20060208811A1 (en) 2005-03-21 2006-09-21 An-Ming Lee Multi-phase clock generator and method thereof
US20060255866A1 (en) 2005-05-10 2006-11-16 Nec Electronics Corporation Pulse width modulation circuit and multiphase clock generation circuit
US7142623B2 (en) 2002-05-31 2006-11-28 International Business Machines Corporation On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit
US20070006053A1 (en) 2005-07-01 2007-01-04 Lucent Technologies Inc. Method and apparatus for synchronizing data channels using an alternating parity deskew channel
US20070041486A1 (en) 2005-08-18 2007-02-22 Samsung Electronics Co., Ltd. Semiconductor device, spread spectrum clock generator and method thereof
US20070047972A1 (en) 2005-08-25 2007-03-01 Fujitsu Limited DQPSK optical receiver circuit
US7265690B2 (en) 2003-09-25 2007-09-04 Texas Instruments Incorporated Simplified data recovery from high speed encoded data
US7286625B2 (en) 2003-02-07 2007-10-23 The Regents Of The University Of California High-speed clock and data recovery circuit
WO2008018034A2 (en) 2006-08-10 2008-02-14 Nxp B.V. Dual gilbert cell mixer with offset cancellation
US20080100364A1 (en) 2006-10-30 2008-05-01 Nec Electronics Corporation Multiphase clock generation circuit
US20080111634A1 (en) 2006-11-15 2008-05-15 Shaw-N Min Phase-locked loop capable of dynamically adjusting phase of output signal according to detection result of phase/frequency detector, and method thereof
US7386084B2 (en) 2002-11-06 2008-06-10 Broadcom Corporation Method and system for pattern-independent phase adjustment in a clock and data recovery (CDR) circuit
US20080192873A1 (en) 2007-02-09 2008-08-14 Fujitsu Limited Single Loop Frequency and Phase Detection
US7420870B2 (en) 2005-06-21 2008-09-02 Samsung Electronics Co., Ltd. Phase locked loop circuit and method of locking a phase
US20080260071A1 (en) 2005-12-07 2008-10-23 Stefanos Sidiropoulos Methods and Apparatus for Frequency Synthesis with Feedback Interpolation
US20080309319A1 (en) 2007-06-12 2008-12-18 Texas Instruments Deutschland G.M.B.H. Electronic Device and Method for on Chip Jitter Measurement
US20090009228A1 (en) 2007-07-02 2009-01-08 Samsung Electronics Co., Ltd. Clock generating apparatus
US7489743B2 (en) 2004-07-14 2009-02-10 Samsung Electronics Co., Ltd. Recovery circuits and methods for the same
US20090066423A1 (en) 2007-09-05 2009-03-12 Texas Instruments Deutschland Gmbh Spread spectrum clocking in fractional-n pll
US20090125652A1 (en) 2002-07-26 2009-05-14 Broadcom Corporation Physical layer device having a serdes pass through mode
US7535271B2 (en) 2002-03-22 2009-05-19 Rambus Inc. Locked loop circuit with clock hold function
US20090237128A1 (en) 2008-03-19 2009-09-24 Integrated Device Technology, Inc. High frequency fractional-N divider
US20100086075A1 (en) 2008-07-29 2010-04-08 Fujitsu Limited Parallel Generation and Matching of a Deskew Channel
US20100085086A1 (en) 2008-07-29 2010-04-08 Fujitsu Limited Digital Frequency Detector
US20100090733A1 (en) 2008-07-29 2010-04-15 Fujitsu Limited Generating Multiple Clock Phases
US20100091927A1 (en) 2008-07-29 2010-04-15 Fujitsu Limited Clock and Data Recovery (CDR) Using Phase Interpolation
US20100091925A1 (en) 2008-07-29 2010-04-15 Fujitsu Limited Triple Loop Clock and Data Recovery (CDR)
US20100090723A1 (en) 2008-07-29 2010-04-15 Fujitsu Limited Symmetric Phase Detector
US20100119024A1 (en) 2005-01-21 2010-05-13 Shumarayev Sergey Y Method and apparatus for multi-mode clock data recovery
US20100241918A1 (en) 2009-03-20 2010-09-23 Fujitsu Limited Clock and data recovery for differential quadrature phase shift keying
US20100266006A1 (en) 2003-12-17 2010-10-21 Werner Carl W Signaling system with selectively-inhibited adaptive equalization
US7924071B2 (en) 2008-09-16 2011-04-12 Renesas Electronics Corporation Synchronization detection circuit, pulse width modulation circuit using the same, and synchronization detection method

Patent Citations (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920278A (en) 1987-05-26 1990-04-24 Nec Corporation Phase comparator
US5039889A (en) 1989-08-19 1991-08-13 U.S. Philips Corp. Phase comparison circuit
US5343097A (en) 1991-09-13 1994-08-30 Nec Corporation Phase comparator circuit and phase locked loop (PLL) circuit using the same
US6377575B1 (en) 1998-08-05 2002-04-23 Vitesse Semiconductor Corporation High speed cross point switch routing circuit with word-synchronous serial back plane
US6381291B1 (en) 1998-09-28 2002-04-30 Harris Corporation Phase detector and method
US20020131539A1 (en) 2000-10-27 2002-09-19 Li Hung Sung Clock and data recovery method and apparatus
US6496077B2 (en) 2000-11-23 2002-12-17 Samsung Electronics Co., Ltd. Phase detector for automatically controlling offset current and phase locked loop including the same
US6545507B1 (en) 2001-10-26 2003-04-08 Texas Instruments Incorporated Fast locking CDR (clock and data recovery circuit) with high jitter tolerance and elimination of effects caused by metastability
US6426662B1 (en) 2001-11-12 2002-07-30 Pericom Semiconductor Corp. Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays
US7535271B2 (en) 2002-03-22 2009-05-19 Rambus Inc. Locked loop circuit with clock hold function
US20040022339A1 (en) 2002-03-27 2004-02-05 Takehiko Nakao Clock recovery circuit
US20030189464A1 (en) 2002-04-04 2003-10-09 Oleg Drapkin Spurious-free fractional-n frequency synthesizer with multi-phase network circuit
US20030198105A1 (en) 2002-04-15 2003-10-23 Fujitsu Limited Clock recovery circuit and data receiving circuit
US20030198311A1 (en) 2002-04-19 2003-10-23 Wireless Interface Technologies, Inc. Fractional-N frequency synthesizer and method
US7142623B2 (en) 2002-05-31 2006-11-28 International Business Machines Corporation On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit
US20090125652A1 (en) 2002-07-26 2009-05-14 Broadcom Corporation Physical layer device having a serdes pass through mode
US7386084B2 (en) 2002-11-06 2008-06-10 Broadcom Corporation Method and system for pattern-independent phase adjustment in a clock and data recovery (CDR) circuit
US7286625B2 (en) 2003-02-07 2007-10-23 The Regents Of The University Of California High-speed clock and data recovery circuit
US7057435B2 (en) 2003-05-30 2006-06-06 Regents Of The University Of California Distributed delay-locked-based clock and data recovery systems
US7012474B2 (en) 2003-08-07 2006-03-14 Broadcom Corporation System and method generating a delayed clock output
US7265690B2 (en) 2003-09-25 2007-09-04 Texas Instruments Incorporated Simplified data recovery from high speed encoded data
US20100266006A1 (en) 2003-12-17 2010-10-21 Werner Carl W Signaling system with selectively-inhibited adaptive equalization
US7489743B2 (en) 2004-07-14 2009-02-10 Samsung Electronics Co., Ltd. Recovery circuits and methods for the same
US20100119024A1 (en) 2005-01-21 2010-05-13 Shumarayev Sergey Y Method and apparatus for multi-mode clock data recovery
US20060208811A1 (en) 2005-03-21 2006-09-21 An-Ming Lee Multi-phase clock generator and method thereof
US7446616B2 (en) 2005-03-21 2008-11-04 Realtek Semiconductor Corp. Multi-phase clock generator and method thereof
US20060255866A1 (en) 2005-05-10 2006-11-16 Nec Electronics Corporation Pulse width modulation circuit and multiphase clock generation circuit
US7420870B2 (en) 2005-06-21 2008-09-02 Samsung Electronics Co., Ltd. Phase locked loop circuit and method of locking a phase
US20070006053A1 (en) 2005-07-01 2007-01-04 Lucent Technologies Inc. Method and apparatus for synchronizing data channels using an alternating parity deskew channel
US7881419B2 (en) 2005-08-18 2011-02-01 Samsung Electronics Co., Ltd. Semiconductor device, spread spectrum clock generator and method thereof
US20070041486A1 (en) 2005-08-18 2007-02-22 Samsung Electronics Co., Ltd. Semiconductor device, spread spectrum clock generator and method thereof
US7444085B2 (en) 2005-08-25 2008-10-28 Fujitsu Limited DQPSK optical receiver circuit
US20070047972A1 (en) 2005-08-25 2007-03-01 Fujitsu Limited DQPSK optical receiver circuit
US20080260071A1 (en) 2005-12-07 2008-10-23 Stefanos Sidiropoulos Methods and Apparatus for Frequency Synthesis with Feedback Interpolation
WO2008018034A2 (en) 2006-08-10 2008-02-14 Nxp B.V. Dual gilbert cell mixer with offset cancellation
US20090149149A1 (en) 2006-08-10 2009-06-11 Ruijs Leonardus C H Dual Gilbert Cell Mixer with Offset Cancellation
US20080100364A1 (en) 2006-10-30 2008-05-01 Nec Electronics Corporation Multiphase clock generation circuit
US20080111634A1 (en) 2006-11-15 2008-05-15 Shaw-N Min Phase-locked loop capable of dynamically adjusting phase of output signal according to detection result of phase/frequency detector, and method thereof
US7679453B2 (en) 2006-11-15 2010-03-16 Realtek Semiconductor Corp. Phase-locked loop capable of dynamically adjusting phase of output signal according to detection result of phase/frequency detector, and method thereof
US20080192873A1 (en) 2007-02-09 2008-08-14 Fujitsu Limited Single Loop Frequency and Phase Detection
US20080309319A1 (en) 2007-06-12 2008-12-18 Texas Instruments Deutschland G.M.B.H. Electronic Device and Method for on Chip Jitter Measurement
US20090009228A1 (en) 2007-07-02 2009-01-08 Samsung Electronics Co., Ltd. Clock generating apparatus
US20090066423A1 (en) 2007-09-05 2009-03-12 Texas Instruments Deutschland Gmbh Spread spectrum clocking in fractional-n pll
US7737791B2 (en) 2007-09-05 2010-06-15 Texas Instruments Deutschland Gmbh Spread spectrum clocking in fractional-N PLL
US20090237128A1 (en) 2008-03-19 2009-09-24 Integrated Device Technology, Inc. High frequency fractional-N divider
US20100085086A1 (en) 2008-07-29 2010-04-08 Fujitsu Limited Digital Frequency Detector
US20100090723A1 (en) 2008-07-29 2010-04-15 Fujitsu Limited Symmetric Phase Detector
US20100091925A1 (en) 2008-07-29 2010-04-15 Fujitsu Limited Triple Loop Clock and Data Recovery (CDR)
US20100091927A1 (en) 2008-07-29 2010-04-15 Fujitsu Limited Clock and Data Recovery (CDR) Using Phase Interpolation
US20100090733A1 (en) 2008-07-29 2010-04-15 Fujitsu Limited Generating Multiple Clock Phases
US20100086075A1 (en) 2008-07-29 2010-04-08 Fujitsu Limited Parallel Generation and Matching of a Deskew Channel
US8058914B2 (en) 2008-07-29 2011-11-15 Fujitsu Limited Generating multiple clock phases
US8138798B2 (en) 2008-07-29 2012-03-20 Fujitsu Limited Symmetric phase detector
US7924071B2 (en) 2008-09-16 2011-04-12 Renesas Electronics Corporation Synchronization detection circuit, pulse width modulation circuit using the same, and synchronization detection method
US20100241918A1 (en) 2009-03-20 2010-09-23 Fujitsu Limited Clock and data recovery for differential quadrature phase shift keying

Non-Patent Citations (30)

* Cited by examiner, † Cited by third party
Title
Dally, William et al., "Digital Systems Engineering," Cambridge University Press, Cambridge, UK, 2008.
Hanumolu, P. K. et al., "A Wide-Tracking Range Clock and Data Recovery Circuit", IEEE JSSC, 43:2, Feb. 2008.
Lee, J. et al., "A 40-Gb/s Clock and Data Recovery Circuit in O.18-/-tm CMOS Technology", IEEE Journal of Solid-State Circuits, 38:12, Dec. 2003.
Nedovic, N. et al., "A 40-44Gb/s 3x Oversampling CMOS CDR /1: 16 DEMUX", ISSCC Digest of Technical Papers.
Nedovic, N., U.S. Appl. No. 12/510,211, USPTO, Amendment after non-fmal Office Action filed Dec. 2, 2010.
Nedovic, N., U.S. Appl. No. 12/510,211, USPTO, Appeal Brief filed Sep. 6, 2011.
Nedovic, N., U.S. Appl. No. 12/510,211, USPTO, Examiner's Answer to Appeal Brief dated Nov. 10, 2011.
Nedovic, N., U.S. Appl. No. 12/510,211, USPTO, Notice of Appeal and Pre-Brief Appeal filed Jun. 8, 2011.
Nedovic, N., U.S. Appl. No. 12/510,211, USPTO, Reply Brief filed Jan. 9, 2012.
Nedovic, N., U.S. Appl. No. 12/511,340, USPTO, Amendment after non-final Office Action filed Dec. 28, 2010.
Nedovic, N., U.S. Appl. No. 12/511,340, USPTO, Notice of Allowance dated Jan. 19, 2012.
Nedovic, N., U.S. Appl. No. 12/511,352, USPTO, Amendment after non-final Office Action filed Feb. 8, 2011.
Nedovic, N., U.S. Appl. No. 12/511,352, USPTO, Notice of Allowance dated Aug. 23, 2011.
Nedovic, N., U.S. Appl. No. 13/424,728, USPTO, Non-final Office Action dated Apr. 26, 2012.
Nedovic, N., U.S. Appl. No. 13/424,728, USPTO, Patent Application filed Mar. 20, 2012, Symmetric Phase Detector .
Office Action for U.S. Appl. No. 12/510,211, Aug. 23, 2010.
Office Action for U.S. Appl. No. 12/510,211, Feb. 10, 2011.
Office Action for U.S. Appl. No. 12/511,340, Sep. 28, 2010.
Office Action for U.S. Appl. No. 12/511,352, Oct. 29, 2010.
Office Action for U.S. Appl. No. 12/511,365, Oct. 25, 2011.
Parikh, S., U.S. Appl. No. 12/511,917, USPTO, Non-final Office Action dated May 29, 2012.
Savoj, Jafar et al., "Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems," Proceedings of Design Automation Conference, 2001.
Scalable SerDes Framer Interface (SFI-S): Implementation Agreement for Interfaces beyond 40G for Physical Layer Devices, IA# OIF-SFI-S-01.0, Nov. 2008.
SerDes Framer Interface Level 5 Phase 2 (SFI-5.2): Implementation Agreement for 40Gb/s Interface for Physical Layer Devices, IA# OIF-SFI5-02.0, Oct. 2, 2006.
Staszewski, R. B. et al, "All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS", IEEE JSSC, 39:12, Dec. 2004.
USPTO Notice of Allowance and Fees Due for U.S. Appl. No. 12/728,756.
Von Bueren, George et al, "5.75 to 44Gb/s Quarter Rate CDR with Data Rate Selection in 90nm Bulk CMOS," 34th European Solid-State Circuits Conference, ESSCIRC, 2008.
Walker, W., U.S. Appl. No. 12/511,365, USPTO, Non-final Office Action dated Mar. 29, 2012.
Walker, W., U.S. Appl. No. 12/511,365, USPTO, Supplemental Amendment to Office Action filed Mar. 5, 2012.
Walker, W.., U.S. Appl. No. 12/511,365, USPTO, Amendment after non-final Office Action filed Jan. 20, 2012.

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120250738A1 (en) * 2011-03-30 2012-10-04 Fujitsu Limited Radio apparatus, radio apparatus controller, and synchronization establishing method
US8472578B2 (en) * 2011-03-30 2013-06-25 Fujitsu Limited Radio apparatus, radio apparatus controller, and synchronization establishing method
US20130249612A1 (en) * 2012-03-26 2013-09-26 Rambus Inc. Method and apparatus for source-synchronous signaling
US10840920B2 (en) 2012-03-26 2020-11-17 Rambus Inc. Method and apparatus for source-synchronous signaling
US10541693B2 (en) 2012-03-26 2020-01-21 Rambus Inc. Method and apparatus for source-synchronous signaling
US8836394B2 (en) * 2012-03-26 2014-09-16 Rambus Inc. Method and apparatus for source-synchronous signaling
US10211841B2 (en) 2012-03-26 2019-02-19 Rambus Inc. Method and apparatus for source-synchronous signaling
US9748960B2 (en) 2012-03-26 2017-08-29 Rambus Inc. Method and apparatus for source-synchronous signaling
US8928370B2 (en) * 2012-10-24 2015-01-06 SK Hynix Inc. Deserializers
US8928371B2 (en) * 2012-10-24 2015-01-06 SK Hynix Inc. Deserializers
US20140344611A1 (en) * 2012-10-24 2014-11-20 SK Hynix Inc. Deserializers
US20140340247A1 (en) * 2012-10-24 2014-11-20 SK Hynix Inc. Deserializers
US8823426B2 (en) * 2012-10-24 2014-09-02 SK Hynix Inc. Deserializers
US20140111256A1 (en) * 2012-10-24 2014-04-24 SK Hynix Inc. Deserializers
US9548855B2 (en) 2013-08-21 2017-01-17 Silab Tech Pvt. Ltd. Method and apparatus for managing estimation and calibration of non-ideality of a phase interpolator (PI)-based clock and data recovery (CDR) circuit
CN107563020A (en) * 2017-08-17 2018-01-09 郑州云海信息技术有限公司 A kind of clock frequency division module design method based on CPLD/FPGA
US10236897B1 (en) * 2018-07-26 2019-03-19 Texas Instruments Incorporated Loss of lock detector

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