US8438453B2 - Low latency read operation for managed non-volatile memory - Google Patents
Low latency read operation for managed non-volatile memory Download PDFInfo
- Publication number
- US8438453B2 US8438453B2 US12/538,053 US53805309A US8438453B2 US 8438453 B2 US8438453 B2 US 8438453B2 US 53805309 A US53805309 A US 53805309A US 8438453 B2 US8438453 B2 US 8438453B2
- Authority
- US
- United States
- Prior art keywords
- data
- read
- host controller
- nvm
- controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
Definitions
- NVM non-volatile memory
- Flash memory is a type of electrically erasable programmable read-only memory (EEPROM). Because flash memories are non-volatile and relatively dense, they are used to store files and other persistent objects in handheld computers, mobile phones, digital cameras, portable music players, and many other devices in which other storage solutions (e.g., magnetic disks) are inappropriate.
- EEPROM electrically erasable programmable read-only memory
- NAND is a type of flash memory that can be accessed like a block device, such as a hard disk or memory card. Each block consists of a number of pages (e.g., 64-128 pages). A typical page size is 4 KB-8 KB bytes. A NAND device can have multiple dies each having 4096-8192 blocks. Associated with each page are a number of bytes (e.g., 12-16 bytes) that are used for storage of error detection and correction checksums. Reading and programming is performed on a page basis, erasure is performed on a block basis, and data in a block can only be written sequentially. NAND relies on Error Correction Code (ECC) to compensate for bits that may flip during normal device operation. When performing erase or program operations, the NAND device can detect blocks that fail to program or erase and mark the blocks as bad in a bad block map. The data can be written to a different, good block, and the bad block map updated.
- ECC Error Correction Code
- Managed NAND devices combine raw NAND with a memory controller to handle error correction and detection, as well as memory management functions of NAND memory.
- Managed NAND is commercially available in Ball Grid Array (BGA) packages, or other Integrated Circuit (IC) package which supports standardized processor interfaces, such as Multimedia Memory Card (MMC) and Secure Digital (SD) card.
- BGA Ball Grid Array
- IC Integrated Circuit
- a managed NAND device can include a number of NAND devices or dies which can be accessed using one or more chip select signals.
- a chip select is a control line used in digital electronics to select one chip out of several chips connected to the same bus.
- the chip select is typically a command pin on most IC packages which connects the input pins on the device to the internal circuitry of that device. When the chip select pin is held in the inactive state, the chip or device ignores changes in the state of its input pins. When the chip select pin is held in the active state, the chip or device responds as if it is the only chip on
- ONFI Open NAND Flash Interface Working Group
- ONFI specification version 1.0 specifies: a standard physical interface (pin-out) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages; a standard command set for reading, writing, and erasing NAND flash chips; and a mechanism for self-identification.
- ONFI specification version 2.0 supports dual channel interfaces, with odd chip selects (also referred to as chip enable or “CE”) connected to channel 1 and even CEs connected to channel 2.
- CE chip enable
- a host controller is coupled to a non-volatile memory (NVM) package (e.g., NAND device).
- NVM non-volatile memory
- the host controller sends a read command to the NVM package requesting a low latency read operation.
- a controller in the NVM package retrieves the data and sends the data to an ECC engine for correcting.
- the host controller sends a read status request command to the controller in the NVM package.
- the controller sends a status report to the host controller indicating that some or all of the data is available for transfer to the host controller. Responsive to the report, the host controller transfers the data.
- an underrun status is determined by the controller in the NVM package and reported to the host controller in response to a read operation status request command sent by the host controller at the end of the read operation.
- the read operation status reported by the NVM package indicates whether there was an underrun, where uncorrected data was transferred to the host controller, as well as whether the data was correctable or uncorrectable. Based on the read operation status, the host controller can take action, such as performing another read operation without regard to low latency.
- An advantage of the disclosed low latency read operations is that corrected portions of requested data can be transferred to the host controller, as compared to conventional non-volatile memory systems where all of the requested data is loaded in a buffer and corrected before any of the data is transferred to the host controller.
- FIG. 1 is a block diagram of an exemplary memory system including a host processor coupled to a managed NVM package.
- FIG. 2 illustrates an exemplary address mapping for the managed NVM package of FIG. 1 .
- FIG. 3 illustrates the address mapping of FIG. 2 including bad block replacement.
- FIG. 4 illustrates an exemplary method of a low latency read of managed non-volatile memory
- FIG. 5 illustrates an exemplary process for determining an underrun status in a low latency read operation.
- FIG. 6 illustrates another exemplary method of a low latency read of managed non-volatile memory
- FIG. 7 is a flow diagram of low latency read operations performed by a host controller.
- FIG. 8 is a flow diagram of low latency read operations performed by an NVM controller.
- FIG. 1 is a block diagram of an exemplary memory system 100 including a host controller 102 coupled to a managed NVM package 104 (e.g., a NAND device).
- the NVM package 104 can be a BGA package or other IC package, including multiple NVM devices 108 (e.g., multiple raw NAND devices).
- the memory system 100 can be used in a variety of devices, including but not limited to: handheld computers, mobile phones, digital cameras, portable music players, toys, thumb drives, email devices, and any other devices in which non-volatile memory is desired or required.
- raw NVM is a memory device or package which is managed by an external host processor
- managed NVM is a memory device or package that includes at least one internal memory management function, such as error correction, wear leveling, bad block management, etc.
- the NVM package 104 can include a controller 106 for accessing and managing the NVM devices 108 over internal channels using internal chip select signals.
- An internal channel is a data path between the controller 106 and a NVM device 108 .
- the controller 106 can perform memory management functions (e.g., wear leveling, bad block management) and can include an error correction (ECC) engine 110 for detecting and correcting data errors (e.g., flipped bits).
- ECC error correction
- the ECC engine 110 can be implemented as a hardware component in the controller 106 or as a software component executed by the controller 106 .
- the ECC engine 110 can be located in the NVM devices 108 .
- the host controller 102 and NVM package 104 can communicate information (e.g., control commands, addresses, data) over a communication channel visible to the host (“host channel”).
- the host channel can support standard interfaces, such as raw NAND interfaces or dual channel interfaces, such as is described in ONFI specification version 2.0.
- the host controller 102 can also provide a host chip enable (CE) signal.
- CE host chip enable
- the NVM package 104 supports CE hiding.
- CE hiding allows the single host CE to be used for each internal channel in the NVM package 104 , thus reducing the number of signals required to support the interface of the NVM package 104 .
- Memory accesses can be mapped to internal channels and the NVM devices 108 using an address space and address mapping, as described in reference to FIGS. 2 and 3 .
- Individual NVM devices 108 can be enabled using internal CE signals generated by the controller 106 .
- FIG. 2 illustrates an exemplary address mapping for the managed NVM package 104 of FIG. 1 .
- the mapping can be used with managed NAND devices that include multiple dies, where each die can potentially include multiple planes.
- the address mapping operates on Concurrently Addressable Units (CAUs).
- CAUs Concurrently Addressable Units
- a CAU is a portion of physical storage accessible from a single host channel that may be read, programmed or erased simultaneously to, or in parallel with other CAUs in the NVM package.
- a CAU can be, for example, a single plane or a single die.
- a CAU size is the number of erasable blocks in a CAU.
- a block size is defined as a number of pages in an erasable block.
- 16 bytes of metadata are available for each 4 kilobytes of data.
- Other memory architectures are also possible.
- the metadata can be allocated more or fewer bytes.
- the address mapping shown in FIG. 2 allows the use of raw NAND protocol to read/program/erase NAND blocks and additional commands that enable optimized performance.
- the NVM package 104 includes an ECC engine (e.g., ECC engine 110 ) for managing data reliability of the NAND.
- ECC engine 110 e.g., ECC engine 110
- the host controller 102 does not need to include an ECC engine 110 or otherwise process data for reliability purposes.
- the NVM package 104 defines a CAU as an area that can be accessed (e.g., moving data from the NAND memory cells to an internal register) simultaneous to, or in parallel with, other CAUs.
- CAUs can have a different numbers of blocks. Table I below describes a exemplary row address format for accessing a page in a CAU.
- an exemplary n-bit (e.g., 24 bits) row address can be presented to a controller in the NAND device in the following format: [CAU: Block: Page].
- CAU is a number (e.g., an integer) that represents a die or plane.
- Block is a block offset in the CAU identified by the CAU number
- Page is a page offset in the block identified by Block.
- Z will be 3 (22 ⁇ 6 ⁇ 23).
- the exemplary NVM package 104 shown in FIG. 2 includes two NAND dies 204 a , 204 b , and each die has two planes.
- die 204 a includes planes 206 a , 206 b .
- die 204 b includes planes 206 c , 206 d .
- each plane is CAU and each CAU has 2048 multi-level cell (MLC) blocks with 128 pages per block.
- MLC multi-level cell
- Program and erase operations can be performed on a stride of blocks (a block from each CAU).
- a stride is defined as an array of blocks each coming from a different CAU.
- a “stride 0 ” defines a block 0 from each of CAUs 0 - 3
- a “stride 1 ” defines a block 1 from each of CAUs 0 - 3
- a “stride 2 ” defines a block 2 from each of CAUs 0 - 3 and so forth.
- the NVM package includes an NVM controller 202 , which communicates with the CAUs through control bus 208 and address/data bus 210 .
- the NVM controller 202 receives commands from the host controller (not shown) and in response to the command asserts control signals on the control bus 208 and addresses or data on the address/data bus 210 to perform an operation (e.g., read, program, or erase operation) on one or more CAUs.
- the command includes a row address having the form [CAU: Block: Page], as described in reference to FIG. 2 .
- FIG. 3 illustrates the address mapping of FIG. 2 including bad block replacement.
- the host controller 102 has issued a stride address for an NVM package 104 including three CAUs, where one of the CAUs holds a bad block in the stride block offset.
- a “stride 4 ” address would normally access CAU 0 : Block 4 , CAU 1 : Block 4 and CAU 2 : Block 4 .
- the bad block CAU 1 : Block 4 is replaced by CAU 1 : Block 2000 .
- FIG. 4 illustrates an exemplary method of a low latency read operation for managed non-volatile memory.
- a low latency read status function allows the host controller to start transferring bytes of data following a read operation as soon as portions of a page of data are ready. This read status operation indicates when the first portion of the data is ready. Assuming that the host controller and NVM controller busses use similar timing and that the ECC procedure does not significantly impact latency throughout the read operation, starting the transfer of an ECC segment as soon as the segment is ready can provide a significant latency improvement.
- the host controller can read a status provided by the NVM controller before and after transferring the data.
- the protocol can specify as an illegal condition having two pending commands executed using the same row address.
- Table II describes exemplary information returned by the operation read status function described above. An 8-bit return value is assumed for this example.
- the NVM controller if the NVM controller returns a “0”, then there was an ECC delay.
- the host controller read a portion of a page before the portion was processed by the ECC engine. If this condition occurs, the host controller can use the operation read status and potentially reread the page. If the NVM controller returns a “1”, the data was improperly read from the NVM package. The host controller can issue another read status command for additional status information. Other information can be returned in a status from the NVM package as desired.
- FIG. 4 what is shown are four stacked rows of low latency read events performed during a low latency read operation by an internal bus, an NVM controller, a low latency external bus and a normal external bus. Time increases along the x-axis from left to right.
- the internal bus and NVM controller are located in the NVM package (e.g., a NAND device).
- the low latency and normal external buses couple the host controller (e.g., host controller 102 ) to the NVM package.
- a low latency read command is sent from the host controller to the NVM controller over the low latency external bus.
- the read command is processed by the NVM controller.
- the NVM device includes three CAUs, which can be accessed using the map addressing described in reference to FIG. 2 .
- the NVM controller begins processing ECC segments of data read from the CAUs.
- the segments of data (e.g., one or more pages) are transferred from memory cells to a buffer.
- An ECC segment can be defined as a correctable unit size that includes data plus metadata. Once the segment is in the buffer, the segment can be processed by the ECC engine and an indication of whether the segment is corrected or uncorrectable by the ECC engine can be recorded.
- the host controller After the host controller issues a read command, the host controller issues a low latency status request command (“LL status”) to the NVM controller to determine if an ECC segment is available.
- the NVM controller responds with a status indicating that an ECC segment is available for transfer to the host controller or an error code indicating that there was a problem with the data. If the status indicates that an ECC segment is available, the host controller issues an external transfer command (“Ext Xfer”) to transfer the ECC segment to the host controller over the external bus. This process repeats itself until there are no more ECC segments indicating that the read operation is complete. If the status indicates an error, then a normal process for handling bad data can be performed (e.g., bad block replacement).
- a segment of data is transferred on the external bus without being first processed by the ECC engine because the ECC engine could not complete the ECC process in time for the external transfer to the host controller. This is referred to as an “underrun.”
- the host controller issues a final status request command to determine if data was transferred that did not receive ECC processing or if any bad data was uncorrectable. If the NVM controller provides a status indicating an underrun or that the segment includes bad data that could not be corrected, then the host controller and NVM controller perform a normal read operation using the normal external bus protocol.
- a normal read operation results in the data to be read to be transferred in its entirety to a buffer. The entire buffer of data is then processed by the ECC engine before being transferred on the normal external bus to the host controller. The normal read operation is illustrated by the bottom row in FIG. 4 .
- FIG. 5 illustrates an exemplary process for determining an underrun status in a low latency read operation.
- two pointers are maintained: a host read byte pointer 502 and a highest address valid byte pointer 504 .
- the pointer 502 can be implemented using an n-bit flip-flop.
- the pointer 502 increments in host bus width chunks (e.g., increments in bytes).
- the pointer 502 can be initialized to the Page offset address specified in the row address [CAU: Bock: Page] included in the read command sent by the host controller.
- the pointer 504 can also be implemented using an n-bit flip-flop.
- the pointer 504 increments in ECC segments.
- the pointer 504 increments when an ECC segment is known to be corrected or uncorrectable.
- the pointers 502 , 504 can be compared by a comparator 506 to determine if the value of pointer 502 is greater than the value of pointer 504 , indicating an underrun. If an underrun is detected, then an underrun flip-flop can be set to “1”. In this example, it is assumed that the underrun flip-flop was initialized to “0”. There are four outcomes for the underrun logic, which are listed in Table III below.
- the read operation will proceed as normal. If there is no underrun and the data is good, then the read operation will proceed as normal. If there is no underrun and there is bad data that is uncorrectable, then the read operation can proceed as normal (e.g., perform bad block replacement). If there is an underrun and the data is good, the read operation can be retried without performing an early transfer of ECC segments to the host controller. If there is an underrun and the data is uncorrectable, then the read operation can proceed as normal or retried.
- FIG. 6 illustrates another exemplary method of low latency read of managed non-volatile memory.
- FIG. 6 is similar in form to FIG. 5 and should be interpreted the same as FIG. 5 .
- a read command is sent to the NVM controller over an external low latency bus.
- the read command is transferred to the NVM controller over an internal bus.
- the NVM controller transfers the requested data into a buffer and performs ECC operations on the data in the buffer.
- a read status command is sent to the NVM controller.
- the NVM controller returns a status indicating a number of ECC segments that are available for transfer to the host controller.
- the host controller initiates the transfer of the available ECC segments. After completion of the transfer, a final read status is requested by the host processor.
- the method illustrated in FIG. 6 allows for transfer ECC segments as soon as the segments are ready. Since the data is not allowed to be transferred until the data has been processed by the ECC engine, an underrun cannot occur using this method.
- FIG. 7 is a flow diagram of low latency read operations 700 , 722 performed by a host controller (e.g., host controller 102 ).
- the process 700 is also referred to as Method A (Host), and the process 722 is also referred to as Method B (Host).
- the process 700 begins when the host controller sends a read command to an NVM controller ( 702 ). Following the read command, the host controller sends a read status request command to the NVM controller ( 704 ). The host controller receives a status report from the NVM controller ( 706 ). The status report indicates whether an ECC segment is ready for transfer ( 708 ). If the ECC segment is not ready for transfer, the process 700 returns to step 704 . Otherwise, data is read from the NVM package ( 710 ) and sent to the host controller.
- process 700 reports ready ECC segments of data for transfer, and the host controller transfers only the data that has be corrected or found to be uncorrectable.
- the process 722 begins when the host controller sends a read command to an NVM controller ( 724 ). Following the read command, the host controller sends a read status request command to the NVM controller ( 726 ). The host controller receives a status report from the NVM controller ( 728 ). The status report indicates whether an ECC segment is ready for early transfer ( 730 ). If the ECC segment is not ready for early transfer, then the process 722 returns to step 726 . Otherwise, the ECC segment is read from the device ( 732 ) and transferred to the host controller. The host controller requests read status to determine if there is an uncorrectable ECC segment or an underrun ( 734 ).
- the host controller receives a status from the NVM controller ( 736 ). A determination is made as to whether an underrun occurred or an uncorrectable ECC ( 738 ). If there was an underrun, then the host controller performs a normal read operation (an operation at normal latency) with no early transfer of data to the host controller ( 740 ). If there is an uncorrectable ECC ( 742 ), then an uncorrectable ECC policy is performed ( 744 ). Otherwise the process 722 terminates.
- Process 722 also includes a method for determining if the host controller ran ahead of the NVM controller ECC processing of the data, which is referred to as an “underrun.”
- FIG. 8 is a flow diagram of low latency read operations 800 , 816 performed by an NVM controller.
- the process 800 is also referred to as Method A (Device) and the process 816 is also referred to as Method B (Device).
- the process 800 begins when the NVM controller receives a read command ( 802 ). Responsive to the read command, the NVM controller reads an ECC segment (also referred to as a “chunk”) into an internal buffer ( 804 ). The contents of the buffer are processed by an ECC engine to correct the ECC segment ( 806 ). In some implementations, a next ECC segment can be read while the current ECC segment is being processed by the ECC engine.
- the NVM controller receives a read status request and responds to the request by reporting data available for transfer ( 808 ).
- the report can include a number of bytes ready for transfer or an uncorrectable ECC state for the next chunk.
- a determination is made as to whether the transfer is complete ( 810 ). If the transfer is complete, and in response to a final status request by the host controller, the NVM controller provides a report of correctable/uncorrectable status to the host controller ( 814 ). Otherwise, data is transferred to the host controller ( 812 ) and the process 800 returns to step 808 . In some implementations, the data is transferred concurrently with the read loop on the host request described in step 806 . There is no underrun for process 800 by design.
- the process 816 begins when the NVM controller receives a read command ( 818 ). Responsive to the read command, the NVM controller reads an ECC segment/chunk into an internal buffer ( 820 ). The contents of the buffer are processed by an ECC engine to correct the ECC segment ( 822 ). In some implementations, a next ECC segment can be read while the current ECC segment is being processed by the ECC engine.
- a determination is made as to whether there is enough data for early transfer ( 824 ). Responsive to a read status request command from the host controller, a report is provided by the NVM controller that early transfer of data can begin ( 826 ). Data is transferred to the host controller ( 828 ). In some implementations, the data can be transferred concurrently with the read loop on the host request described in step 822 . Responsive to a final read status request command from the host controller, the NVM controller reports underrun status and correctable/uncorrectable status to the host controller ( 830 ).
Abstract
Description
TABLE I |
Exemplary Row Address Format |
R[X + Y:X + Z − 1] | R[X:X + Y − 1] | R[0:X − 1] |
CAU | Block | Page |
TABLE II |
Exemplary Return Information For Operation Read Status |
Bit | Read |
0 | 1 - ECC delay (host read areas of the page |
before it was ready). User should use the | |
operation read status and potentially | |
reread the page. | |
1 | 1 - Data was properly read from the |
device. User should use operation read | |
status for |
|
2 | Reserved |
3 | |
4 | |
5 | |
6 | 1 - Data is ready to begin |
7 | Reserved |
TABLE III |
Exemplary Outcomes and Actions For Underrun Process |
Outcomes | Actions |
No Underrun, data OK | Proceed as normal |
No Underrun, data uncorrectable | Proceed as normal |
Underrun, data OK | Retry, ignore early-transfer start bit |
Underrun, data uncorrectable | Proceed as normal, or retry |
Claims (22)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/538,053 US8438453B2 (en) | 2009-05-06 | 2009-08-07 | Low latency read operation for managed non-volatile memory |
KR1020117029103A KR101382060B1 (en) | 2009-05-06 | 2010-04-27 | Low latency read operation for managed non-volatile memory |
CN201080019952.8A CN102414666B (en) | 2009-05-06 | 2010-04-27 | Low latency read operation for managed non-volatile memory |
PCT/US2010/032627 WO2010129305A1 (en) | 2009-05-06 | 2010-04-27 | Low latency read operation for managed non-volatile memory |
JP2012509840A JP5591917B2 (en) | 2009-05-06 | 2010-04-27 | Low latency read operation for managed non-volatile memory |
EP10719683.4A EP2427824B1 (en) | 2009-05-06 | 2010-04-27 | Low latency read operation for managed non-volatile memory |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17605509P | 2009-05-06 | 2009-05-06 | |
US12/538,053 US8438453B2 (en) | 2009-05-06 | 2009-08-07 | Low latency read operation for managed non-volatile memory |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100287446A1 US20100287446A1 (en) | 2010-11-11 |
US8438453B2 true US8438453B2 (en) | 2013-05-07 |
Family
ID=42308338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/538,053 Active 2031-01-05 US8438453B2 (en) | 2009-05-06 | 2009-08-07 | Low latency read operation for managed non-volatile memory |
Country Status (6)
Country | Link |
---|---|
US (1) | US8438453B2 (en) |
EP (1) | EP2427824B1 (en) |
JP (1) | JP5591917B2 (en) |
KR (1) | KR101382060B1 (en) |
CN (1) | CN102414666B (en) |
WO (1) | WO2010129305A1 (en) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120311408A1 (en) * | 2011-06-03 | 2012-12-06 | Sony Corporation | Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program |
US8612791B2 (en) | 2009-09-16 | 2013-12-17 | Apple Inc. | Method of selective power cycling of components in a memory device independently by turning off power to a memory array or memory controller |
US20140089760A1 (en) * | 2011-12-14 | 2014-03-27 | Jonathan E. Schmidt | Storage of codeword portions |
US20150143035A1 (en) * | 2013-11-21 | 2015-05-21 | Samsung Electronics Co., Ltd. | User device having a host flash translation layer (ftl), a method for transferring an erase count thereof, a method for transferring reprogram information thereof, and a method for transferring a page offset of an open block thereof |
US9368166B2 (en) | 2013-01-18 | 2016-06-14 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices, memory systems, and control methods using simultaneous recovery and output operations |
US20160232088A1 (en) * | 2014-07-17 | 2016-08-11 | Sandisk Enterprise Ip Llc | Garbage Collection in Storage System with Distributed Processors |
US9489253B2 (en) | 2013-11-27 | 2016-11-08 | Samsung Electronics Co., Ltd. | Memory controller and method of operating memory controller for reading data from memory device at high speed |
US20170039001A1 (en) * | 2015-08-06 | 2017-02-09 | Stmicroelectronics (Rousset) Sas | Method for Writing in an EEPROM Memory and Corresponding Memory |
US9653184B2 (en) | 2014-06-16 | 2017-05-16 | Sandisk Technologies Llc | Non-volatile memory module with physical-to-physical address remapping |
US9720624B2 (en) | 2014-02-05 | 2017-08-01 | Samsung Electronics Co., Ltd. | Method of controlling a memory system |
US9880748B2 (en) | 2015-02-13 | 2018-01-30 | Qualcomm Incorporated | Bifurcated memory management for memory elements |
US10090858B2 (en) | 2015-12-14 | 2018-10-02 | Samsung Electronics Co., Ltd. | Storage device and operating method of storage device |
US10296233B2 (en) | 2015-02-11 | 2019-05-21 | Samsung Electronics Co., Ltd. | Method of managing message transmission flow and storage device using the method |
US11049581B2 (en) * | 2018-09-28 | 2021-06-29 | Toshiba Memory Corporation | Media error reporting improvements for storage drives |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8370603B2 (en) | 2008-12-23 | 2013-02-05 | Apple Inc. | Architecture for address mapping of managed non-volatile memory |
JP5651457B2 (en) * | 2010-12-15 | 2015-01-14 | 株式会社東芝 | Semiconductor memory device |
US8738882B2 (en) | 2011-06-03 | 2014-05-27 | Apple Inc. | Pre-organization of data |
US8656251B2 (en) * | 2011-09-02 | 2014-02-18 | Apple Inc. | Simultaneous data transfer and error control to reduce latency and improve throughput to a host |
US9652376B2 (en) * | 2013-01-28 | 2017-05-16 | Radian Memory Systems, Inc. | Cooperative flash memory control |
MY180992A (en) * | 2013-03-13 | 2020-12-15 | Intel Corp | Memory latency management |
US9690953B2 (en) * | 2013-03-14 | 2017-06-27 | Apple Inc. | Generating efficient reads for a system having non-volatile memory |
KR20150135311A (en) | 2013-03-25 | 2015-12-02 | 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. | Memory device having error correction logic |
US9262263B2 (en) | 2013-11-25 | 2016-02-16 | Qualcomm Incorporated | Bit recovery system |
US9378081B2 (en) | 2014-01-02 | 2016-06-28 | Qualcomm Incorporated | Bit remapping system |
US9323610B2 (en) * | 2014-01-30 | 2016-04-26 | Sandisk Technologies Inc. | Non-blocking commands |
US9454422B2 (en) | 2014-01-30 | 2016-09-27 | International Business Machines Corporation | Error feedback and logging with memory on-chip error checking and correcting (ECC) |
US9367392B2 (en) | 2014-08-01 | 2016-06-14 | Winbond Electronics Corporation | NAND flash memory having internal ECC processing and method of operation thereof |
US9811420B2 (en) * | 2015-03-27 | 2017-11-07 | Intel Corporation | Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) |
CN107783727B (en) * | 2016-08-31 | 2022-01-14 | 华为技术有限公司 | Access method, device and system of memory device |
KR20180078864A (en) | 2016-12-30 | 2018-07-10 | 에스케이하이닉스 주식회사 | Memory system and operation method of the same |
ES2840423T3 (en) * | 2017-06-23 | 2021-07-06 | Huawei Tech Co Ltd | Memory access technology and computer system |
US11307929B2 (en) * | 2019-06-17 | 2022-04-19 | Micron Technology, Inc. | Memory device with status feedback for error correction |
US11194643B1 (en) * | 2020-06-03 | 2021-12-07 | Micron Technology, Inc. | Access operation status signaling for memory systems |
Citations (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4937830A (en) * | 1987-05-19 | 1990-06-26 | Fujitsu Limited | Semiconductor memory device having function of checking and correcting error of read-out data |
US5341489A (en) | 1992-04-14 | 1994-08-23 | Eastman Kodak Company | Memory card with programmable interleaving |
US5434872A (en) * | 1992-07-28 | 1995-07-18 | 3Com Corporation | Apparatus for automatic initiation of data transmission |
US5524218A (en) * | 1993-12-23 | 1996-06-04 | Unisys Corporation | Dedicated point to point fiber optic interface |
US5559449A (en) | 1994-02-18 | 1996-09-24 | Sgs-Thomson Microelectronics S.R.L. | Programmable logic array structure for semiconductor nonvolatile memories, particularly flash-eeproms |
US5613144A (en) | 1994-12-20 | 1997-03-18 | National Semiconductor Corporation | Serial register multi-input multiplexing architecture for multiple chip processor |
US5615162A (en) | 1995-01-04 | 1997-03-25 | Texas Instruments Incorporated | Selective power to memory |
US5673223A (en) | 1995-06-09 | 1997-09-30 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device with multiple word line voltage generators |
US5751631A (en) | 1996-10-21 | 1998-05-12 | Liu; David K. Y. | Flash memory cell and a new method for sensing the content of the new memory cell |
US6092158A (en) | 1997-06-13 | 2000-07-18 | Intel Corporation | Method and apparatus for arbitrating between command streams |
US6134149A (en) | 1999-03-01 | 2000-10-17 | Integrated Memory Technologies, Inc. | Method and apparatus for reducing high current during chip erase in flash memories |
US6148354A (en) * | 1999-04-05 | 2000-11-14 | M-Systems Flash Disk Pioneers Ltd. | Architecture for a universal serial bus-based PC flash disk |
US6449111B1 (en) * | 1995-09-01 | 2002-09-10 | Adaptec, Inc. | Data frame write and read processes |
US20020194451A1 (en) | 2001-06-19 | 2002-12-19 | Tdk Corporation | Memory controller, flash memory system employing memory controller and method for controlling flash memory device |
US20030046628A1 (en) | 2001-09-06 | 2003-03-06 | Rankin Linda J. | Error method, system and medium |
US20030200411A1 (en) | 1999-10-21 | 2003-10-23 | Takuji Maeda | Semiconductor memory card access apparatus, a computer-readable recording medium, an initialization method, and a semiconductor memory card |
US6684301B1 (en) | 2001-05-31 | 2004-01-27 | Lsi Logic Corporation | Out of order execution memory access request FIFO |
US20040139286A1 (en) | 2003-01-15 | 2004-07-15 | Frank Lin | Method and related apparatus for reordering access requests used to access main memory of a data processing system |
US20040153902A1 (en) * | 2003-01-21 | 2004-08-05 | Nexflash Technologies, Inc. | Serial flash integrated circuit having error detection and correction |
US20040257888A1 (en) * | 2003-04-22 | 2004-12-23 | Kabushiki Kaisha Toshiba | Data storage system |
US20050166007A1 (en) | 2004-01-27 | 2005-07-28 | Seiko Epson Corporation | Information processing apparatus and method of accessing memory |
US20060039196A1 (en) * | 2003-10-03 | 2006-02-23 | Gorobets Sergey A | Corrected data storage and handling methods |
US20060059406A1 (en) * | 2004-09-10 | 2006-03-16 | Stmicroelectronics S.R.L. | Memory with embedded error correction codes |
US20060164907A1 (en) | 2003-07-22 | 2006-07-27 | Micron Technology, Inc. | Multiple flash memory device management |
US20060248432A1 (en) | 2005-04-28 | 2006-11-02 | International Business Machines Corporation | Method and apparatus for implementing processor bus speculative data completion |
US20070043900A1 (en) | 2005-08-20 | 2007-02-22 | Samsung Electronics Co., Ltd. | Flash memory management method and flash memory system |
US20070050668A1 (en) * | 2005-09-01 | 2007-03-01 | Micron Technology, Inc. | Test mode to force generation of all possible correction codes in an ECC memory |
US20070106919A1 (en) | 2002-10-28 | 2007-05-10 | Sandisk Corporation | Power Management Block for Use in a Non-Volatile Memory System |
US20070136512A1 (en) * | 1998-11-04 | 2007-06-14 | Toombs Thomas N | Voltage Negotiation in a Single Host Multiple Cards System |
US20070140007A1 (en) | 2005-12-21 | 2007-06-21 | Nec Electronics Corporation | Flash memory, memory control circuit, microcomputer and memory control method |
US20070165458A1 (en) | 2006-01-17 | 2007-07-19 | Nancy Leong | Random cache read using a double memory |
US20070168625A1 (en) | 2006-01-18 | 2007-07-19 | Cornwell Michael J | Interleaving policies for flash memory |
US20070271494A1 (en) * | 2006-05-17 | 2007-11-22 | Sandisk Corporation | Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices |
US20080069098A1 (en) | 2006-09-15 | 2008-03-20 | Shah Mehul A | Group communication system and method |
US7372715B2 (en) | 2006-06-14 | 2008-05-13 | Micron Technology, Inc. | Architecture and method for NAND flash memory |
US20080126776A1 (en) | 2006-11-27 | 2008-05-29 | Fujifilm Corporation | Electronic apparatus |
US20080147994A1 (en) | 2006-12-18 | 2008-06-19 | Samsung Electronics Co., Ltd. | Command scheduling method and apparatus of virtual file system embodied in nonvolatile data storage device |
US20080147968A1 (en) | 2000-01-06 | 2008-06-19 | Super Talent Electronics, Inc. | High Performance Flash Memory Devices (FMD) |
US20080195799A1 (en) | 2007-02-13 | 2008-08-14 | Samsung Electronics Co., Ltd. | Systems, methods and computer program products for operating a data processing system in which a file delete command is sent to an external storage device for invalidating data thereon |
US20080211303A1 (en) | 2006-12-22 | 2008-09-04 | Canon Kabushiki Kaisha | Interface circuit |
US20080288814A1 (en) * | 2007-05-16 | 2008-11-20 | Jun Kitahara | Apparatus for detecting and recovering from data destruction caused in an unaccessed memory cell by read, and method therefor |
US20090019340A1 (en) * | 2005-04-28 | 2009-01-15 | Micron Technology | Non-systematic coded error correction |
US20090063934A1 (en) * | 2007-08-28 | 2009-03-05 | Samsung Electronics Co., Ltd. | Multi-channel memory system including error correction decoder architecture with efficient area utilization |
US20090100115A1 (en) | 2007-10-12 | 2009-04-16 | Samsung Electronics Co., Ltd. | Methods and Apparatus for File Management Using Partitioned File Metadata |
US20090113114A1 (en) | 2007-10-26 | 2009-04-30 | Berenbaum Alan D | Implementation of One Time Programmable Memory with Embedded Flash Memory in a System-on-Chip |
US20090125785A1 (en) * | 2004-05-13 | 2009-05-14 | Sergey Anatolievich Gorobets | Pipelined Data Relocation and Improved Chip Architectures |
US20090164698A1 (en) | 2007-12-24 | 2009-06-25 | Yung-Li Ji | Nonvolatile storage device with NCQ supported and writing method for a nonvolatile storage device |
US20090198947A1 (en) | 2008-02-04 | 2009-08-06 | Apple Inc. | Memory Mapping Restore and Garbage Collection Operations |
US20090265513A1 (en) * | 2005-01-11 | 2009-10-22 | Samsung Electronics Co., Ltd. | Solid state disk controller apparatus |
US20100250836A1 (en) * | 2009-03-25 | 2010-09-30 | Anobit Technologies Ltd | Use of Host System Resources by Memory Controller |
US20100287329A1 (en) | 2009-05-06 | 2010-11-11 | Apple Inc. | Partial Page Operations for Non-Volatile Memory Systems |
US20100287353A1 (en) | 2009-05-06 | 2010-11-11 | Apple Inc. | Multipage Preparation Commands for Non-Volatile Memory Systems |
US20110153911A1 (en) | 2009-12-18 | 2011-06-23 | Steven Sprouse | Method and system for achieving die parallelism through block interleaving |
US7975109B2 (en) | 2007-05-30 | 2011-07-05 | Schooner Information Technology, Inc. | System including a fine-grained memory and a less-fine-grained memory |
US7979658B2 (en) | 2008-03-25 | 2011-07-12 | Spansion Llc | Secure management of memory regions in a memory |
US20110213945A1 (en) | 2010-02-26 | 2011-09-01 | Apple Inc. | Data partitioning scheme for non-volatile memories |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4105819B2 (en) * | 1999-04-26 | 2008-06-25 | 株式会社ルネサステクノロジ | Storage device and memory card |
US20040083334A1 (en) * | 2002-10-28 | 2004-04-29 | Sandisk Corporation | Method and apparatus for managing the integrity of data in non-volatile memory system |
JP4595342B2 (en) * | 2004-02-19 | 2010-12-08 | 日本電気株式会社 | Data writing / reading method for storage device and data storage system |
US7424648B2 (en) * | 2005-03-10 | 2008-09-09 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile memory system, nonvolatile memory device, data read method, and data read program |
-
2009
- 2009-08-07 US US12/538,053 patent/US8438453B2/en active Active
-
2010
- 2010-04-27 CN CN201080019952.8A patent/CN102414666B/en not_active Expired - Fee Related
- 2010-04-27 EP EP10719683.4A patent/EP2427824B1/en active Active
- 2010-04-27 WO PCT/US2010/032627 patent/WO2010129305A1/en active Application Filing
- 2010-04-27 JP JP2012509840A patent/JP5591917B2/en not_active Expired - Fee Related
- 2010-04-27 KR KR1020117029103A patent/KR101382060B1/en active IP Right Grant
Patent Citations (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4937830A (en) * | 1987-05-19 | 1990-06-26 | Fujitsu Limited | Semiconductor memory device having function of checking and correcting error of read-out data |
US5341489A (en) | 1992-04-14 | 1994-08-23 | Eastman Kodak Company | Memory card with programmable interleaving |
US5732094A (en) * | 1992-07-28 | 1998-03-24 | 3Com Corporation | Method for automatic initiation of data transmission |
US5434872A (en) * | 1992-07-28 | 1995-07-18 | 3Com Corporation | Apparatus for automatic initiation of data transmission |
US5524218A (en) * | 1993-12-23 | 1996-06-04 | Unisys Corporation | Dedicated point to point fiber optic interface |
US5559449A (en) | 1994-02-18 | 1996-09-24 | Sgs-Thomson Microelectronics S.R.L. | Programmable logic array structure for semiconductor nonvolatile memories, particularly flash-eeproms |
US5613144A (en) | 1994-12-20 | 1997-03-18 | National Semiconductor Corporation | Serial register multi-input multiplexing architecture for multiple chip processor |
US5615162A (en) | 1995-01-04 | 1997-03-25 | Texas Instruments Incorporated | Selective power to memory |
US5673223A (en) | 1995-06-09 | 1997-09-30 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device with multiple word line voltage generators |
US6449111B1 (en) * | 1995-09-01 | 2002-09-10 | Adaptec, Inc. | Data frame write and read processes |
US5751631A (en) | 1996-10-21 | 1998-05-12 | Liu; David K. Y. | Flash memory cell and a new method for sensing the content of the new memory cell |
US6092158A (en) | 1997-06-13 | 2000-07-18 | Intel Corporation | Method and apparatus for arbitrating between command streams |
US7374108B2 (en) * | 1998-11-04 | 2008-05-20 | Sandisk Corporation | Write protection and use of erase tags in a single host multiple cards system |
US20070136512A1 (en) * | 1998-11-04 | 2007-06-14 | Toombs Thomas N | Voltage Negotiation in a Single Host Multiple Cards System |
US6134149A (en) | 1999-03-01 | 2000-10-17 | Integrated Memory Technologies, Inc. | Method and apparatus for reducing high current during chip erase in flash memories |
US6148354A (en) * | 1999-04-05 | 2000-11-14 | M-Systems Flash Disk Pioneers Ltd. | Architecture for a universal serial bus-based PC flash disk |
US20030200411A1 (en) | 1999-10-21 | 2003-10-23 | Takuji Maeda | Semiconductor memory card access apparatus, a computer-readable recording medium, an initialization method, and a semiconductor memory card |
US20080147968A1 (en) | 2000-01-06 | 2008-06-19 | Super Talent Electronics, Inc. | High Performance Flash Memory Devices (FMD) |
US6684301B1 (en) | 2001-05-31 | 2004-01-27 | Lsi Logic Corporation | Out of order execution memory access request FIFO |
US20020194451A1 (en) | 2001-06-19 | 2002-12-19 | Tdk Corporation | Memory controller, flash memory system employing memory controller and method for controlling flash memory device |
US20030046628A1 (en) | 2001-09-06 | 2003-03-06 | Rankin Linda J. | Error method, system and medium |
US20070106919A1 (en) | 2002-10-28 | 2007-05-10 | Sandisk Corporation | Power Management Block for Use in a Non-Volatile Memory System |
US20040139286A1 (en) | 2003-01-15 | 2004-07-15 | Frank Lin | Method and related apparatus for reordering access requests used to access main memory of a data processing system |
US20040153902A1 (en) * | 2003-01-21 | 2004-08-05 | Nexflash Technologies, Inc. | Serial flash integrated circuit having error detection and correction |
US20040257888A1 (en) * | 2003-04-22 | 2004-12-23 | Kabushiki Kaisha Toshiba | Data storage system |
US20060164907A1 (en) | 2003-07-22 | 2006-07-27 | Micron Technology, Inc. | Multiple flash memory device management |
US20060039196A1 (en) * | 2003-10-03 | 2006-02-23 | Gorobets Sergey A | Corrected data storage and handling methods |
US20050166007A1 (en) | 2004-01-27 | 2005-07-28 | Seiko Epson Corporation | Information processing apparatus and method of accessing memory |
US20090125785A1 (en) * | 2004-05-13 | 2009-05-14 | Sergey Anatolievich Gorobets | Pipelined Data Relocation and Improved Chip Architectures |
US20060059406A1 (en) * | 2004-09-10 | 2006-03-16 | Stmicroelectronics S.R.L. | Memory with embedded error correction codes |
US20090265513A1 (en) * | 2005-01-11 | 2009-10-22 | Samsung Electronics Co., Ltd. | Solid state disk controller apparatus |
US20060248432A1 (en) | 2005-04-28 | 2006-11-02 | International Business Machines Corporation | Method and apparatus for implementing processor bus speculative data completion |
US20090019340A1 (en) * | 2005-04-28 | 2009-01-15 | Micron Technology | Non-systematic coded error correction |
US20070043900A1 (en) | 2005-08-20 | 2007-02-22 | Samsung Electronics Co., Ltd. | Flash memory management method and flash memory system |
US20070050668A1 (en) * | 2005-09-01 | 2007-03-01 | Micron Technology, Inc. | Test mode to force generation of all possible correction codes in an ECC memory |
US20070140007A1 (en) | 2005-12-21 | 2007-06-21 | Nec Electronics Corporation | Flash memory, memory control circuit, microcomputer and memory control method |
US20070165458A1 (en) | 2006-01-17 | 2007-07-19 | Nancy Leong | Random cache read using a double memory |
US20070168625A1 (en) | 2006-01-18 | 2007-07-19 | Cornwell Michael J | Interleaving policies for flash memory |
US20070271494A1 (en) * | 2006-05-17 | 2007-11-22 | Sandisk Corporation | Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices |
US7372715B2 (en) | 2006-06-14 | 2008-05-13 | Micron Technology, Inc. | Architecture and method for NAND flash memory |
US20080069098A1 (en) | 2006-09-15 | 2008-03-20 | Shah Mehul A | Group communication system and method |
US20080126776A1 (en) | 2006-11-27 | 2008-05-29 | Fujifilm Corporation | Electronic apparatus |
US20080147994A1 (en) | 2006-12-18 | 2008-06-19 | Samsung Electronics Co., Ltd. | Command scheduling method and apparatus of virtual file system embodied in nonvolatile data storage device |
US20080211303A1 (en) | 2006-12-22 | 2008-09-04 | Canon Kabushiki Kaisha | Interface circuit |
US20080195799A1 (en) | 2007-02-13 | 2008-08-14 | Samsung Electronics Co., Ltd. | Systems, methods and computer program products for operating a data processing system in which a file delete command is sent to an external storage device for invalidating data thereon |
US20080288814A1 (en) * | 2007-05-16 | 2008-11-20 | Jun Kitahara | Apparatus for detecting and recovering from data destruction caused in an unaccessed memory cell by read, and method therefor |
US7975109B2 (en) | 2007-05-30 | 2011-07-05 | Schooner Information Technology, Inc. | System including a fine-grained memory and a less-fine-grained memory |
US20090063934A1 (en) * | 2007-08-28 | 2009-03-05 | Samsung Electronics Co., Ltd. | Multi-channel memory system including error correction decoder architecture with efficient area utilization |
US20090100115A1 (en) | 2007-10-12 | 2009-04-16 | Samsung Electronics Co., Ltd. | Methods and Apparatus for File Management Using Partitioned File Metadata |
US20090113114A1 (en) | 2007-10-26 | 2009-04-30 | Berenbaum Alan D | Implementation of One Time Programmable Memory with Embedded Flash Memory in a System-on-Chip |
US20090164698A1 (en) | 2007-12-24 | 2009-06-25 | Yung-Li Ji | Nonvolatile storage device with NCQ supported and writing method for a nonvolatile storage device |
US20090198902A1 (en) | 2008-02-04 | 2009-08-06 | Apple Inc. | Memory mapping techniques |
US20090198952A1 (en) | 2008-02-04 | 2009-08-06 | Apple Inc | Memory Mapping Architecture |
US20090198947A1 (en) | 2008-02-04 | 2009-08-06 | Apple Inc. | Memory Mapping Restore and Garbage Collection Operations |
US7979658B2 (en) | 2008-03-25 | 2011-07-12 | Spansion Llc | Secure management of memory regions in a memory |
US20100250836A1 (en) * | 2009-03-25 | 2010-09-30 | Anobit Technologies Ltd | Use of Host System Resources by Memory Controller |
US20100287329A1 (en) | 2009-05-06 | 2010-11-11 | Apple Inc. | Partial Page Operations for Non-Volatile Memory Systems |
US20100287353A1 (en) | 2009-05-06 | 2010-11-11 | Apple Inc. | Multipage Preparation Commands for Non-Volatile Memory Systems |
US20110153911A1 (en) | 2009-12-18 | 2011-06-23 | Steven Sprouse | Method and system for achieving die parallelism through block interleaving |
US20110213945A1 (en) | 2010-02-26 | 2011-09-01 | Apple Inc. | Data partitioning scheme for non-volatile memories |
Non-Patent Citations (18)
Title |
---|
"Dual supply level translator for dual memory cards (mini SD/micro SD + managed NAND)," STMicroelectronics, Paper No. ST6G3240 [online], Retrieved from the Internet: , Apr. 2008, 29 pages. |
"Dual supply level translator for dual memory cards (mini SD/micro SD + managed NAND)," STMicroelectronics, Paper No. ST6G3240 [online], Retrieved from the Internet: <http://www.st.com/stonline/products/literature/ds/14581.pdf>, Apr. 2008, 29 pages. |
"Increasing Boot Operations with Managed NAND," QuickLogic® White Paper, Quicklogic Corporation [online], Retrieved from the Internet: <http://www.quicklogic.com/images/QL:-Increasing-Boot-Opt-w-Managed-NAND-WP-RevE.pdf>, 2007-2009, 8 pages. |
Authorized officer Yolaine Cussac, International Preliminary Report on Patentability in PCT/US2010/32627 mailed Nov. 9, 2011, 8 pages. |
International Preliminary Report on Patentability in PCT/US2009/065804 mailed Jul. 7, 2011, 12 pages. |
International Preliminary Report on Patentability in PCT/US2010/032628 dated Nov. 9, 2011, 8 pages. |
International Search Report and Written Opinion for Application No. PCT/US2010/032627, dated Jul. 21, 2010, 13 pages. |
International Search Report/Written Opinion in PCT/US2009/065804 mailed May 10, 2010, 17 pages. |
International Search Report/Written Opinion in PCT/US2010/032628 dated Aug. 11, 2010, 12 pages. |
Invitation to Pay Additional Fees and, Where Applicable, Protest Fee in PCT/US2009/065804 mailed Mar. 4, 2010, 4 pages. |
Khmelnitsky et al., "Multipage Preparation Commands for Non-Volatile Memory Systems", U.S. Appl. No. 12/545,011, filed Aug. 20, 2009. |
Lim et al., "An Efficient NAND Flash File System for Flash Memory Storage," IEEE Transactions on Computers, 2006, 55(7):906-912. |
Toelkes et al., "Architecture for Address Mapping of Managed Non-Volatile Memory", U.S. Appl. No. 12/614,369, filed Nov. 6, 2009. |
Toelkes et al., "Partial Page Operations for Non-Volatile Memory Systems", U.S. Appl. No. 12/536,410, filed Aug. 5, 2009. |
Toshiba, "TC58NVG0S3ETA00 Toshiba Mos Digital Integrated Circuit Silicon Gate CMOS," Nov. 20, 2008, revision 1.00, Semico Toshiba, pp. 1-65. http://www.semicon.toshiba.co.jp/docs/datasheet/en/Memory/TC58NVG0S3ETA00-en-datasheet-110301.pdf. |
Wakrat et al., "Controller for Optimizing Throughput of Read Operations", U.S. Appl. No. 12/509,240, filed Jul. 24, 2009. |
Wakrat et al., "File System Derived Metadata for Management of Non-Volatile Memory", U.S. Appl. No. 12/561,173, filed Sep. 16, 2009. |
Wakrat et al., "Memory Array Power Cycling", U.S. Appl. No. 12/561,158, filed Sep. 16, 2009. |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8612791B2 (en) | 2009-09-16 | 2013-12-17 | Apple Inc. | Method of selective power cycling of components in a memory device independently by turning off power to a memory array or memory controller |
US8862963B2 (en) * | 2011-06-03 | 2014-10-14 | Sony Corporation | Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program |
US20120311408A1 (en) * | 2011-06-03 | 2012-12-06 | Sony Corporation | Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program |
US9092349B2 (en) * | 2011-12-14 | 2015-07-28 | Intel Corporation | Storage of codeword portions |
US20140089760A1 (en) * | 2011-12-14 | 2014-03-27 | Jonathan E. Schmidt | Storage of codeword portions |
US9368166B2 (en) | 2013-01-18 | 2016-06-14 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices, memory systems, and control methods using simultaneous recovery and output operations |
US9520168B2 (en) | 2013-01-18 | 2016-12-13 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices, memory systems and related control methods |
US20150143035A1 (en) * | 2013-11-21 | 2015-05-21 | Samsung Electronics Co., Ltd. | User device having a host flash translation layer (ftl), a method for transferring an erase count thereof, a method for transferring reprogram information thereof, and a method for transferring a page offset of an open block thereof |
US9612773B2 (en) * | 2013-11-21 | 2017-04-04 | Samsung Electronics Co., Ltd. | User device having a host flash translation layer (FTL), a method for transferring an erase count thereof, a method for transferring reprogram information thereof, and a method for transferring a page offset of an open block thereof |
US9489253B2 (en) | 2013-11-27 | 2016-11-08 | Samsung Electronics Co., Ltd. | Memory controller and method of operating memory controller for reading data from memory device at high speed |
US9720624B2 (en) | 2014-02-05 | 2017-08-01 | Samsung Electronics Co., Ltd. | Method of controlling a memory system |
US9653184B2 (en) | 2014-06-16 | 2017-05-16 | Sandisk Technologies Llc | Non-volatile memory module with physical-to-physical address remapping |
US20160232088A1 (en) * | 2014-07-17 | 2016-08-11 | Sandisk Enterprise Ip Llc | Garbage Collection in Storage System with Distributed Processors |
US10296233B2 (en) | 2015-02-11 | 2019-05-21 | Samsung Electronics Co., Ltd. | Method of managing message transmission flow and storage device using the method |
US9880748B2 (en) | 2015-02-13 | 2018-01-30 | Qualcomm Incorporated | Bifurcated memory management for memory elements |
US20170039001A1 (en) * | 2015-08-06 | 2017-02-09 | Stmicroelectronics (Rousset) Sas | Method for Writing in an EEPROM Memory and Corresponding Memory |
US10013208B2 (en) * | 2015-08-06 | 2018-07-03 | Stmicroelectronics (Rousset) Sas | Method for writing in an EEPROM memory and corresponding memory |
US10090858B2 (en) | 2015-12-14 | 2018-10-02 | Samsung Electronics Co., Ltd. | Storage device and operating method of storage device |
US10637502B2 (en) | 2015-12-14 | 2020-04-28 | Samsung Electronics Co., Ltd. | Storage device and operating method of storage device |
US11049581B2 (en) * | 2018-09-28 | 2021-06-29 | Toshiba Memory Corporation | Media error reporting improvements for storage drives |
US11482294B2 (en) | 2018-09-28 | 2022-10-25 | Kioxia Corporation | Media error reporting improvements for storage drives |
Also Published As
Publication number | Publication date |
---|---|
CN102414666A (en) | 2012-04-11 |
EP2427824A1 (en) | 2012-03-14 |
US20100287446A1 (en) | 2010-11-11 |
CN102414666B (en) | 2015-03-25 |
WO2010129305A1 (en) | 2010-11-11 |
KR20120005548A (en) | 2012-01-16 |
EP2427824B1 (en) | 2015-10-21 |
JP5591917B2 (en) | 2014-09-17 |
JP2012526323A (en) | 2012-10-25 |
KR101382060B1 (en) | 2014-04-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8438453B2 (en) | Low latency read operation for managed non-volatile memory | |
US8806151B2 (en) | Multipage preparation commands for non-volatile memory systems | |
US8370603B2 (en) | Architecture for address mapping of managed non-volatile memory | |
US20100287329A1 (en) | Partial Page Operations for Non-Volatile Memory Systems | |
US8612791B2 (en) | Method of selective power cycling of components in a memory device independently by turning off power to a memory array or memory controller | |
US8495332B2 (en) | Controller for optimizing throughput of read operations | |
US8984219B2 (en) | Data storage device and method of writing data in the same | |
US8838877B2 (en) | File system derived metadata for management of non-volatile memory | |
US9304900B2 (en) | Data reading method, memory controller, and memory storage device | |
US20240061620A1 (en) | Memory system and information processing system | |
TWI602061B (en) | Data writing method, memory storage device and memory control circuit unit | |
US10884660B2 (en) | Memory management method, memory storage device and memory control circuit unit | |
TWI804236B (en) | Memory management method, memory storage device and memory control circuit unit | |
US20230244402A1 (en) | Storage device and operating method of storage device | |
CN114627941A (en) | Memory management method, memory storage device and memory control circuit unit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: APPLE INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:POST, DANIEL JEFFREY;WAKRAT, NIR JACOB;KHMELNITSKY, VADIM;REEL/FRAME:023070/0958 Effective date: 20090727 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |