US8557649B2 - Method for controlling structure height - Google Patents

Method for controlling structure height Download PDF

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US8557649B2
US8557649B2 US13/278,301 US201113278301A US8557649B2 US 8557649 B2 US8557649 B2 US 8557649B2 US 201113278301 A US201113278301 A US 201113278301A US 8557649 B2 US8557649 B2 US 8557649B2
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layer
semiconductor structure
amorphous carbon
depositing
oxide
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US20130102125A1 (en
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Rajasekhar Venigalla
Michael Vincent Aquilino
Massud A. Aminpur
Michael P. Belyansky
Unoh Kwon
Christopher Duncan Sheraw
Daewon Yang
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GlobalFoundries US Inc
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the present invention relates to semiconductor fabrication, and more particularly, to methods for controlling the variability of the height of various semiconductor structures.
  • Increased density and proximity of both active and passive electronic device structures in an integrated circuit have been recognized to provide benefits in both performance and functionality of integrated circuits. For example, reduced lengths of signal propagation paths allow operation at higher clock rates while reducing susceptibility to noise. Increased numbers of devices on a single chip also generally support such improved performance while allowing a greater number and variety of circuit functions to be provided such as local voltage regulation and conversion, local memory and additional logic circuitry or coprocessors for microprocessors, non-volatile storage, redundant circuitry, self-test arrangements and many other types and combinations of circuits.
  • step height is the difference in height between the tops of two layers within a semiconductor structure.
  • a consistent step height is important for repeatability and consistency amongst various manufactured samples of a particular type of semiconductor device.
  • a method of forming a replacement metal transistor gate comprises depositing a layer of amorphous carbon on a sacrificial gate disposed at a location on a semiconductor structure, depositing an oxide layer on the amorphous carbon layer, depositing a nitride layer on the oxide layer, planarizing the semiconductor structure to expose the layer of amorphous carbon, removing the amorphous carbon, removing the sacrificial gate and forming a metal gate in the location previously occupied by the sacrificial gate.
  • a method of forming a replacement metal transistor gate comprises forming a sacrificial gate comprised of amorphous carbon at a location on a semiconductor structure, depositing an oxide layer on the amorphous carbon sacrificial gate, depositing a nitride layer on the oxide layer, planarizing the semiconductor structure to expose the amorphous carbon sacrificial gate, removing the amorphous carbon sacrificial gate, and forming a metal gate in the area previously occupied by the amorphous carbon sacrificial gate.
  • a method of forming a shallow trench isolation region in a semiconductor structure comprises depositing a first oxide layer on a silicon substrate, depositing a first nitride layer on the first oxide layer; depositing an amorphous carbon layer on the first nitride layer, depositing a second nitride layer on the amorphous carbon layer, depositing a second oxide layer on the nitride layer, depositing a photoresist layer on the second oxide layer, forming an opening that extends from the top of the photoresist layer into the silicon substrate, filling the opening with an STI oxide, and planarizing the semiconductor structure to the level of the top of the amorphous carbon layer.
  • FIGs. The figures are intended to be illustrative, not limiting.
  • cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity.
  • FIG. 1 shows a prior art semiconductor structure for replacement metal gate transistors.
  • FIG. 2 shows a semiconductor structure used for fabrication of replacement metal gate transistors in accordance with an embodiment of the present invention.
  • FIG. 3 shows a semiconductor structure used for fabrication of replacement metal gate transistors in accordance with an alternative embodiment of the present invention.
  • FIG. 4 shows an embodiment of the present invention after planarization.
  • FIG. 4A shows replacement metal gates fabricated by a method in accordance with an embodiment of the present invention.
  • FIG. 5 shows a semiconductor structure at a starting point for another embodiment of the present invention.
  • FIG. 6 shows a semiconductor structure similar to that of FIG. 5 , after a lithographic patterning step.
  • FIG. 7 shows a semiconductor structure similar to that of FIG. 6 , after a first anisotropic etch.
  • FIG. 8 shows a semiconductor structure similar to that of FIG. 7 , after depositing protective nitride spacers.
  • FIG. 9 shows a semiconductor structure similar to that of FIG. 8 , after a second anisotropic etch.
  • FIG. 10 shows a semiconductor structure similar to that of FIG. 9 , after depositing an oxide liner.
  • FIG. 11 shows a semiconductor structure similar to that of FIG. 10 , after depositing a shallow trench isolation (STI) oxide.
  • STI shallow trench isolation
  • FIG. 12 shows a semiconductor structure similar to that of FIG. 11 , after a planarization step.
  • FIG. 13 shows a semiconductor structure similar to that of FIG. 12 , after a BHF deglaze step.
  • FIG. 14 shows a semiconductor structure similar to that of FIG. 13 , after removal of sacrificial layers.
  • FIG. 15 is a flowchart for an embodiment of the present invention.
  • FIG. 16 is a flowchart for another embodiment of the present invention.
  • FIG. 1 shows a prior art semiconductor structure 100 for replacement metal gate transistors.
  • Prior art semiconductor structure 100 comprises buried oxide (BOX) layer 102 . Disposed on BOX layer 102 is a silicon layer 104 . An NFET transistor 130 and PFET transistor 132 are formed on the silicon layer 104 . A shallow trench isolation (STI) region 105 is disposed between the NFET transistor 130 and the PFET transistor 132 . Each transistor is comprised of a gate 116 disposed on a gate oxide 106 . Sidewall spacers 114 are formed adjacent to gate 116 .
  • a “PC cap stack” 117 comprised of two layers is disposed on gate 116 . PC cap stack 117 comprises an oxide layer 118 and a nitride layer 120 .
  • Stress layer 122 is a nitride layer that induces mechanical stress on the NFET to improve electron mobility.
  • a stress nitride 124 Disposed over the PFET 132 is a stress nitride 124 . Stress layer 124 induces mechanical stress on the PFET to improve hole mobility.
  • the stress layer 124 is typically of a different material than the stress nitride 122 , as the types of performance-increasing stresses differ for NFETs and PFETs.
  • FIG. 2 shows a semiconductor structure 200 used for fabrication of replacement metal gate transistors in accordance with an embodiment of the present invention.
  • the original gate material e.g. polysilicon
  • a metal such as ruthenium or titanium, for example.
  • similar elements may be referred to by similar numbers in various figures (FIGs) of the drawings, in which case typically the last two significant digits may be the same.
  • stress layer 222 of FIG. 2 is similar to stress layer 122 of FIG. 1 .
  • PC cap stack 217 A difference between semiconductor structure 200 of FIG. 2 and semiconductor structure 100 of FIG. 1 is the PC cap stack 217 . Similar to PC cap stack 117 of FIG. 1 , PC cap stack 217 comprises nitride layer 220 and oxide layer 218 . However, PC cap stack 217 also comprises amorphous carbon (aC) layer 234 disposed on the sacrificial gate structure 216 . Gate structure 216 may be comprised of polysilicon. In the finished FET, the gate structure 216 is replaced with a metal gate (not shown).
  • the aC layer 234 functions as a stopping layer during subsequent planarization steps that are performed with one or more chemical mechanical polish (CMP) steps. In one embodiment, the aC layer 234 is deposited using chemical vapor deposition. In one embodiment, the aC layer 234 has a thickness ranging from about 100 angstroms to about 300 angstroms. In another embodiment, the thickness of aC layer 234 is about 200 angstroms.
  • FIG. 3 shows a semiconductor structure 300 used for fabrication of replacement metal gate transistors in accordance with an alternative embodiment of the present invention.
  • the entire sacrificial gate 316 is comprised of amorphous carbon.
  • the amorphous carbon sacrificial gate 316 serves as a stopping layer.
  • the amorphous carbon sacrificial gate structure 316 is replaced with a metal gate (see FIG. 4A ).
  • FIG. 4 shows an embodiment of the present invention after planarization.
  • Semiconductor structure 400 represents semiconductor structure 200 ( FIG. 2 ) after planarization.
  • the planarization may be performed via a chemical mechanical polish (CMP) process.
  • CMP chemical mechanical polish
  • a combination of slurry polish processes and fixed abrasive polish processes may be used.
  • the CMP process stops on the aC layer 434 , preventing over-polishing of the semiconductor structure 400 .
  • gap fill layer 436 Prior to the CMP process, gap fill layer 436 may be deposited to preserve other layers during subsequent processing steps.
  • gap fill layer 436 is comprised of a USG (undoped silicate glass) and TEOS (tetraethylorthosilicate) material.
  • the aC layer 434 may be removed with an O2 plasma ash process.
  • the standard replacement metal gate (RMG) processing steps may then follow.
  • FIG. 4A shows replacement metal gates (RMG) 417 fabricated by a method in accordance with an embodiment of the present invention.
  • the sacrificial gates ( 316 of FIG. 3 ) or ( 216 of FIG. 2 ) have been replaced with metal gates 417 .
  • the metal gates 417 are in the space previously occupied by sacrificial gates.
  • the use of the amorphous carbon as an etch stop during the steps leading up to the RMG provide for a consistent planarization level, resulting in a consistent height for the metal gates 417 amongst devices on the semiconductor structure. This results in more repeatable device performance and improved product yield.
  • FIG. 5 shows a semiconductor structure 500 at a starting point for another embodiment of the present invention.
  • Semiconductor structure 500 comprises silicon layer (substrate) 540 .
  • a first (pad) oxide layer 542 Disposed on silicon layer 540 is a first (pad) oxide layer 542 .
  • pad oxide 542 Disposed on pad oxide 542 is pad nitride 546 .
  • pad nitride 546 Disposed on pad nitride 546 is amorphous carbon (aC) layer 548 .
  • aC layer 548 Disposed on aC layer 548 is a second nitride layer 550 .
  • Disposed on second nitride layer 550 Disposed on second oxide layer 551 .
  • photoresist layer 552 Disposed on second oxide layer 551 is photoresist layer 552 .
  • FIG. 6 shows a semiconductor structure 600 similar to that of FIG. 5 , after a lithographic patterning step, which creates opening 654 in photoresist layer 652 .
  • FIG. 7 shows a semiconductor structure 700 similar to that of FIG. 6 , after a first anisotropic etch which creates opening 754 which stops on pad oxide layer 742 .
  • FIG. 8 shows a semiconductor structure 800 similar to that of FIG. 7 , after removing the photoresist layer (compare with 752 of FIG. 7 ), and depositing a third (protective) nitride layer 856 .
  • FIG. 9 shows a semiconductor structure 900 similar to that of FIG. 8 , after a second anisotropic etch which extends opening 954 partially through the silicon layer 940 , followed by planarization to remove the portion of the third nitride layer that is on the top surface of the semiconductor structure, as well as the second oxide layer (compare with 851 of FIG. 8 ).
  • the opening 954 comprises interior surface 955 .
  • the remaining portion of the third nitride layer 956 serves as a “spacer” to protect the amorphous carbon layer 948 . Without such protection, the amorphous carbon layer 948 could be damaged during subsequent processing, such as formation of an oxide liner on the interior surface 955 .
  • FIG. 10 shows a semiconductor structure 1000 similar to that of FIG. 9 , after forming an oxide liner 1058 on the interior surface (see 955 of FIG. 9 ) of opening 1054 .
  • the oxide liner 1058 may be a thermal oxide grown at a high temperature.
  • the oxide liner serves to cover the silicon areas of the trench, which may have become damaged during trench formation.
  • FIG. 11 shows a semiconductor structure 1100 similar to that of FIG. 10 , after depositing a shallow trench isolation (STI) oxide 1160 .
  • STI oxide 1160 fills the opening (see 1054 of FIG. 10 ) and is also disposed on the top of semiconductor structure 1100 .
  • the STI oxide 1160 may be a low temperature oxide.
  • FIG. 12 shows a semiconductor structure 1200 similar to that of FIG. 11 , after a planarization step.
  • the STI oxide 1260 is now only in the opening, and has been removed from the top surface of the semiconductor structure 1200 .
  • the planarization may be performed via one or more chemical mechanical polish (CMP) processes.
  • CMP processes may be slurry-based, fixed abrasive, or a combination of both types.
  • the planarization process utilizes aC layer 1248 as a stopping layer.
  • FIG. 13 shows a semiconductor structure 1300 similar to that of FIG. 12 , after a BHF (buffered hydrofluoric acid) deglaze step. This recesses the STI oxide 1360 to the desired height for forming the STI regions that are disposed between adjacent semiconductor devices such as transistors.
  • BHF buffered hydrofluoric acid
  • FIG. 14 shows a semiconductor structure 1400 similar to that of FIG. 13 , after removal of sacrificial layers.
  • the aC layer ( 1348 of FIG. 13 ) may be removed with an O2 ash process.
  • the removal of pad nitride layer (layer 1346 of FIG. 13 ) may be performed with any suitable nitride removal process, such as a wet etch.
  • the step height, represented by arrow C, is of a consistent height throughout the fabrication run, resulting in reduced variability among fabricated devices, and improved semiconductor performance.
  • FIG. 15 is a flowchart for an embodiment of the present invention.
  • an amorphous carbon layer is deposited. This is shown as 234 in FIG. 2 .
  • a stress layer is deposited. This is shown as 222 in FIG. 2 .
  • a gap fill layer is deposited. This is shown as 436 in FIG. 4 .
  • the semiconductor structure is planarized. This is shown with semiconductor structure 400 of FIG. 4 .
  • the planarization may be performed with a chemical mechanical polish (CMP).
  • the CMP may be a fixed abrasive CMP or a slurry based CMP, or a combination of both types may be used.
  • FIG. 16 is a flowchart for another embodiment of the present invention.
  • process step 1680 lithographic patterning is performed. This is shown in FIG. 6 (see 654 ).
  • process step 1682 a first anisotropic etch is performed. This is shown in FIG. 7 (see 754 ).
  • process step 1684 a protective nitride layer is deposited over the amorphous carbon. This is shown in FIG. 8 (see 856 ).
  • a second anisotropic etch is performed. This is shown in FIG. 9 (see 954 ).
  • process step 1688 an oxide liner is deposited. This is shown in FIG. 10 (see 1058 ).
  • process step 1690 an oxide layer is deposited.
  • process step 1692 a planarization is performed. This is shown in FIG. 12 (see 1200 ).
  • process step 1694 a BHF deglaze is performed. This is shown in FIG. 13 (see 1300 ).
  • the pad nitride layer is removed (see 1346 of FIG. 13 , which is removed in semiconductor structure 1400 of FIG. 14 ). This may be performed with a wet chemistry, or other suitable removal process.
  • process step 1698 the amorphous carbon layer is removed. The amorphous carbon removal process may be performed via an O2 (oxygen plasma) ashing process. The resulting semiconductor structure is shown in FIG. 14 (see 1400 ).
  • the methods describe herein provide for a consistent step height in semiconductor devices.
  • the step height is important in various semiconductor structures, such as the height of a transistor gate above the STI region, or the height of the STI region as compared with the pad oxide.
  • the use of the amorphous carbon in these methods serves to provide an effective stopping layer for these processes.

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Abstract

Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.

Description

FIELD OF THE INVENTION
The present invention relates to semiconductor fabrication, and more particularly, to methods for controlling the variability of the height of various semiconductor structures.
BACKGROUND OF THE INVENTION
Increased density and proximity of both active and passive electronic device structures in an integrated circuit have been recognized to provide benefits in both performance and functionality of integrated circuits. For example, reduced lengths of signal propagation paths allow operation at higher clock rates while reducing susceptibility to noise. Increased numbers of devices on a single chip also generally support such improved performance while allowing a greater number and variety of circuit functions to be provided such as local voltage regulation and conversion, local memory and additional logic circuitry or coprocessors for microprocessors, non-volatile storage, redundant circuitry, self-test arrangements and many other types and combinations of circuits.
However, such increases in integration density and performance require improved control of various device parameters. One such parameter is the step height, which is the difference in height between the tops of two layers within a semiconductor structure. A consistent step height is important for repeatability and consistency amongst various manufactured samples of a particular type of semiconductor device.
SUMMARY
In one embodiment, a method of forming a replacement metal transistor gate is disclosed. The method comprises depositing a layer of amorphous carbon on a sacrificial gate disposed at a location on a semiconductor structure, depositing an oxide layer on the amorphous carbon layer, depositing a nitride layer on the oxide layer, planarizing the semiconductor structure to expose the layer of amorphous carbon, removing the amorphous carbon, removing the sacrificial gate and forming a metal gate in the location previously occupied by the sacrificial gate.
In another embodiment, a method of forming a replacement metal transistor gate is disclosed. The method comprises forming a sacrificial gate comprised of amorphous carbon at a location on a semiconductor structure, depositing an oxide layer on the amorphous carbon sacrificial gate, depositing a nitride layer on the oxide layer, planarizing the semiconductor structure to expose the amorphous carbon sacrificial gate, removing the amorphous carbon sacrificial gate, and forming a metal gate in the area previously occupied by the amorphous carbon sacrificial gate.
In another embodiment, a method of forming a shallow trench isolation region in a semiconductor structure is disclosed. The method comprises depositing a first oxide layer on a silicon substrate, depositing a first nitride layer on the first oxide layer; depositing an amorphous carbon layer on the first nitride layer, depositing a second nitride layer on the amorphous carbon layer, depositing a second oxide layer on the nitride layer, depositing a photoresist layer on the second oxide layer, forming an opening that extends from the top of the photoresist layer into the silicon substrate, filling the opening with an STI oxide, and planarizing the semiconductor structure to the level of the top of the amorphous carbon layer.
BRIEF DESCRIPTION OF THE DRAWINGS
The structure, operation, and advantages of the present invention will become further apparent upon consideration of the following description taken in conjunction with the accompanying figures (FIGs.). The figures are intended to be illustrative, not limiting.
Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity.
Often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG).
FIG. 1 shows a prior art semiconductor structure for replacement metal gate transistors.
FIG. 2 shows a semiconductor structure used for fabrication of replacement metal gate transistors in accordance with an embodiment of the present invention.
FIG. 3 shows a semiconductor structure used for fabrication of replacement metal gate transistors in accordance with an alternative embodiment of the present invention.
FIG. 4 shows an embodiment of the present invention after planarization.
FIG. 4A shows replacement metal gates fabricated by a method in accordance with an embodiment of the present invention.
FIG. 5 shows a semiconductor structure at a starting point for another embodiment of the present invention.
FIG. 6 shows a semiconductor structure similar to that of FIG. 5, after a lithographic patterning step.
FIG. 7 shows a semiconductor structure similar to that of FIG. 6, after a first anisotropic etch.
FIG. 8 shows a semiconductor structure similar to that of FIG. 7, after depositing protective nitride spacers.
FIG. 9 shows a semiconductor structure similar to that of FIG. 8, after a second anisotropic etch.
FIG. 10 shows a semiconductor structure similar to that of FIG. 9, after depositing an oxide liner.
FIG. 11 shows a semiconductor structure similar to that of FIG. 10, after depositing a shallow trench isolation (STI) oxide.
FIG. 12 shows a semiconductor structure similar to that of FIG. 11, after a planarization step.
FIG. 13 shows a semiconductor structure similar to that of FIG. 12, after a BHF deglaze step.
FIG. 14 shows a semiconductor structure similar to that of FIG. 13, after removal of sacrificial layers.
FIG. 15 is a flowchart for an embodiment of the present invention.
FIG. 16 is a flowchart for another embodiment of the present invention.
 DETAILED DESCRIPTION
FIG. 1 shows a prior art semiconductor structure 100 for replacement metal gate transistors. Prior art semiconductor structure 100 comprises buried oxide (BOX) layer 102. Disposed on BOX layer 102 is a silicon layer 104. An NFET transistor 130 and PFET transistor 132 are formed on the silicon layer 104. A shallow trench isolation (STI) region 105 is disposed between the NFET transistor 130 and the PFET transistor 132. Each transistor is comprised of a gate 116 disposed on a gate oxide 106. Sidewall spacers 114 are formed adjacent to gate 116. A “PC cap stack” 117 comprised of two layers is disposed on gate 116. PC cap stack 117 comprises an oxide layer 118 and a nitride layer 120. Disposed over the NFET 130 is a stress layer 122. Stress layer 122 is a nitride layer that induces mechanical stress on the NFET to improve electron mobility. Disposed over the PFET 132 is a stress nitride 124. Stress layer 124 induces mechanical stress on the PFET to improve hole mobility. The stress layer 124 is typically of a different material than the stress nitride 122, as the types of performance-increasing stresses differ for NFETs and PFETs.
FIG. 2 shows a semiconductor structure 200 used for fabrication of replacement metal gate transistors in accordance with an embodiment of the present invention. In a replacement metal gate (RMG) process, the original gate material (e.g. polysilicon) is replaced with a metal (such as ruthenium or titanium, for example). As stated previously, often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawings, in which case typically the last two significant digits may be the same. For example, stress layer 222 of FIG. 2 is similar to stress layer 122 of FIG. 1.
A difference between semiconductor structure 200 of FIG. 2 and semiconductor structure 100 of FIG. 1 is the PC cap stack 217. Similar to PC cap stack 117 of FIG. 1, PC cap stack 217 comprises nitride layer 220 and oxide layer 218. However, PC cap stack 217 also comprises amorphous carbon (aC) layer 234 disposed on the sacrificial gate structure 216. Gate structure 216 may be comprised of polysilicon. In the finished FET, the gate structure 216 is replaced with a metal gate (not shown). The aC layer 234 functions as a stopping layer during subsequent planarization steps that are performed with one or more chemical mechanical polish (CMP) steps. In one embodiment, the aC layer 234 is deposited using chemical vapor deposition. In one embodiment, the aC layer 234 has a thickness ranging from about 100 angstroms to about 300 angstroms. In another embodiment, the thickness of aC layer 234 is about 200 angstroms.
FIG. 3 shows a semiconductor structure 300 used for fabrication of replacement metal gate transistors in accordance with an alternative embodiment of the present invention. In this case, the entire sacrificial gate 316 is comprised of amorphous carbon. The amorphous carbon sacrificial gate 316 serves as a stopping layer. In the finished FET, the amorphous carbon sacrificial gate structure 316 is replaced with a metal gate (see FIG. 4A).
FIG. 4 shows an embodiment of the present invention after planarization. Semiconductor structure 400 represents semiconductor structure 200 (FIG. 2) after planarization. The planarization may be performed via a chemical mechanical polish (CMP) process. A combination of slurry polish processes and fixed abrasive polish processes may be used. The CMP process stops on the aC layer 434, preventing over-polishing of the semiconductor structure 400. Prior to the CMP process, gap fill layer 436 may be deposited to preserve other layers during subsequent processing steps. In one embodiment, gap fill layer 436 is comprised of a USG (undoped silicate glass) and TEOS (tetraethylorthosilicate) material. The aC layer 434 may be removed with an O2 plasma ash process. The standard replacement metal gate (RMG) processing steps may then follow.
FIG. 4A shows replacement metal gates (RMG) 417 fabricated by a method in accordance with an embodiment of the present invention. The sacrificial gates (316 of FIG. 3) or (216 of FIG. 2) have been replaced with metal gates 417. Hence, the metal gates 417 are in the space previously occupied by sacrificial gates. The use of the amorphous carbon as an etch stop during the steps leading up to the RMG provide for a consistent planarization level, resulting in a consistent height for the metal gates 417 amongst devices on the semiconductor structure. This results in more repeatable device performance and improved product yield.
FIG. 5 shows a semiconductor structure 500 at a starting point for another embodiment of the present invention. Semiconductor structure 500 comprises silicon layer (substrate) 540. Disposed on silicon layer 540 is a first (pad) oxide layer 542. Disposed on pad oxide 542 is pad nitride 546. Disposed on pad nitride 546 is amorphous carbon (aC) layer 548. Disposed on aC layer 548 is a second nitride layer 550. Disposed on second nitride layer 550 is a second oxide layer 551. Disposed on second oxide layer 551 is photoresist layer 552.
FIG. 6 shows a semiconductor structure 600 similar to that of FIG. 5, after a lithographic patterning step, which creates opening 654 in photoresist layer 652.
FIG. 7 shows a semiconductor structure 700 similar to that of FIG. 6, after a first anisotropic etch which creates opening 754 which stops on pad oxide layer 742.
FIG. 8 shows a semiconductor structure 800 similar to that of FIG. 7, after removing the photoresist layer (compare with 752 of FIG. 7), and depositing a third (protective) nitride layer 856.
FIG. 9 shows a semiconductor structure 900 similar to that of FIG. 8, after a second anisotropic etch which extends opening 954 partially through the silicon layer 940, followed by planarization to remove the portion of the third nitride layer that is on the top surface of the semiconductor structure, as well as the second oxide layer (compare with 851 of FIG. 8). The opening 954 comprises interior surface 955. The remaining portion of the third nitride layer 956 serves as a “spacer” to protect the amorphous carbon layer 948. Without such protection, the amorphous carbon layer 948 could be damaged during subsequent processing, such as formation of an oxide liner on the interior surface 955.
FIG. 10 shows a semiconductor structure 1000 similar to that of FIG. 9, after forming an oxide liner 1058 on the interior surface (see 955 of FIG. 9) of opening 1054. The oxide liner 1058 may be a thermal oxide grown at a high temperature. The oxide liner serves to cover the silicon areas of the trench, which may have become damaged during trench formation.
FIG. 11 shows a semiconductor structure 1100 similar to that of FIG. 10, after depositing a shallow trench isolation (STI) oxide 1160. STI oxide 1160 fills the opening (see 1054 of FIG. 10) and is also disposed on the top of semiconductor structure 1100. The STI oxide 1160 may be a low temperature oxide.
FIG. 12 shows a semiconductor structure 1200 similar to that of FIG. 11, after a planarization step. The STI oxide 1260 is now only in the opening, and has been removed from the top surface of the semiconductor structure 1200. The planarization may be performed via one or more chemical mechanical polish (CMP) processes. In some embodiments, the CMP processes may be slurry-based, fixed abrasive, or a combination of both types. The planarization process utilizes aC layer 1248 as a stopping layer.
FIG. 13 shows a semiconductor structure 1300 similar to that of FIG. 12, after a BHF (buffered hydrofluoric acid) deglaze step. This recesses the STI oxide 1360 to the desired height for forming the STI regions that are disposed between adjacent semiconductor devices such as transistors.
FIG. 14 shows a semiconductor structure 1400 similar to that of FIG. 13, after removal of sacrificial layers. The aC layer (1348 of FIG. 13) may be removed with an O2 ash process. The removal of pad nitride layer (layer 1346 of FIG. 13) may be performed with any suitable nitride removal process, such as a wet etch. The step height, represented by arrow C, is of a consistent height throughout the fabrication run, resulting in reduced variability among fabricated devices, and improved semiconductor performance.
FIG. 15 is a flowchart for an embodiment of the present invention. In process step 1570, an amorphous carbon layer is deposited. This is shown as 234 in FIG. 2. In process step 1572 a stress layer is deposited. This is shown as 222 in FIG. 2. In process step 1574, a gap fill layer is deposited. This is shown as 436 in FIG. 4. In process step 1576, the semiconductor structure is planarized. This is shown with semiconductor structure 400 of FIG. 4. The planarization may be performed with a chemical mechanical polish (CMP). The CMP may be a fixed abrasive CMP or a slurry based CMP, or a combination of both types may be used.
FIG. 16 is a flowchart for another embodiment of the present invention. In process step 1680, lithographic patterning is performed. This is shown in FIG. 6 (see 654). In process step 1682, a first anisotropic etch is performed. This is shown in FIG. 7 (see 754). In process step 1684, a protective nitride layer is deposited over the amorphous carbon. This is shown in FIG. 8 (see 856). In process step 1686, a second anisotropic etch is performed. This is shown in FIG. 9 (see 954). In process step 1688, an oxide liner is deposited. This is shown in FIG. 10 (see 1058). In process step 1690, an oxide layer is deposited. This is shown in FIG. 11 (see 1160). In process step 1692, a planarization is performed. This is shown in FIG. 12 (see 1200). In process step 1694, a BHF deglaze is performed. This is shown in FIG. 13 (see 1300). In process step 1696, the pad nitride layer is removed (see 1346 of FIG. 13, which is removed in semiconductor structure 1400 of FIG. 14). This may be performed with a wet chemistry, or other suitable removal process. In process step 1698, the amorphous carbon layer is removed. The amorphous carbon removal process may be performed via an O2 (oxygen plasma) ashing process. The resulting semiconductor structure is shown in FIG. 14 (see 1400). The methods describe herein provide for a consistent step height in semiconductor devices. The step height is important in various semiconductor structures, such as the height of a transistor gate above the STI region, or the height of the STI region as compared with the pad oxide. The use of the amorphous carbon in these methods serves to provide an effective stopping layer for these processes.
Although the invention has been shown and described with respect to a certain preferred embodiment or embodiments, certain equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.) the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more features of the other embodiments as may be desired and advantageous for any given or particular application.

Claims (5)

What is claimed is:
1. A method of forming a replacement metal transistor gate comprising;
depositing a layer of amorphous carbon on a sacrificial gate disposed at a location on a semiconductor structure;
depositing an oxide layer on the layer of amorphous carbon;
depositing a nitride layer on the oxide layer;
planarizing the semiconductor structure to expose the layer of amorphous carbon;
removing the layer of amorphous carbon;
removing the sacrificial gate; and
forming a metal gate in the location previously occupied by the sacrificial gate.
2. The method of claim 1, further including planarizing the semiconductor structure with a chemical mechanical polish.
3. The method of claim 2, further including planarizing the semiconductor structure with a fixed abrasive chemical mechanical polish.
4. The method of claim 1, wherein depositing a layer of amorphous carbon on a sacrificial gate comprises depositing a layer of amorphous carbon having a thickness ranging from about 100 angstroms to about 300 angstroms.
5. The method of claim 1, further including depositing a layer of amorphous carbon with a chemical vapor deposition process.
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