US8597032B2 - Electronic assemblies mating system - Google Patents
Electronic assemblies mating system Download PDFInfo
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- US8597032B2 US8597032B2 US13/035,921 US201113035921A US8597032B2 US 8597032 B2 US8597032 B2 US 8597032B2 US 201113035921 A US201113035921 A US 201113035921A US 8597032 B2 US8597032 B2 US 8597032B2
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- 230000000712 assembly Effects 0.000 title abstract description 10
- 238000000429 assembly Methods 0.000 title abstract description 10
- 230000013011 mating Effects 0.000 title description 4
- 238000009826 distribution Methods 0.000 claims description 7
- 230000006870 function Effects 0.000 description 4
- 238000001816 cooling Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
Definitions
- the invention relates to the field of computer systems, and, more particularly, to electronic assemblies mating systems.
- the second category is associated with integrated servers, to which physical nodes not only utilize common mechanical support, power, and/or cooling infrastructure, but also are required to share computing resources.
- these physical nodes e.g. books, drawers, blades, logic nodes, and/or the like, are required to share general communications such as common system-level clocking, service support processing function, and/or the like as well as specific inter-node computing functions via a fabric or parallel communication bus structure.
- a system to mate electronic assemblies may include a computer backplane, and a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly.
- the system may also include a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect, the second electronic interconnect configured to operationally mate with a second electronic assembly where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time.
- the first electronic interconnect and the second electronic interconnect may be positioned on the computer backplane based upon the respective positions of the first electronic assembly and the second electronic assembly.
- the first electronic interconnect may comprise a third electronic assembly
- the second electronic interconnect may comprise a fourth electronic assembly
- the first electronic assembly and the second electronic assembly are carried by a circuit board.
- the system may also include at least a third electronic interconnect carried by the computer backplane and configured to operationally mate with at least a respective fifth electronic assembly, where the at least third electronic interconnect may comprise at least a sixth electronic assembly, and the fifth electronic assembly may be carried by the circuit board.
- the third electronic assembly and the fourth electronic assembly may comprise power supplies and the computer backplane positions each power supply close to a respective first and second electronic assembly to reduce distributions losses from either power supply to the respective electronic assembly.
- the first electronic interconnect and the second electronic interconnect may be in parallel and not in series.
- the computer sub-assembly backplane may have a reduced profile due to the first electronic interconnect and the second electronic interconnect being distributed plane.
- the reduced profile of the backplane may increase the airflow around an electronic assembly the backplane mates to.
- the first electronic interconnect and the second electronic interconnect may use mechanical tracks to align with the first electronic assembly and second electronic assembly respectively.
- the system may comprise a computer backplane, and a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly.
- the system may also include a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect, the second electronic interconnect configured to operationally mate with a second electronic assembly where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time.
- the first electronic interconnect and the second electronic interconnect may be positioned on the computer backplane based upon the respective positions of the first electronic assembly and the second electronic assembly, and the first electronic interconnect and the second electronic interconnect are in parallel and not in series.
- the system may include a computer backplane, and a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly.
- the system may also include a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect to reduce the computer backplane's profile due to the first electronic interconnect and the second electronic interconnect being distributed along the computer backplane and the reduced profile of the backplane increases the airflow around an electronic assembly the backplane mates to.
- the second electronic interconnect may be configured to operationally mate with a second electronic assembly where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time.
- FIG. 1 is a cross-sectional view of a system to mate electronic assemblies in accordance with the invention.
- FIG. 2 is a front isometric view of the system of FIG. 1 .
- FIG. 3 is a top and bottom isometric views of the computer backplane and associated cover found in the system of FIG. 1 .
- FIG. 4 a is a rear view of the system of FIG. 1 .
- FIG. 4 b is a front view of the system of FIG. 1 .
- FIG. 5 is a bottom-side view of the computer backplane cover of FIG. 3 .
- system 10 includes a computer backplane 12 a - 12 n , which may include a cover 15 and backplane circuit board 17 .
- the system 10 also includes a first electronic interconnect 14 carried by the computer backplane configured to operationally mate with a first electronic assembly 16 .
- the electronic assembly 16 like all other electronic assemblies in this disclosure, comprises memory cards, computer modules, input/output fanout cards, mini boards, and/or the like.
- the system 10 also includes a second electronic interconnect 18 carried by the computer backplane 12 a - 12 n that is physically separate from the first electronic interconnect 14 , which means the first electronic interconnect and the second electronic interconnect do not share the same housing, wiring, and/or the like at the point each contacts a respective electronic assembly, for example.
- the second electronic interconnect 18 is configured to operationally mate with a second electronic assembly 20 , which means the second electronic interconnect 18 and the second electronic assembly 20 relay data, power, and/or the like across each other, for instance. Further, the first electronic interconnect 14 and the second electronic assembly 20 mate with the computer backplane 12 a - 12 n at substantially the same time.
- first electronic interconnect 14 and the second electronic interconnect 18 are positioned on the computer backplane 12 a - 12 n based upon the respective positions of the first electronic assembly 16 and the second electronic assembly 20 .
- first electronic interconnect 14 comprises a third electronic assembly 22
- second electronic interconnect 18 comprises a fourth electronic assembly 24
- the first electronic assembly 16 and the second electronic assembly 20 are carried by a circuit board 26 .
- the system 10 also includes at least a third electronic interconnect 28 a - 28 n carried by the computer backplane 12 a - 12 n and configured to operationally mate with at least a respective fifth electronic assembly 30 a - 30 n , where the at least third electronic interconnect comprises at least a sixth electronic assembly 32 a - 32 n , and the fifth electronic assembly is carried by the circuit board 26 .
- the third electronic assembly 22 and the forth electronic assembly 24 comprise power supplies and the computer backplane 12 a - 12 n positions each power supply close to a respective first and second electronic assembly 16 and 20 to reduce distributions losses from either power supply to the respective electronic assembly.
- the first electronic interconnect 14 and the second electronic interconnect 18 are in parallel and not in series.
- the computer sub-assembly backplane 12 a - 12 n has a reduced profile due to the first electronic interconnect 14 and the second electronic interconnect 18 being distributed along the assembly which mates to a system computer back-plane.
- the reduced profile of the backplane 12 a - 12 n increases the airflow around an electronic assembly 16 , 20 , and 30 a - 30 n the backplane mates to.
- the first electronic interconnect 14 and the second electronic interconnect 18 use mechanical tracks to align with the first electronic assembly 16 and second electronic assembly 20 respectively.
- there is no blind swapping mechanism because cards align to electronic interconnect 14 , 18 , and/or 28 a - 28 n via the mechanical tracks.
- the system 10 comprises a computer backplane 12 a - 12 n , and a first electronic interconnect 14 carried by the computer backplane configured to operationally mate with a first electronic assembly 16 .
- the system 10 also includes a second electronic interconnect 18 carried by the computer backplane 12 a - 12 n that is physically separate from the first electronic interconnect 14 , the second electronic interconnect 18 configured to operationally mate with a second electronic assembly 20 where the first electronic assembly 16 and the second electronic assembly 20 mate with the computer backplane at substantially the same time.
- the first electronic interconnect 14 and the second electronic interconnect 18 are positioned on the computer backplane 12 a - 12 n based upon the respective positions of the first electronic assembly 16 and the second electronic assembly 20 , and the first electronic interconnect and the second electronic interconnect 18 are in parallel and not in series.
- the system 10 includes a computer backplane 12 a - 12 n , and a first electronic interconnect 14 carried by the computer backplane and configured to operationally mate with an electronic assembly 16 .
- the system 10 also includes a second electronic interconnect 18 carried by the computer backplane 12 a - 12 n that is physically separate from the first electronic interconnect 14 to reduce the computer backplane's profile due to the first electronic interconnect and the second electronic interconnect being distributed along the computer backplane and the reduced profile of the backplane increases the airflow around an electronic assembly 16 the backplane mates to.
- the second electronic interconnect 18 is configured to operationally mate with a second electronic assembly 20 where the first electronic assembly 16 and the second electronic assembly mate with the computer backplane 12 a - 12 n at substantially the same time.
- the system 10 aids in mating electronic assemblies such as 16 , 20 , 22 , 24 , 30 a - 30 n , and/or 32 a - 32 n .
- the system 10 removes more heat from the mated electronic assemblies than current electronic mating assemblies.
- System 10 provides system-level integration facilitated thru the use of multiple, parallel electronic interconnects 14 , 18 , and/or 28 a - 28 n having co-docking features.
- the computer backplane 12 a - 12 n installs into front of server drawer as illustrated in FIG. 4 b.
- the computer backplane 12 a - 12 n will slide under I/O cards and rise up toward the circuit board 26 and four right angle electronic connectors 34 a - 34 n on bottom of the circuit board will mate simultaneously with 4 right angle electronic interconnects 14 , 18 , and/or 28 a - 28 n on top of computer backplane.
- the system 10 provides airflow from front to rear.
- the computer backplane 12 a - 12 n includes a cover with perforations on front, bottom, and rear as illustrated in FIG. 5 .
- the unused volume in node assembly is the clearance between the computer backplane 12 a - 12 n cover and height of mated connectors plus a sliding clearance allowance. This space can subsequently be used as air plenum for air flow.
- multiple connector positions provides distributed low voltage current distribution into processor circuit board 26 to reduce voltage drop and I 2 R heating.
- power distribution in computer backplane 12 a - 12 n is higher voltage so lower current.
Abstract
A system to mate electronic assemblies includes a computer backplane, and a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly. The system also includes a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect, the second electronic interconnect configured to operationally mate with a second electronic assembly where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time.
Description
The invention relates to the field of computer systems, and, more particularly, to electronic assemblies mating systems.
This application contains subject matter related to the following co-pending U.S. patent application Ser. No. 13/035,924, filed Feb. 26, 2011 and titled “System to Operationally Connect Logic Nodes”, U.S. patent application Ser. No. 13/035,925, filed Feb. 26, 2011 and titled “Shared System to Operationally Connect Logic Nodes”, and U.S. patent application Ser. No. 13/035,926, filed Feb. 26, 2011 and titled “Logic Node Connection System”, the entire subject matters of which are incorporated herein by reference in their entirety. The aforementioned applications are assigned to the same assignee as this application, International Business Machines Corporation of Armonk, N.Y.
Recent developments of rack-mounted servers generally reside in two specific categories. The first of these are stand-alone servers which reside in a common rack, but do not communicate or share computing resources such as processor, memory, and/or input/output utilization, but share mechanical support, power, and/or cooling infrastructure.
The second category is associated with integrated servers, to which physical nodes not only utilize common mechanical support, power, and/or cooling infrastructure, but also are required to share computing resources. In this case, these physical nodes, e.g. books, drawers, blades, logic nodes, and/or the like, are required to share general communications such as common system-level clocking, service support processing function, and/or the like as well as specific inter-node computing functions via a fabric or parallel communication bus structure.
According to one embodiment of the invention, a system to mate electronic assemblies may include a computer backplane, and a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly. The system may also include a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect, the second electronic interconnect configured to operationally mate with a second electronic assembly where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time.
The first electronic interconnect and the second electronic interconnect may be positioned on the computer backplane based upon the respective positions of the first electronic assembly and the second electronic assembly. The first electronic interconnect may comprise a third electronic assembly, the second electronic interconnect may comprise a fourth electronic assembly, and the first electronic assembly and the second electronic assembly are carried by a circuit board.
The system may also include at least a third electronic interconnect carried by the computer backplane and configured to operationally mate with at least a respective fifth electronic assembly, where the at least third electronic interconnect may comprise at least a sixth electronic assembly, and the fifth electronic assembly may be carried by the circuit board. The third electronic assembly and the fourth electronic assembly may comprise power supplies and the computer backplane positions each power supply close to a respective first and second electronic assembly to reduce distributions losses from either power supply to the respective electronic assembly. The first electronic interconnect and the second electronic interconnect may be in parallel and not in series.
The computer sub-assembly backplane may have a reduced profile due to the first electronic interconnect and the second electronic interconnect being distributed plane. The reduced profile of the backplane may increase the airflow around an electronic assembly the backplane mates to. The first electronic interconnect and the second electronic interconnect may use mechanical tracks to align with the first electronic assembly and second electronic assembly respectively.
In an embodiment, the system may comprise a computer backplane, and a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly. The system may also include a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect, the second electronic interconnect configured to operationally mate with a second electronic assembly where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time. The first electronic interconnect and the second electronic interconnect may be positioned on the computer backplane based upon the respective positions of the first electronic assembly and the second electronic assembly, and the first electronic interconnect and the second electronic interconnect are in parallel and not in series.
In an embodiment, the system may include a computer backplane, and a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly. The system may also include a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect to reduce the computer backplane's profile due to the first electronic interconnect and the second electronic interconnect being distributed along the computer backplane and the reduced profile of the backplane increases the airflow around an electronic assembly the backplane mates to. The second electronic interconnect may be configured to operationally mate with a second electronic assembly where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time.
The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. Like numbers refer to like elements throughout, like numbers with letter suffixes are used to identify similar parts in a single embodiment, and letter suffix lower case n is a variable that indicates an unlimited number of similar elements.
With reference now to FIGS. 1-4 b, a system 10 to mate electronic assemblies is initially described. In an embodiment, system 10 includes a computer backplane 12 a-12 n, which may include a cover 15 and backplane circuit board 17. The system 10 also includes a first electronic interconnect 14 carried by the computer backplane configured to operationally mate with a first electronic assembly 16. The electronic assembly 16, like all other electronic assemblies in this disclosure, comprises memory cards, computer modules, input/output fanout cards, mini boards, and/or the like.
The system 10 also includes a second electronic interconnect 18 carried by the computer backplane 12 a-12 n that is physically separate from the first electronic interconnect 14, which means the first electronic interconnect and the second electronic interconnect do not share the same housing, wiring, and/or the like at the point each contacts a respective electronic assembly, for example. The second electronic interconnect 18 is configured to operationally mate with a second electronic assembly 20, which means the second electronic interconnect 18 and the second electronic assembly 20 relay data, power, and/or the like across each other, for instance. Further, the first electronic interconnect 14 and the second electronic assembly 20 mate with the computer backplane 12 a-12 n at substantially the same time.
In an embodiment, the first electronic interconnect 14 and the second electronic interconnect 18 are positioned on the computer backplane 12 a-12 n based upon the respective positions of the first electronic assembly 16 and the second electronic assembly 20. In another embodiment, the first electronic interconnect 14 comprises a third electronic assembly 22, the second electronic interconnect 18 comprises a fourth electronic assembly 24, and the first electronic assembly 16 and the second electronic assembly 20 are carried by a circuit board 26.
In an embodiment, the system 10 also includes at least a third electronic interconnect 28 a-28 n carried by the computer backplane 12 a-12 n and configured to operationally mate with at least a respective fifth electronic assembly 30 a-30 n, where the at least third electronic interconnect comprises at least a sixth electronic assembly 32 a-32 n, and the fifth electronic assembly is carried by the circuit board 26. In another embodiment, the third electronic assembly 22 and the forth electronic assembly 24 comprise power supplies and the computer backplane 12 a-12 n positions each power supply close to a respective first and second electronic assembly 16 and 20 to reduce distributions losses from either power supply to the respective electronic assembly. In another embodiment, the first electronic interconnect 14 and the second electronic interconnect 18 are in parallel and not in series.
In an embodiment, the computer sub-assembly backplane 12 a-12 n has a reduced profile due to the first electronic interconnect 14 and the second electronic interconnect 18 being distributed along the assembly which mates to a system computer back-plane. The reduced profile of the backplane 12 a-12 n increases the airflow around an electronic assembly 16, 20, and 30 a-30 n the backplane mates to. In another embodiment, the first electronic interconnect 14 and the second electronic interconnect 18 use mechanical tracks to align with the first electronic assembly 16 and second electronic assembly 20 respectively. In another embodiment, there is no blind swapping mechanism because cards align to electronic interconnect 14, 18, and/or 28 a-28 n via the mechanical tracks.
In an embodiment, the system 10 comprises a computer backplane 12 a-12 n, and a first electronic interconnect 14 carried by the computer backplane configured to operationally mate with a first electronic assembly 16. The system 10 also includes a second electronic interconnect 18 carried by the computer backplane 12 a-12 n that is physically separate from the first electronic interconnect 14, the second electronic interconnect 18 configured to operationally mate with a second electronic assembly 20 where the first electronic assembly 16 and the second electronic assembly 20 mate with the computer backplane at substantially the same time. The first electronic interconnect 14 and the second electronic interconnect 18 are positioned on the computer backplane 12 a-12 n based upon the respective positions of the first electronic assembly 16 and the second electronic assembly 20, and the first electronic interconnect and the second electronic interconnect 18 are in parallel and not in series.
In an embodiment, the system 10 includes a computer backplane 12 a-12 n, and a first electronic interconnect 14 carried by the computer backplane and configured to operationally mate with an electronic assembly 16. The system 10 also includes a second electronic interconnect 18 carried by the computer backplane 12 a-12 n that is physically separate from the first electronic interconnect 14 to reduce the computer backplane's profile due to the first electronic interconnect and the second electronic interconnect being distributed along the computer backplane and the reduced profile of the backplane increases the airflow around an electronic assembly 16 the backplane mates to. The second electronic interconnect 18 is configured to operationally mate with a second electronic assembly 20 where the first electronic assembly 16 and the second electronic assembly mate with the computer backplane 12 a-12 n at substantially the same time.
In view of the foregoing, the system 10 aids in mating electronic assemblies such as 16, 20, 22, 24, 30 a-30 n, and/or 32 a-32 n. In addition, the system 10 removes more heat from the mated electronic assemblies than current electronic mating assemblies.
In an embodiment, the computer backplane 12 a-12 n will slide under I/O cards and rise up toward the circuit board 26 and four right angle electronic connectors 34 a-34 n on bottom of the circuit board will mate simultaneously with 4 right angle electronic interconnects 14, 18, and/or 28 a-28 n on top of computer backplane.
In an embodiment, the system 10 provides airflow from front to rear. In another embodiment, the computer backplane 12 a-12 n includes a cover with perforations on front, bottom, and rear as illustrated in FIG. 5 .
In an embodiment, the unused volume in node assembly is the clearance between the computer backplane 12 a-12 n cover and height of mated connectors plus a sliding clearance allowance. This space can subsequently be used as air plenum for air flow.
In an embodiment, multiple connector positions provides distributed low voltage current distribution into processor circuit board 26 to reduce voltage drop and I2R heating. In another embodiment, power distribution in computer backplane 12 a-12 n is higher voltage so lower current.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
Claims (15)
1. A system comprising:
a computer backplane;
a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly; and
a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect, the second electronic interconnect configured to operationally mate with a second electronic assembly, and where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time;
a circuit board carrying the first electronic assembly and the second electronic assembly;
wherein the first electronic interconnect comprises a third electronic assembly;
wherein the second electronic interconnect comprises a fourth electronic assembly; and
wherein the third electronic assembly and the forth electronic assembly comprise power supplies and the computer backplane positions each power supply close to the first electronic assembly and the second electronic assembly to reduce distributions losses from either power supply to the first electronic assembly and the second electronic assembly.
2. The system of claim 1 wherein the first electronic interconnect and the second electronic interconnect are positioned on the computer backplane based upon the respective positions of the first electronic assembly and the second electronic assembly.
3. The system of claim 1 further comprising at least a third electronic interconnect carried by the computer backplane and configured to operationally mate with at least a respective fifth electronic assembly, the at least third electronic interconnect comprises at least a sixth electronic assembly, and the fifth electronic assembly is carried by the circuit board.
4. The system of claim 1 wherein the first electronic interconnect and the second electronic interconnect are in parallel and not in series.
5. The system of claim 1 wherein the computer backplane has a reduced profile due to the first electronic interconnect and the second electronic interconnect being distributed along the first electronic assembly and the second electronic assembly which mates to a system computer backplane.
6. The system of claim 5 wherein the reduced profile of the computer backplane increases the airflow around the first electronic assembly and the second electronic assembly the computer backplane mates to.
7. The system of claim 1 wherein the first electronic interconnect and the second electronic interconnect use mechanical tracks to align with the first electronic assembly and second electronic assembly respectively.
8. A system comprising:
a computer backplane;
a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly; and
a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect, the second electronic interconnect configured to operationally mate with a second electronic assembly, and where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time, the first electronic interconnect and the second electronic interconnect are positioned on the computer backplane based upon the respective positions of the first electronic assembly and the second electronic assembly, and the first electronic interconnect and the second electronic interconnect are in parallel and not in series;
a circuit board carrying the first electronic assembly and the second electronic assembly;
wherein the first electronic interconnect comprises a third electronic assembly;
wherein the second electronic interconnect comprises a fourth electronic assembly; and
wherein the third electronic assembly and the forth electronic assembly comprise power supplies and the computer backplane positions each power supply close to the first electronic assembly and the second electronic assembly to reduce distributions losses from either power supply to the first electronic assembly and the second electronic assembly.
9. The system of claim 8 further comprising at least a third electronic interconnect carried by the computer backplane and configured to operationally mate with at least a respective fifth electronic assembly, the at least third electronic interconnect comprises at least a sixth electronic assembly, and the fifth electronic assembly is carried by the circuit board.
10. The system of claim 8 wherein the computer backplane has a reduced profile due to the first electronic interconnect and the second electronic interconnect being distributed along the first electronic assembly and the second electronic assembly which mates to a system computer backplane.
11. The system of claim 10 wherein the reduced profile of the computer backplane increases the airflow around the first electronic assembly and the second electronic assembly the computer backplane mates to.
12. The system of claim 8 wherein the first electronic interconnect and the second electronic interconnect use mechanical tracks to align with the first electronic assembly and second electronic assembly respectively.
13. A system comprising:
a computer backplane;
a first electronic interconnect carried by the computer backplane configured to operationally mate with a first electronic assembly; and
a second electronic interconnect carried by the computer backplane that is physically separate from the first electronic interconnect to reduce the computer backplane's profile due to the first electronic interconnect and the second electronic interconnect being distributed along the first electronic assembly which mates the computer backplane and the reduced profile of the computer backplane increases the airflow around the first electronic assembly and a second electronic assembly the computer backplane mates to, and the second electronic interconnect configured to operationally mate with the second electronic assembly, and where the first electronic assembly and the second electronic assembly mate with the computer backplane at substantially a same time;
wherein a third electronic assembly and a forth electronic assembly comprise power supplies and the computer backplane positions each power supply close to a respective first and second electronic assembly to reduce distributions losses from either power supply to the first electronic assembly and the second electronic assembly.
14. The system of claim 13 wherein the first electronic interconnect and the second electronic interconnect are positioned on the computer backplane based upon the respective positions of the first electronic assembly and the second electronic assembly.
15. The system of claim 13 wherein the first electronic interconnect and the second electronic interconnect are in parallel and not in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/035,921 US8597032B2 (en) | 2011-02-26 | 2011-02-26 | Electronic assemblies mating system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/035,921 US8597032B2 (en) | 2011-02-26 | 2011-02-26 | Electronic assemblies mating system |
Publications (2)
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| US20120218698A1 US20120218698A1 (en) | 2012-08-30 |
| US8597032B2 true US8597032B2 (en) | 2013-12-03 |
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| US13/035,921 Expired - Fee Related US8597032B2 (en) | 2011-02-26 | 2011-02-26 | Electronic assemblies mating system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8713228B2 (en) * | 2011-02-26 | 2014-04-29 | International Business Machines Corporation | Shared system to operationally connect logic nodes |
| US8589608B2 (en) * | 2011-02-26 | 2013-11-19 | International Business Machines Corporation | Logic node connection system |
| US8597032B2 (en) | 2011-02-26 | 2013-12-03 | International Business Machines Corporation | Electronic assemblies mating system |
| US8738828B2 (en) * | 2011-02-26 | 2014-05-27 | International Business Machines Corporation | System to operationally connect logic nodes |
| TWI566083B (en) * | 2015-04-24 | 2017-01-11 | 台達電子工業股份有限公司 | Standalone Uninterruptible Power Supply |
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| US20120218698A1 (en) | 2012-08-30 |
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