US8654561B1 - Read methods, circuits and systems for memory devices - Google Patents
Read methods, circuits and systems for memory devices Download PDFInfo
- Publication number
- US8654561B1 US8654561B1 US13/276,763 US201113276763A US8654561B1 US 8654561 B1 US8654561 B1 US 8654561B1 US 201113276763 A US201113276763 A US 201113276763A US 8654561 B1 US8654561 B1 US 8654561B1
- Authority
- US
- United States
- Prior art keywords
- memory
- memory device
- value
- read
- programmable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 230000015654 memory Effects 0.000 claims abstract description 218
- 230000008859 change Effects 0.000 claims abstract description 25
- 230000015556 catabolic process Effects 0.000 claims description 67
- 230000004044 response Effects 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 7
- 239000010416 ion conductor Substances 0.000 claims description 3
- 150000004706 metal oxides Chemical group 0.000 claims description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 2
- 239000005751 Copper oxide Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910000431 copper oxide Inorganic materials 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 229910000314 transition metal oxide Inorganic materials 0.000 claims description 2
- 229910052755 nonmetal Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 27
- 230000009471 action Effects 0.000 description 8
- 238000009826 distribution Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 230000003068 static effect Effects 0.000 description 7
- 230000014759 maintenance of location Effects 0.000 description 5
- 238000013459 approach Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- YIZVROFXIVWAAZ-UHFFFAOYSA-N germanium disulfide Chemical compound S=[Ge]=S YIZVROFXIVWAAZ-UHFFFAOYSA-N 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0061—Timing circuits or methods
Definitions
- the present disclosure relates generally to memory devices, and more particularly to memory devices having memory elements that can have dynamic changes in impedance during read operations.
- Conventional memory devices typically access stored data values with read operations.
- Conventional read operations can access memory cells to generate read signals based on a state of one or more memory elements within the cell. Such read signals can be compared to some threshold value to thereby determine a value of the data stored (e.g., “1” or “0”).
- a value of the data stored e.g., “1” or “0”.
- Many memory devices seek to access data values as quickly as possible in a single read operation.
- resistive memory elements such as resistive random access memories (RRAMs)
- programmable elements may be driven with a voltage sufficient to ensure that such elements maintain a resistance value (e.g., high or low resistance) over an extended period of time.
- a resistance value e.g., high or low resistance
- driving programmable resistance elements in such a manner can affect device endurance.
- resistance values of programmed elements may change over time, presenting a data retention limit in such devices. Data retention and device endurance can be important aspects of a memory device in many applications.
- FIG. 1 is a flow diagram of a method of reading data from a memory device according to an embodiment.
- FIGS. 2A to 2C are timing diagrams showing a method of reading data from a programmable impedance element that includes selectively applying check conditions based on a detected element impedance.
- FIG. 3 is a graph showing a “breakdown” response of memory elements according to one embodiment.
- FIG. 4 is a flow diagram showing a method of reading data from a memory device according to another embodiment.
- FIG. 5A is a graph showing conventional static distributions of programmable resistance elements.
- FIG. 5B is a graph showing dynamic responses of resistance elements according to an embodiment.
- FIG. 6 is a flow diagram showing a method of reading data from a memory device according to a further embodiment.
- FIG. 7 is a graph showing time-to-breakdown distributions of programmable impedance elements according to an embodiment.
- FIG. 8 is a timing diagram showing a time-to-breakdown read operation according to an embodiment.
- FIG. 9 is a flow diagram showing a method of reading data from a memory device according to another embodiment.
- FIGS. 10A to 10C are block schematic diagrams showing read circuits and read operations of a memory device according to an embodiment.
- FIGS. 11A to 11D are timing diagrams comparing program pulses to check pulses according to embodiments.
- FIGS. 12A and 12B are timing diagrams showing read operations according to additional embodiments.
- FIG. 13 is a block schematic diagram of read circuits of a memory device according to another embodiment.
- FIG. 14 is a block schematic diagram of a memory device according to an embodiment.
- FIGS. 15A and 15B are timing diagrams showing read and related operations that can be included in an embodiment like that of FIG. 14 .
- FIG. 16 is a block schematic diagram of a memory device according to another embodiment.
- FIGS. 17A and 17B are timing diagrams showing read and related operations that can be included in an embodiment like that of FIG. 16 .
- FIG. 18 is a block schematic diagram of a memory device according to an embodiment.
- FIG. 19 is a state diagram of operations that can be executed by a memory device like that of FIG. 18 .
- FIG. 20 is a state diagram of other operations that can be executed by a memory device like that of FIG. 18 .
- the time required to induce a change in impedance can determine a stored data value.
- states of memory elements can be checked more than once, or extended over a period of time, after read operations determine an initial data state.
- a time to breakdown can be used alone, or in combination with other read techniques to determine a stored data value.
- program and/or “erase” operations. It is noted that such operations should not be construed as inducing any particular impedance state (i.e., low/high resistance), as such operations can induce changes in memory elements that vary according to technology. That is, while for some technologies a programming operation can lower impedance of an element, in other technologies, programming operations can alter a time to breakdown, increase impedance, or vary capacitance as just a few possible examples. Program and/or erase can be considered variations on write operations.
- the circuits and methods shown herein can include programmable memory elements that include a dielectric material disposed between two electrodes, where such a dielectric can include an ion conductor material.
- a dielectric can include an ion conductor material.
- such an ion conductor material can include germanium disulfide (GeS 2 ) with a metal therein (e.g., silver and/or copper).
- GeS 2 germanium disulfide
- alternate embodiments can include memory elements based on other materials, including silicon oxide (or silicon oxide-like) dielectrics, memory elements relying on graphene as a programmable matrix, and/or memory elements utilizing a metal oxide as a programmable material, such as titanium oxide, copper oxide, or other transition metal oxides, as but a few examples.
- a metal oxide as a programmable material, such as titanium oxide, copper oxide, or other transition metal oxides, as but a few examples.
- Any suitable programmable element structure can be employed in the embodiments
- FIG. 1 is a flow chart showing a method 100 according to one embodiment.
- a method 100 can include reading data from a memory cell ( 102 ). Unlike a conventional approach, which can generate output values from such read data, if the read data has a particular value, a read operation can be repeated to confirm the data value ( 104 ).
- confirming a data value can include applying “check conditions” to the memory cell that can apply energy to the memory cell to induce a change in memory cell properties.
- check conditions are not programming (or write) conditions.
- check conditions can include one or more electrical pulses and/or a continuation of the read conditions.
- check conditions can include the application of other forms of energy, such as heat, to storage elements of a memory cell.
- a read operation can continue or be repeated to ensure that the memory cell maintains the state.
- a method like that described above, or an equivalent, can be utilized in various memory types, as will be described in more detail below.
- a method can be particularly applicable to memory elements that store data according to impedance changes, such as a memory elements based on conductive bridging random access memory (CBRAM) type cells or programmable metallization cells (PMCs).
- CBRAM conductive bridging random access memory
- PMCs programmable metallization cells
- FIGS. 2A to 2C show a method of reading according to a particular embodiment.
- FIGS. 2A to 2C are timing diagrams showing an element impedance (Z_Element) over time (t).
- FIG. 2A shows a read operation of a memory element having a first state (shown as state 1) according to an embodiment.
- An impedance of a memory element (Z_Element) can be compared to a threshold impedance (Zth 1 ).
- Z_Element can be less than Zth 1 , which can be determined to be a valid state (e.g., output as a logic “1”).
- FIG. 2B shows a read operation of a memory element having a second state (shown as state 1′).
- An impedance of a memory element Z_Element
- Zth 1 threshold impedance
- Z_Element can initially be greater than Zth 1 .
- check conditions CHK
- check conditions are different from program or erase (or other write) conditions.
- an impedance of a memory element can be compared to a threshold impedance (Zth 2 ).
- Z_Element can be less than Zth 2 , which can be determined to be the stored data values (e.g., output as a logic “1”).
- FIG. 2C shows a read operation of a memory element having a third state (called 0, in this example).
- an impedance of a memory element can be initially compared to an initial threshold impedance (Zth 1 ), with the initial state not determining the stored data value.
- check conditions CHK
- an impedance of a memory element can be compared to threshold impedance (Zth 2 ).
- an impedance of Z_Element can be greater than Zth 2 , which can be determined to be a valid state (e.g., output as a logic “0”).
- an initial threshold impedance can be different from a threshold impedance following the application of check conditions (i.e., Zth 1 ⁇ Zth 2 ).
- FIGS. 2A to 2C describe read operations in which an element impedance can be checked to determine if it is greater than a threshold, in other embodiments an impedance of an element can be checked to determine if it is less than a threshold impedance, or checked to determine if it is within one or more bounded impedance ranges.
- Programmable impedance elements according to embodiments herein can exhibit dynamic changes during read operations.
- such changes can be relatively sudden, changing in relatively short time with respect to the application of check conditions.
- such changes can be more gradual, with an impedance of an element changing throughout, or during most of, the time when check conditions are applied.
- FIG. 3 shows responses of memory elements according to one particular embodiment.
- FIG. 3 is a graph showing a time to breakdown with respect to an applied voltage.
- the memory elements of FIG. 3 can include a dielectric or dielectric-type material between two electrodes.
- a check condition in this embodiment a voltage
- an element dielectric can “breakdown”, forming a substantially conductive path through the dielectric, where such a path was not previously present.
- a state of a programmable can be reversed back to the previous (non-breakdown, or high impedance/resistance) state.
- FIG. 3 includes with two curves, one representing a first state (0) of an element, the other representing a second state (1) of an element.
- a given check condition e.g., voltage
- the element state e.g., 1 or 0
- breakdown can occur at a different point in time.
- Such a characteristic can be used to store data values.
- programmable elements can store data values based on a dynamic change in impedance, as opposed to being based on a static impedance of such elements.
- RRAM resistive random access memory
- DRAM dynamic RAM
- EEPROMs electrically erasable and programmable read only memories
- FIG. 4 is a flow diagram showing a method 400 according to an embodiment.
- a method 400 can include reading a state of a cell ( 406 ). Such an action can include any of various read methods depending upon cell type. As but a few examples, reading a state of a cell can include detecting a current and/or voltage based on an impedance or change in impedance, including detecting a stored charge, as but a few possible examples.
- a determination can be made as to the memory cells state ( 408 ). In the embodiment shown, a determination can be made to check of the cell is a logic “1”. In some embodiments, such an action can include comparing a measured state of a cell to one or more limits, or thresholds. In a very particular embodiment, a logic “1” can correspond to a low cell resistance (e.g., a resistance less than a threshold).
- the memory cell can be determined to store that value ( 410 ).
- check conditions can be applied to the memory cell.
- application of check conditions can include applying one or more voltage pulses ( 412 ).
- Check condition voltage pulses are not of sufficient magnitude to write a particular data value into an element (e.g., can be below levels of pulses used to program or erase).
- a state of the memory cell can be checked again, which in the this particular embodiment can include determining if a resistance of the memory cell has dropped below a threshold value during, or in response to, the check conditions ( 414 ). If a memory cell is found to have one state (e.g., resistance has dropped below the threshold value), it can be determined to store one value, in this case a logic “1” ( 416 ). However, if a memory cell is found to have a different state (e.g., resistance has not dropped below the threshold value) it can be determined to store a different value, in this case a logic “0” ( 418 ).
- a method can include accessing a memory after applying check conditions to confirm that the memory cell stores a particular value.
- Method 400 of FIG. 4 should not be construed as being limited to any particular memory type. However, in embodiments having programmable resistance elements, a method 400 can reduce data retention requirements of a memory device.
- a cell programmed to one state e.g., low resistance
- another state e.g., high resistance
- a memory cell in such a state would result in erroneous data, as a high resistance would be detected when the cell was supposed to be programmed to a low resistance.
- a memory device can reprogram elements within a certain amount of time to ensure a low resistance state is maintained.
- a method 400 (or an equivalent method), application of check conditions can cause such a memory cell to change from a high resistance to a low resistance, without requiring a full programming operation and/or error check operation. This can result in substantially longer data retention times for such memory cells.
- FIGS. 5A and 5B are graphs comparing conventional memory cell data storage states to those according to one embodiment.
- FIG. 5A shows a conventional arrangement in which memory cells are programmed to one state “0”, can have a resistance above a threshold value (Rth). Memory cells programmed to another state “1”, can have a resistance below the threshold value (Rth).
- FIG. 5B shows memory cells according to an embodiment.
- Memory cells programmed to one state “0”, can have an impedance above a threshold value (Zth).
- memory cells programmed to the state “1”, can also have an impedance above the same threshold value (Zth).
- CHECK check conditions
- memory cells programmed to the state “1” can have an impedance that falls below the threshold value (Zth).
- memory cells programmed to the “0” state can have an impedance that remains above the threshold value (Zth). That is, in particular embodiments, a read operation induces a dynamic change in element impedance.
- Distribution shapes shown in FIG. 5B are exemplary. Distributions can have different shapes depending upon device structure, program and erase conditions, as well as check conditions.
- a read operation can include a continuous application of conditions to induce a change in impedance. Examples of such embodiments will now be described.
- FIG. 6 is a flow diagram showing a method 600 according to another embodiment.
- a method 600 can operate on elements having variations in breakdown time, such as those shown in FIG. 3 .
- Method 600 can include applying breakdown conditions to one or more memory elements ( 614 ).
- such an action can include applying a voltage across a memory element.
- a voltage can be a static voltage, or can be a series of voltage pulses, or other suitable dynamic waveforms.
- such an action can include applying different forms of energy, such as enabling heat flow to a memory element (i.e., into or out of a memory element).
- a determination of a memory element state can be made ( 616 ). Such an action can determine if a memory element is in a breakdown state.
- a breakdown state can result from a relatively fast change from one impedance to one or more other impedances under the applied breakdown conditions.
- a change to a breakdown state can be detected by a relatively fast decrease in voltage across an element and/or a relatively sudden increase in current through an element.
- the memory cell can be determined to store one data value ( 610 ) (in this case, a “1”).
- the memory cell can be determined to store a different data value ( 612 ) (in this case, a “0”).
- FIG. 6 shows a binary system
- alternate embodiments can include multiple threshold times for programmable elements capable of being written to more than two different states.
- a method can include determining a data value based on a time to breakdown of an element, as opposed to an impedance of the element.
- two or more data states can exhibit a time to breakdown under the applied breakdown conditions.
- elements in different states both end in the breakdown state, with one element taking longer than the other under the same conditions.
- FIG. 7 is a graph showing memory element responses according to one particular embodiment.
- FIG. 7 shows distributions of elements programmed into different states (“1” and “0”) versus a time-to-breakdown (t_brkdn).
- a time-to-breakdown can be the amount of time to induce a change in impedance in memory elements under the same time-to-breakdown conditions.
- the distribution of FIG. 7 can represent a response of elements like those shown in FIG. 3 and/or the response of elements included in the method of FIG. 6 .
- elements programmed to one state “1”, can have breakdown times less than a threshold time (T_threshold).
- Elements programmed to another state “0”, can have breakdown times greater than a threshold time (T_threshold).
- Distribution shapes shown in FIG. 7 are exemplary. Distributions can have different shapes depending upon device structure, program and erase conditions, as well as check conditions.
- FIG. 8 a timing diagram shows read operations according to an embodiment.
- FIG. 8 includes a number of waveforms: CELL CONDITIONS, which shows when bias conditions are applied to memory cells; MEMORY CELLi, which shows a response of a memory cell programmed to one state; and MEMORY CELLj, which shows a response of a memory cell programmed to another state.
- CELL STATE shows an impedance state of each memory cell.
- Di_OUT/Dj_OUT show data values corresponding to each memory cell.
- Such cells Prior to time t 0 , no bias conditions are applied to the cells. Further, such cells can have an initial, high impedance state (Hi-Z), which can be conceptualized as a “non-breakdown” state. At this time, an output value for such cells (Di_OUT/Dj_OUT) can be undetermined (represented by “?”).
- bias conditions can be applied to the memory cells.
- Such bias conditions can be conceptualized as breakdown inducing conditions.
- CELLi can “breakdown”, changing from a Hi-Z state to a lower impedance state (Lower-Z). Such an action can indicate the memory cell (CELLi) stores a data value “1”. As a result, Di_OUT can be determined to be “1”. At the same time, CELLj does not breakdown, maintaining a Hi-Z state.
- T_threshold a threshold time (T_threshold) can have passed since the application of the bias conditions.
- CELLj continues to have a Hi-Z state.
- Dj_OUT can be determined to be a “0”.
- FIG. 9 shows a method 900 according to yet another embodiment.
- a method 900 can operate on elements having variations in breakdown time, such as those shown in FIG. 3 .
- Method 900 can include reading a state of a cell ( 906 ). Such an action can include any of various read methods depending upon cell type. As but a few examples, such an action can detect a resistance, capacitance, or combination thereof. A determination can be made as to the memory cells state ( 908 ). In the embodiment shown, a determination can be made to check if the cell is a logic “1”. In a very particular embodiment, a logic “1” can correspond to a cell resistance being lower than some threshold resistance. In some embodiments, such a threshold resistance can be static.
- such a threshold resistance can be dynamic, changing during the sensing operation and/or changing according to a state of a device, including operating conditions (e.g., operating voltage or temperature) and/or wear level (number of read or write cycles performed).
- operating conditions e.g., operating voltage or temperature
- wear level number of read or write cycles performed
- the memory cell can be determined to store that value ( 910 ).
- a time required for a cell to switch from a first state (e.g., higher resistance) to a second state (e.g., lower resistance) can be measured ( 916 ). If a measured time is less than a reference time (YES from 916 ), a cell can be determined to have one state (in this case a “1”) ( 910 ). If a measured time is greater than a reference time (NO from 916 ), a cell can be determined to have another state (in this case a “0”) ( 912 ).
- the memory cell ends in a particular impedance state (e.g., low resistance).
- a time to breakdown (time to switch in impedance) can be used to determine a data value stored in a programmable element.
- FIGS. 10A to 10C show a read circuit and corresponding read operations according to one particular embodiment.
- Each of FIGS. 10A to 10C shows a device 1000 having read circuits (two shown as 1018 - 0 / 1 ), each of which can be connected to a memory element 1026 - 0 / 1 by a corresponding bit line 1028 - 0 / 1 .
- each read circuit 1018 - 0 / 1 can be connected to additional memory elements on the corresponding bit line 1028 - 0 / 1 .
- memory elements 1026 - 0 / 1 can be directly connected to a bit line 1028 - 0 / 1 or can be connected to a bit line through one or more access devices.
- bit lines 1028 - 0 / 1 can be connected to read circuits 1018 - 0 / 1 directly, or via one or more selection circuits.
- FIGS. 14 to 17B Particular array architectures of a device 1000 according to embodiments will be described in more detail below in FIGS. 14 to 17B .
- Memory elements 1026 - 0 / 1 can be programmable between two or more resistive states.
- memory elements 1028 - 0 / 1 can be programmed by application of one or more voltage pulses having a particular amplitude, polarity and duration. Further, in one embodiment, memory elements 1026 - 0 / 1 can respond like those shown in FIGS. 2A to 2C .
- sense circuits 1020 - 0 / 1 can be activated to sense a resistance of a corresponding memory element 1026 - 0 / 1 .
- Any suitable method can be utilized, including but not limited to: determining a current drawn by a memory element in response to a voltage and/or determining a voltage drop across a memory element.
- memory element 1026 - 0 can initially have a resistance less than a threshold resistance (R 0 ⁇ Rth). Such a value is sensed as a “1” by sense circuit 1020 - 0 , resulting in a “1” value being stored in store circuit 1022 - 0 .
- memory element 1026 - 1 can initially have a resistance greater than a threshold resistance (R 1 ⁇ Rth). This can be initially sensed as a “0” by sense circuit 1020 - 1 , resulting in a “0” value being stored in store circuit 1022 - 1 .
- a read operation can continue by applying check conditions to memory elements.
- the embodiment of FIG. 10B shows a selective application of a check conditions based on an initially sensed data value.
- a first value is sensed (in this case “1”)
- check conditions are not applied to the corresponding memory element.
- second value in this case “0”
- check conditions are applied to the corresponding element.
- the application of a check conditions can include applying a check voltage pulse (Vcheck) across a memory element.
- Vcheck check voltage pulse
- such a check voltage pulse can apply less energy than that used to program (or erase) a memory element.
- each pulse control circuit 1024 - 0 / 1 can be enabled by a value in the corresponding store circuit 1022 - 0 / 1 . Accordingly, because store circuit 1022 - 0 stores a first value, pulse control circuit 1024 - 0 can be disabled. However, because store circuit 1022 - 1 stores a second value, pulse control circuit 1024 - 1 can be enabled, allowing a check voltage pulse to be applied across memory element 1026 - 1 .
- a read operation can continue by sense circuit 1020 - 1 (and optionally sense circuit 1020 - 0 ) being activated once again to sense a resistance of a corresponding memory element.
- memory element 1026 - 1 has a resistance less than a check resistance (R 1 ⁇ Rchk).
- R 1 ⁇ Rchk a check resistance
- Such a value is sensed as a “1” by sense circuit 1020 - 1 , resulting in a “1” value being stored in store circuit 1022 - 1 .
- Rchk Rth in some embodiments.
- a memory device can store sensed resistance values, and selectively apply check conditions to memory elements having particular logic values.
- FIGS. 10A to 10C show selective application of check conditions
- other embodiments can include non-selective application of check conditions. That is, check conditions could be applied to memory elements regardless of a detected value.
- FIGS. 11A to 11D show various examples of program and check pulses according to embodiments.
- a program pulse can be a pulse used to establish a state of a programmable element.
- a check pulse can be applied to a programmable element to confirm a stored value, as described in the embodiments herein.
- FIGS. 11A to 11D are graphs showing an amplitude of a pulse (E) applied to a memory element with respect to time (t).
- FIG. 11A shows how a check pulse 1132 A can have a smaller amplitude than a program pulse 1130 A.
- FIG. 11B shows how a check pulse 1132 B can have a shorter duration than a program pulse 1130 B, but substantially a same amplitude.
- FIG. 11C shows how a check pulse 1132 C can have a shorter duration and smaller amplitude than a program pulse 1130 C.
- FIG. 11D shows how a number of check pulses 1132 D can be fewer than a number of program pulses 1130 D.
- a program operation can change an impedance from a high to low impedance
- other technologies such program operations can have different effects (e.g., changing a time to breakdown, increasing an impedance).
- pulses like those shown above can have a reverse polarity.
- pulses of one polarity can write one data value
- pulses of another polarity can write a different data value.
- pulse length, duration, number can be varied to write more than two states in the case of multi-state (greater than two states) memory elements.
- FIGS. 12A and 12B show read operations according to additional embodiments.
- FIGS. 12A and 12B can be one implementation of read operations like those show in FIGS. 2A to 2C , in which memory elements can have dynamic changes in impedance during a read operation.
- FIGS. 12A and 12B it is assumed that an electrical current or voltage pulse is applied across memory elements. In response to such a pulse, a sense signal can be generated from the memory elements.
- FIG. 12A is a timing diagram showing a response of three different memory cells CELLi, CELLj and CELLk.
- the timing diagram includes sense signals (I_Celli, I_Cellj, I_Cellk) generated for three different memory cells, as well as data values (DATAi_out, DATAj_out, DATAk_out) corresponding to such sense signals.
- sense signals I_Celli, I_Cellj, I_Cellk
- a read electrical pulse can be applied to the memory cells.
- Sense signal I_Celli can exceed a read threshold Th_Read, and thus generate a data value “1”.
- sense signals I_Cellj and I_Cellk are both below level Th_Read, and thus generate initial data values “0”.
- a check pulse can be applied to those memory cells generating a data value “0”, which in this case can be memory cells CELLj and CELLk. In the embodiment shown, the check pulse is not applied to memory cell CELLi. However, as noted above, alternate embodiments can have a non-selective application of a check pulses.
- a second read electrical pulse can be applied to at least those cells generating a value “0”.
- sense signal I_Cellj can exceed a check threshold Th_Check, and thus its corresponding data value can be changed from “0” to “1”.
- sense signal I_Cellk can remain below level Th_Check, and thus its corresponding data value can continue to be “0”.
- data values (DATAi_out, DATAj_out, DATAk_out) can be output as valid data values.
- FIG. 12A shows an arrangement in which a check threshold is different than a read threshold (in this case lower than).
- FIG. 12B shows a response of two different memory cells CELLi and CELLj, including sense signals (I_Celli, I_Cellj) generated for two different memory cells, as well as data values (DATAi_out, DATAj_out) corresponding to such sense signals.
- sense signals I_Celli, I_Cellj
- data values DATAi_out, DATAj_out
- sense signals can be sensed current values, sensed voltage values, or combinations thereof.
- FIGS. 12A and 12B show sense signals that rise in response to impedance changes
- other embodiments can include sense signals that fall, or have other dynamic responses. That is, FIGS. 12A and 12B show but one of many possible sensing approaches, and so should not be construed as limiting.
- FIG. 13 shows a read circuit 1300 according to another embodiment.
- FIG. 13 shows a device 1300 that can read data from memory elements (two shown as 1326 - 0 / 1 ) that can be programmable between two or more states having different times to breakdown, as described in embodiments above, or equivalents.
- memory elements 1326 - 0 / 1 can be programmed by application of one or more voltage pulses having a particular amplitude, polarity and duration.
- memory elements 1326 - 0 / 1 can respond like those shown in FIG. 3 .
- a device 1300 can include read circuits ( 1334 - 0 / 1 ), bit lines ( 1328 - 0 / 1 ), a timer circuit 1336 , and an input/output (I/O) path 1338 .
- each read circuit 1334 - 0 / 1 can be connected to additional memory elements on a corresponding bit line 1328 - 0 / 1 .
- memory elements 1326 - 0 / 1 can be directly connected to a bit line 1328 - 0 / 1 or can be connected to a bit line through one or more access devices.
- bit lines 1328 - 0 / 1 can be connected to read circuits 1334 - 0 / 1 directly, or via one or more access devices.
- Each read circuit 1334 - 0 / 1 can include a sense circuit 1320 - 0 / 1 , a store circuit 1322 - 0 / 1 , and a control circuit 1340 - 0 / 1 .
- sense circuits 1320 - 0 / 1 can be periodically activated to determine if a “breakdown” condition has occurred.
- sense circuits ( 1320 - 0 / 1 ) can include logic to determine which value to output to a corresponding store circuit ( 1322 - 0 / 1 ) based on inputs from timing circuit 1336 . More particularly, a value output from sense circuits ( 1320 - 0 / 1 ) can vary based on the time of a sensing operation performed by the sense circuits ( 1320 - 0 / 1 ).
- control circuits 1340 - 0 / 1 can activate corresponding sense circuits 1320 - 0 / 1 . If sense circuits 1320 - 0 / 1 detect breakdown in an initial period they can output one logic value, but if a breakdown is not detected within the initial period, a different logic value can be output. It is understood that while FIG. 13 shows a binary case, in which sense circuits can output 1 for one time period, and 0 afterward, in a multi-bit case, sense circuits can output multi-bit values as sense circuits checked for breakdown in each subsequent time period.
- Results from operations of sense circuits 1334 - 0 / 1 can be stored as data values in corresponding store circuits 1322 - 0 / 1 .
- control circuits 1340 - 0 / 1 can selectively activate sense circuits based on a data value held within a corresponding store circuit 1322 - 0 / 1 .
- a corresponding sense circuit can be disabled.
- a status of memory elements 1326 - 0 / 1 can be checked at subsequent points in time, with a time required to cause a change in state (e.g., breakdown) indicating a particular value.
- a change in state e.g., breakdown
- FIG. 14 shows a memory device architecture 1400 according to a particular embodiment.
- Memory device 1400 can include one or more arrays (one shown as 1440 ) of memory cells arranged into rows and columns.
- Each memory cell e.g., 1440
- Each memory cell can include a memory element (e.g., 1426 ) and an access device (e.g., 1446 ).
- a memory element e.g., 1426
- a memory element can be programmable between at least two different impedance states, as described herein and equivalents.
- Memory cells of a same row can be connected to the same word line ( 1444 - 0 to -m), while memory cells of a same column can be connected to a same bit line ( 1428 - 0 to -n).
- a row decoder 1442 can receive row address values, and in response, activate a word line ( 1444 - 0 to -m). When activated, a word line ( 1444 - 0 to -m) can enable (e.g., makes conductive) corresponding access devices (e.g., 1446 ), thereby electrically connecting the corresponding memory element (e.g., 1426 ) to a bit line ( 1428 - 0 to -n).
- FIG. 14 shows potentials corresponding to the activation of word line 1444 - 1 .
- Word line 1444 - 1 can be driven to a select potential (VWL_Sel), while the remaining word lines ( 1444 - 0 , -m) can remain at a de-select potential (VWL_Des).
- FIG. 14 also shows bit line voltages for two possible operations: a selective check operation (shown by row “Check”) and a read-to-breakdown operation (shown by “Breakdown” Read).
- a selective check operation can include a check operation for devices having states like those shown in FIGS. 2A to 2C , or equivalents.
- a “Breakdown” Read operation can show a read operation for device having states like those shown in FIG. 3 , or equivalents.
- Check operation it is assumed that Check operation applies check conditions to the memory cell 1440 , and not other memory cells of the same row. Consequently, bit lines 1428 - 1 can be driven to a check voltage VBL_Check, while other bit lines (corresponding to cells that will not have check conditions applied) can be placed a voltage VBL_Des.
- a memory device with access devices can read data values from memory elements by applying check conditions to induce changes in impedance, and/or that read data values based on variations in breakdown times.
- FIG. 15A shows one very particular example of a check operation like that noted for FIG. 14 .
- FIG. 15A is a timing diagram having waveforms for a selected word line (WL(Sel)), a de-selected word line (WL(Des)), a selected bit line (BL(Sel)), and a de-selected bit line (BL(Des)).
- a selected word line (WL(Sel)) can be driven to a select potential (in this embodiment rise in potential).
- This can enable (i.e., place into low impedance state) access devices (e.g. 1446 ) of a corresponding row, connecting memory elements (e.g., 1440 ) of the accessed row to corresponding bit lines ( 1428 - 0 to -n).
- De-selected word lines (e.g., 1444 - 0 , m) can remain at a de-select potential (which in this embodiment can be a low potential).
- This can disable (e.g., place into high impedance state) access devices (e.g. 1446 ) of a non-accessed rows, isolating memory elements (e.g., 1440 ) of the non-accessed rows from bit lines (e.g., 1428 - 0 to -m).
- a selected bit line BL(Sel) (e.g., 1428 - 1 ) can be driven with check voltage (in this embodiment rise in potential).
- check voltage may result in a change in impedance (or result in no change in impedance) depending upon a state of the accessed element.
- a selected bit line BL(Sel) (e.g., 1428 - 1 ) can return to a previous level, removing the check conditions from the selected memory element.
- a selected word line (WL(Sel)) can return to the de-select potential (in this embodiment, return to a lower potential).
- bit lines can be maintained at one potential, and opposing terminals (i.e., those terminals opposite the bit lines) of memory elements can be driven to the check potential.
- FIG. 15B shows one very particular example of a “Breakdown” Read operation like noted for FIG. 14 .
- FIG. 15B is a timing diagram having waveforms for a selected word line (WL(Sel)), a de-selected word line (WL(Des)), and two bit lines (BLi and BLj).
- bit lines (BLi, BLj) can be driven to a breakdown potential (in this embodiment a rise in potential).
- a selected word line (WL(Sel)) can be driven to a select potential to enable access devices of the corresponding row.
- De-selected word lines can be at a de-selected potential, in the same manner as FIG. 15A . Consequently, a breakdown voltage can be applied across memory elements of the corresponding row.
- a potential on one bit line BLi can fall, indicating a breakdown event in the corresponding memory element.
- a breakdown event can indicate a first type value is stored in the corresponding memory element.
- a potential on bit line BLj can fall, indicating a subsequent breakdown event in the corresponding memory element.
- Such a breakdown event can indicate a second type value is stored in the corresponding memory element.
- FIG. 16 shows another memory device architecture 1600 according to embodiments.
- Architecture 1600 shows a “cross-point” array, which can provide an advantageously compact memory size.
- Memory elements two shown as 1626 , 1627
- Memory elements can be two terminal elements programmable between at least two different states, as described herein and equivalents.
- Memory elements (e.g., 1626 , 1627 ) of a same row can be connected to the same row line ( 1648 - 0 to -m), while memory elements of a same column can be connected to a same bit line ( 1628 - 0 to -n).
- a row decoder 1642 can receive row address values ROW ADD, and in response, drive row lines ( 1648 - 0 to -m) between select and de-select levels. Examples of such levels will be described in more detail below.
- a memory device that reads data values from memory elements by applying check conditions, or relying on variations in breakdown times, can include a cross-point array type architecture.
- FIG. 17A shows a check operation according to one embodiment for a memory device like that shown in FIG. 16 .
- FIG. 17A is a timing diagram that includes waveforms for row lines (Rline) and bit lines (BL).
- a check operation results in a check pulse being applied to memory element 1626 , and not any other memory elements. Accordingly, a row line 1648 - 1 (Rline — 1) corresponding to the selected memory element 1626 can be driven to a row select voltage (VRSEL), while the other row lines 1648 - 0 , 1648 - 2 to -m (e.g., Rline — 0, Rline_m) can remain at a row deselect voltage (VRDES). In the particular embodiment shown, a row select voltage (VRSEL) can be positive with respect to the row deselect voltage (VRDES).
- a bit line 1628 - 1 (BL — 1) corresponding to a selected memory element 1626 can be driven to a column select voltage (VCSEL), while other bit lines 1628 - 0 , 1628 - 2 to -m (e.g. BL — 0, BL_n) can remain at a column deselect voltage (VCDES).
- VCSEL column select voltage
- a column select voltage (VCSEL) can be negative with respect to the column deselect voltage (VCDES).
- a check conditions applied across a memory element can be smaller in potential, shorter in duration, or a combination thereof, as compared to conditions used to write particular values into such a memory element.
- FIG. 17B shows a “Breakdown” Read operation according to one embodiment for an architecture like that of FIG. 16 .
- FIG. 17B is a timing diagram showing waveforms for row lines (Rline) and two bit lines (BL — 1, BL_n).
- a read operation accesses the row corresponding to row line 1648 - 1 (Rline — 1). It is also assumed that memory element 1626 is programmed to one state (e.g., a shorter time to breakdown), while memory element 1627 of the same row is programmed to another state (e.g., a longer time to breakdown).
- row lines ( 1648 - 0 to -m) can be driven to a row deselect voltage VRDES, while bit lines ( 1628 - 0 to -n) can be driven to a bit line deselect voltage VCDES.
- a row line of a selected row (in this example 1648 - 1 , Rline — 1) can be driven to a row select voltage (VRSEL), while the other row lines (e.g., 1648 - 0 , 1648 - 2 to -m) can remain at a deselect voltage (VRDES).
- a row select voltage (VRSEL) can be positive with respect to the row deselect voltage (VRDES).
- bit lines ( 1628 - 0 to -n) can be driven to a bit line read voltage (VBLread), which can be negative with respect to the bit line deselect voltage (VCDES).
- VBLread bit line read voltage
- VCDES bit line deselect voltage
- bit line voltages can return to a de-select voltage when a memory element reaches the “breakdown” state.
- memory element 1626 can reach a breakdown state, thus the corresponding bit line BL — 1( 1628 - 1 ) can return to the bit line deselect voltage (VCDES).
- VCDES bit line deselect voltage
- memory element 1627 is programmed to a different state, at about time t 2 , memory element 1627 can reach a breakdown state, and corresponding bit line BL_n ( 1628 - n ) can return to the bit line deselect voltage (VCDES).
- VCDES bit line deselect voltage
- row/bit line select and de-select voltages of FIG. 17A can be different from those of FIG. 17B .
- FIG. 18 shows a memory device 1800 according to one embodiment.
- a memory device 1800 can include an array 1850 , a row driver 1858 , sense amplifiers 1852 , latch circuits 1854 , pulse generation circuits 1856 , input output (I/O) circuits 1838 , a column select circuit 1864 , an address decoder 1860 , and a controller 1862 .
- An array 1850 can include a number of memory cells arranged into rows and columns.
- each memory cell can include only a memory element (e.g., a cross-point array), while in other embodiments each memory cell can include one or more access devices and one or more memory elements.
- Rows of memory cells within array 1850 can be activated or accessed by a row driver circuit 1842 .
- Memory cells within array 1850 can store data in binary, or multi-bit (i.e., more than two states) form.
- Memory elements within array 1850 can be programmed between two or more different impedance states. In particular embodiments, such different impedance states result in different dynamic responses during a read operation.
- Sense amplifiers 1852 can read data values from a row of accessed memory cells.
- Sense amplifiers 1852 can be circuits suitable for detecting a state of a programmable impedance element (or elements) of accessed memory cells. As but two examples, sense amplifiers can be current or voltage sense amplifiers.
- Sense amplifiers 1852 can compare sensed signals to one or more threshold levels to generate sensed data values.
- Latch circuits 1854 can latch sensed data values generated by sense amplifiers 1852 .
- data values initially latched in latch circuits 1854 are not necessarily the data values output from memory devices.
- Pulse generation circuits 1856 can generate electrical pulses of predetermined amplitude and duration to enable data values to be written (e.g., programmed and/or erased) into memory cells of array 1850 .
- pulse generation circuit 1856 can generate electrical pulses to subject programmable impedance elements to check conditions that can confirm a read data value, as described herein and equivalents.
- pulse generation circuit 1856 can generate read electrical pulses to read data values based on breakdown time of memory elements within array 1850 .
- I/O circuits 1838 can provide output read data paths and input write data paths to array 1850 .
- Column select circuits 1864 can selectively connect columns of array 1850 to I/O circuits 1838 based on column select values provided from address decoder 1860 .
- Column select circuits 1864 can be placed between sense amplifiers 1852 and I/O circuits 1838 (e.g., a sense amplifier is provided for every array column), or alternatively, between sense amplifiers 1852 and array 1850 (e.g., each sense amplifier is multiplexed between multiple array columns).
- Address decoder 1860 can receive address values ADD, and generate row select and column select values for row driver 1858 and column select circuits 1864 , respectively.
- a controller 1862 can receive command information (CMD), and in response, generate control signals for sense amplifiers 1852 , latch circuits 1854 , and pulse generation circuits 1856 , according to a determined mode of operation.
- CMD command information
- a controller 1862 can include circuits for enabling program and erase operations.
- a controller 1862 can generate signals that enable read operations according to the various embodiments described herein, and equivalents, including read operations that apply “check” conditions and/or read operations that determine a data value based on a time to breakdown.
- FIG. 19 shows one example of operations executable by a controller, such as that shown as 1862 in FIG. 18 .
- the embodiment of FIG. 19 shows controller operations that can execute read operations that apply check conditions, as described herein and equivalents.
- memory elements can be programmed to one impedance state and erased to another impedance state.
- a controller can generate signals for writing a particular data value to memory cells at one or more addresses ( 1976 ).
- a controller can generate control signals that cause one or more electrical pulses of a second polarity to be applied to memory cells within an array. Such pulses can place memory elements in a different state than the erase state.
- a program operation can be preceded by an erase operation. That is, a group of memory cells can be erased, and then selected of the erased memory cells can be programmed.
- CMD Read
- a controller can generate signals for applying electrical pulses of different types to memory cells based on received write data ( 1978 ).
- a controller can indicate that check conditions have not been applied for the current read operation ( 1980 ).
- a memory device my include a controller for executing a “two read” operation that enables reading data from memory cells, applying a check pulse to such memory cells, and then confirming the read data values.
- FIG. 20 shows operations executable by a controller, such as that shown as 1862 in FIG. 18 , according to another embodiment.
- the embodiment of FIG. 20 shows an example of a controller that can execute read operations that determine data values based on a time to breakdown of an accessed memory element.
- a controller Upon receiving a command ( 2070 ) a controller can decode command data ( 2072 ) to perform erase ( 2074 ), program ( 2076 ), or alternatively write operations ( 2078 ), in a manner like that described above for FIG. 19 . However, it is understood that such operations can establish different breakdown times for such data elements.
- FIG. 20 shows a controller determining two data values, with additional threshold times, a same approach can determine more than two data values.
- a memory device can employ conventional read operations (e.g., compare memory element resistance to threshold to determine data stored) under predetermined conditions.
- Such conditions can include: the storage location has previously been accessed within a certain period of time, the storage location is below a wear threshold level (i.e., the number of program and/or erase operations), the device is operating in a higher voltage mode (voltages applied to elements is increased), as but a few examples.
- a memory device and method according to the embodiments may be included in a standalone memory device (i.e., a memory device providing substantially only storage functions). In alternate embodiments, such a memory device may be embedded into larger integrated circuit device.
Abstract
Description
Claims (33)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/276,763 US8654561B1 (en) | 2010-10-29 | 2011-10-19 | Read methods, circuits and systems for memory devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US40823110P | 2010-10-29 | 2010-10-29 | |
US13/276,763 US8654561B1 (en) | 2010-10-29 | 2011-10-19 | Read methods, circuits and systems for memory devices |
Publications (1)
Publication Number | Publication Date |
---|---|
US8654561B1 true US8654561B1 (en) | 2014-02-18 |
Family
ID=50072178
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/276,763 Expired - Fee Related US8654561B1 (en) | 2010-10-29 | 2011-10-19 | Read methods, circuits and systems for memory devices |
Country Status (1)
Country | Link |
---|---|
US (1) | US8654561B1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8913444B1 (en) | 2011-03-01 | 2014-12-16 | Adesto Technologies Corporation | Read operations and circuits for memory devices having programmable elements, including programmable resistance elements |
US9099175B1 (en) | 2011-03-01 | 2015-08-04 | Adesto Technologies Corporation | Memory devices and methods for read and write operation to memory elements having dynamic change in property |
US9177639B1 (en) * | 2010-12-09 | 2015-11-03 | Adesto Technologies Corporation | Memory devices, circuits and methods having data values based on dynamic change in material property |
US10236053B1 (en) | 2017-10-17 | 2019-03-19 | R&D 3 Llc | Method and circuit device incorporating time-to-transition signal node sensing |
US11107535B2 (en) | 2019-09-10 | 2021-08-31 | Adesto Technologies Corporation | Memory device with adaptive noise and voltage suppression during read-while-write operations |
US11501826B2 (en) | 2017-10-17 | 2022-11-15 | R&D3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US11537754B1 (en) | 2018-09-18 | 2022-12-27 | Adesto Technologies Corporation | Pseudo physically unclonable functions (PUFS) using one or more addressable arrays of elements having random/pseudo-random values |
Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5761115A (en) | 1996-05-30 | 1998-06-02 | Axon Technologies Corporation | Programmable metallization cell structure and method of making same |
US6487106B1 (en) | 1999-01-12 | 2002-11-26 | Arizona Board Of Regents | Programmable microelectronic devices and method of forming and programming same |
US6635914B2 (en) | 2000-09-08 | 2003-10-21 | Axon Technologies Corp. | Microelectronic programmable device and methods of forming and programming the same |
US20060139989A1 (en) | 2004-12-21 | 2006-06-29 | Infineon Technologies Ag | Integration of 1T1R CBRAM memory cells |
US7106614B2 (en) | 2004-04-19 | 2006-09-12 | Infineon Technologies Ag | Memory circuit and method for providing an item of information for a prescribed period of time |
US7126152B2 (en) | 2003-12-03 | 2006-10-24 | Sony Corporation | Storage device |
US7167390B2 (en) | 2003-05-27 | 2007-01-23 | Sony Corporation | Storage device with resistive memory cells enduring repetitive data writing |
US7209379B2 (en) | 2004-09-30 | 2007-04-24 | Sony Corporation | Storage device and semiconductor device |
US7239542B2 (en) | 2004-10-08 | 2007-07-03 | Sony Corporation | Storage apparatus |
US7242606B2 (en) | 2004-09-29 | 2007-07-10 | Sony Corporation | Storage apparatus and semiconductor apparatus |
US7359236B2 (en) | 2005-03-11 | 2008-04-15 | Adesto Technologies | Read, write and erase circuit for programmable memory devices |
US7411854B2 (en) | 2006-04-18 | 2008-08-12 | Infineon Technologies Ag | System and method for controlling constant power dissipation |
US7426131B2 (en) | 2005-11-01 | 2008-09-16 | Adesto Technologies | Programmable memory device circuit |
US7457145B2 (en) | 2004-03-31 | 2008-11-25 | Infineon Technologies Ag | Write/delete process for resistive switching memory components |
US7508709B2 (en) * | 2005-07-19 | 2009-03-24 | Hynix Semiconductor Inc. | Page buffer circuit with reduced size and methods for reading and programming data with the same |
US7514706B2 (en) | 2005-10-14 | 2009-04-07 | Adesto Technologies | Voltage reference circuit using programmable metallization cells |
US20100195370A1 (en) | 2009-02-05 | 2010-08-05 | Sony Corporation | Nonvolatile semiconductor memory device and method for performing verify write operation on the same |
US8203899B2 (en) * | 2008-10-31 | 2012-06-19 | Seagate Technology Llc | Memory cell with proportional current self-reference sensing |
-
2011
- 2011-10-19 US US13/276,763 patent/US8654561B1/en not_active Expired - Fee Related
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5761115A (en) | 1996-05-30 | 1998-06-02 | Axon Technologies Corporation | Programmable metallization cell structure and method of making same |
US6487106B1 (en) | 1999-01-12 | 2002-11-26 | Arizona Board Of Regents | Programmable microelectronic devices and method of forming and programming same |
US6635914B2 (en) | 2000-09-08 | 2003-10-21 | Axon Technologies Corp. | Microelectronic programmable device and methods of forming and programming the same |
US7167390B2 (en) | 2003-05-27 | 2007-01-23 | Sony Corporation | Storage device with resistive memory cells enduring repetitive data writing |
US7126152B2 (en) | 2003-12-03 | 2006-10-24 | Sony Corporation | Storage device |
US7457145B2 (en) | 2004-03-31 | 2008-11-25 | Infineon Technologies Ag | Write/delete process for resistive switching memory components |
US7106614B2 (en) | 2004-04-19 | 2006-09-12 | Infineon Technologies Ag | Memory circuit and method for providing an item of information for a prescribed period of time |
US7242606B2 (en) | 2004-09-29 | 2007-07-10 | Sony Corporation | Storage apparatus and semiconductor apparatus |
US7209379B2 (en) | 2004-09-30 | 2007-04-24 | Sony Corporation | Storage device and semiconductor device |
US7239542B2 (en) | 2004-10-08 | 2007-07-03 | Sony Corporation | Storage apparatus |
US20060139989A1 (en) | 2004-12-21 | 2006-06-29 | Infineon Technologies Ag | Integration of 1T1R CBRAM memory cells |
US7359236B2 (en) | 2005-03-11 | 2008-04-15 | Adesto Technologies | Read, write and erase circuit for programmable memory devices |
US7508709B2 (en) * | 2005-07-19 | 2009-03-24 | Hynix Semiconductor Inc. | Page buffer circuit with reduced size and methods for reading and programming data with the same |
US7514706B2 (en) | 2005-10-14 | 2009-04-07 | Adesto Technologies | Voltage reference circuit using programmable metallization cells |
US7426131B2 (en) | 2005-11-01 | 2008-09-16 | Adesto Technologies | Programmable memory device circuit |
US7411854B2 (en) | 2006-04-18 | 2008-08-12 | Infineon Technologies Ag | System and method for controlling constant power dissipation |
US8203899B2 (en) * | 2008-10-31 | 2012-06-19 | Seagate Technology Llc | Memory cell with proportional current self-reference sensing |
US20100195370A1 (en) | 2009-02-05 | 2010-08-05 | Sony Corporation | Nonvolatile semiconductor memory device and method for performing verify write operation on the same |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9177639B1 (en) * | 2010-12-09 | 2015-11-03 | Adesto Technologies Corporation | Memory devices, circuits and methods having data values based on dynamic change in material property |
US8913444B1 (en) | 2011-03-01 | 2014-12-16 | Adesto Technologies Corporation | Read operations and circuits for memory devices having programmable elements, including programmable resistance elements |
US9099175B1 (en) | 2011-03-01 | 2015-08-04 | Adesto Technologies Corporation | Memory devices and methods for read and write operation to memory elements having dynamic change in property |
US10629256B2 (en) | 2017-10-17 | 2020-04-21 | R&D 3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US10269413B1 (en) | 2017-10-17 | 2019-04-23 | R&D 3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
WO2019078971A1 (en) * | 2017-10-17 | 2019-04-25 | R&D 3 Llc | Memory having variable impedance cells and time-to-transition data sensing |
US10236053B1 (en) | 2017-10-17 | 2019-03-19 | R&D 3 Llc | Method and circuit device incorporating time-to-transition signal node sensing |
US10796748B2 (en) | 2017-10-17 | 2020-10-06 | R&D 3 Llc | Method and circuit device incorporating time-to-transition signal node sensing |
US10796749B2 (en) | 2017-10-17 | 2020-10-06 | R&D 3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US11049553B2 (en) | 2017-10-17 | 2021-06-29 | R&D 3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US11195574B2 (en) | 2017-10-17 | 2021-12-07 | R&D 3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US11501826B2 (en) | 2017-10-17 | 2022-11-15 | R&D3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US11783891B2 (en) | 2017-10-17 | 2023-10-10 | R&D 3 Llc | Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein |
US11537754B1 (en) | 2018-09-18 | 2022-12-27 | Adesto Technologies Corporation | Pseudo physically unclonable functions (PUFS) using one or more addressable arrays of elements having random/pseudo-random values |
US11107535B2 (en) | 2019-09-10 | 2021-08-31 | Adesto Technologies Corporation | Memory device with adaptive noise and voltage suppression during read-while-write operations |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11615844B2 (en) | Apparatuses and methods including memory and operation of same | |
KR101460954B1 (en) | Stabilization of resistive memory | |
US8654561B1 (en) | Read methods, circuits and systems for memory devices | |
JP5521612B2 (en) | Nonvolatile semiconductor memory device | |
TWI480873B (en) | Non-volatile semiconductor memory device | |
US10410718B2 (en) | Apparatuses and methods for current limitation in threshold switching memories | |
US9001561B2 (en) | Performing forming processes on resistive memory | |
US8854873B1 (en) | Memory devices, architectures and methods for memory elements having dynamic change in property | |
US20220223212A1 (en) | Multi-state programming of memory cells | |
KR20130128458A (en) | Resistive memory sensing methods and devices | |
US10402098B2 (en) | Nonvolatile memory apparatus and verification write method thereof for reducing program time | |
KR20100097407A (en) | Resistive memory device, memory system including the same, and programming method of the same | |
CN114902334A (en) | Tri-state programming of memory cells | |
CN116114021B (en) | Programming memory cells using asymmetric current pulses | |
US11328770B2 (en) | Semiconductor storage device | |
US11915752B2 (en) | Resistive memory with enhanced redundancy writing | |
TWI760924B (en) | Methods and systems for accessing memory cells | |
US9177639B1 (en) | Memory devices, circuits and methods having data values based on dynamic change in material property | |
CN115731987A (en) | Semiconductor device with a plurality of semiconductor chips |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ADESTO TECHNOLOGIES CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JAMESON, JOHN ROSS;DINH, JOHN;LEWIS, DERRIC;AND OTHERS;SIGNING DATES FROM 20120109 TO 20120118;REEL/FRAME:027636/0341 |
|
AS | Assignment |
Owner name: OPUS BANK, CALIFORNIA Free format text: SECURITY AGREEMENT;ASSIGNORS:ADESTO TECHNOLOGIES CORPORATION;ARTEMIS ACQUISITION LLC;REEL/FRAME:029090/0922 Effective date: 20120927 |
|
AS | Assignment |
Owner name: ARTEMIS ACQUISITION LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OPUS BANK;REEL/FRAME:031414/0232 Effective date: 20131009 Owner name: ADESTO TECHNOLOGIES CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OPUS BANK;REEL/FRAME:031414/0232 Effective date: 20131009 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: OPUS BANK, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNORS:ADESTO TECHNOLOGIES CORPORATION;ARTEMIS ACQUISITION LLC;REEL/FRAME:035754/0580 Effective date: 20150430 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNORS:ADESTO TECHNOLOGIES CORPORATION;ARTEMIS ACQUISITION LLC;REEL/FRAME:046105/0731 Effective date: 20180508 Owner name: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGEN Free format text: SECURITY INTEREST;ASSIGNORS:ADESTO TECHNOLOGIES CORPORATION;ARTEMIS ACQUISITION LLC;REEL/FRAME:046105/0731 Effective date: 20180508 |
|
AS | Assignment |
Owner name: ADESTO TECHNOLOGIES CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OPUS BANK;REEL/FRAME:049125/0970 Effective date: 20160707 Owner name: ARTEMIS ACQUISITION LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OPUS BANK;REEL/FRAME:049125/0970 Effective date: 20160707 |
|
AS | Assignment |
Owner name: ADESTO TECHNOLOGIES CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT;REEL/FRAME:050480/0836 Effective date: 20190923 Owner name: ARTEMIS ACQUISITION LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT;REEL/FRAME:050480/0836 Effective date: 20190923 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20220218 |