|Numéro de publication||US8871646 B2|
|Type de publication||Octroi|
|Numéro de demande||US 13/947,792|
|Date de publication||28 oct. 2014|
|Date de dépôt||22 juil. 2013|
|Date de priorité||24 nov. 2008|
|Autre référence de publication||CN102224569A, CN102224569B, EP2353172A2, EP2353172A4, US8492282, US20100130016, US20130309871, WO2010059441A2, WO2010059441A3|
|Numéro de publication||13947792, 947792, US 8871646 B2, US 8871646B2, US-B2-8871646, US8871646 B2, US8871646B2|
|Cessionnaire d'origine||Micron Technology, Inc.|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Citations de brevets (217), Citations hors brevets (22), Référencé par (8), Classifications (20), Événements juridiques (3)|
|Liens externes: USPTO, Cession USPTO, Espacenet|
This application is a continuation of U.S. patent application Ser. No. 12/546,466, filed Aug. 24, 2009, entitled METHODS OF FORMING A MASKING PATTERN FOR INTEGRATED CIRCUITS, which claims the priority benefit under 35 U.S.C. §119(e) of Provisional Application Ser. No. 61/117,526, filed Nov. 24, 2008. The full disclosures of the priority application are incorporated herein by reference.
1. Field of the Invention
This invention relates generally to integrated circuit fabrication and, more particularly, to masking techniques.
2. Description of the Related Art
As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency, integrated circuits are continuously being made more dense. The sizes of the constituent features that form the integrated circuits, e.g., electrical devices and interconnect lines, are constantly being decreased to facilitate this scaling.
The trend of decreasing feature size is evident, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), flash memory, static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically comprises millions of identical circuit elements, known as memory cells. In general, a capacitor-based memory cell, such as in conventional DRAM, typically consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell through the transistor and can be read by sensing charge in the capacitor. Some memory technologies employ elements that can act as both a storage device and a switch (e.g., dendritic memory employing silver-doped chalcogenide glass) and some nonvolatile memories do not require switches for each cell (e.g., magnetoresistive RAM). In addition, in some technologies, some elements can act as both charge storage and charge sensing devices. For example, this is the case with flash memory, thus, allowing this type of memory to have one of the smallest cell sizes (4F2) of all memory technologies. In general, by decreasing the sizes of the electrical devices that constitute a memory cell and the sizes of the conducting lines that access the memory cells, the memory devices can be made smaller. Additionally, storage capacities can be increased by fitting more memory cells on a given area in the memory devices.
The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to pattern features, such as conductive lines. The concept of pitch can be used to describe the sizes of these features. Pitch is defined as the distance between an identical point in two neighboring features when the pattern includes repeating features, as in arrays. These features are typically defined by spaces between adjacent features, which spaces are typically filled by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature. However, due to factors such as optics and light or radiation wavelength, photolithography techniques each have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Thus, the minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction.
“Pitch doubling” or “pitch multiplication” is one method for extending the capabilities of photolithographic techniques beyond their minimum pitch. A pitch multiplication method is illustrated in
While the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.” Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. The conventional terminology is retained herein.
Because a spacer pattern typically follows the outlines of mandrels, pitch multiplication is generally useful for forming regularly spaced linear features, such as conductive interconnect lines in a memory array. However, in addition to features which extend linearly over relatively large distances (e.g., conductive interconnect lines), integrated circuits typically contain features having various shapes and sizes which can be difficult to form by conventional pitch multiplication processes. In addition, the continuing reduction in the sizes of integrated circuits has provided a continuing demand for reductions in the sizes of features.
Accordingly, there is a continuing need for methods of forming features having a small pitch and high density.
The invention will be better understood from the Detailed Description of the Preferred Embodiments and from the appended drawings, which are meant to illustrate and not to limit certain embodiments of the invention, and wherein:
In the context of this document, the term “integrated circuit (IC) device” refers to a semiconductor device, including, but not limited to, a memory device and a microprocessor. The memory device may be a volatile memory such as a random access memory (RAM) or non-volatile memory such as a read-only memory (ROM). Examples of RAMs include dynamic random access memories (DRAMs) and static random access memories (SRAMs). Examples of ROMs include programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), electrically-erasable programmable read-only memories (EEPROMs), and flash memories.
The term “semiconductor substrate” is defined to mean any construction comprising semiconductor materials, including, but not limited to, bulk semiconductor materials such as a semiconductor wafer (either alone or in integrated assemblies comprising other materials thereon) and semiconductor material layers (either alone or in integrated assemblies comprising other materials). The term “substrate” refers to any supporting substrate, including, but not limited to, the semiconductor substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated. A layer may overlie a portion of, or the entirety of, a substrate.
The term, “features,” as used herein, refers to parts of a pattern, such as lines, spaces, via, pillars, trenches, troughs, or moats. The term, “mandrels,” as used herein, refers to mask features formed at a vertical level. The term, “intervening mask features, as used herein, refers to mask features that are formed between two immediately neighboring mandrels.
The term “array” refers to a regularly repeating pattern of IC elements on a semiconductor substrate. For example, a memory array typically has a number of identical memory cells in a matrix form. Logic arrays may similarly include repeating patterns of conductive lines and/or transistors.
The term, “target layer,” as used herein, refers to a layer in which a pattern of features is formed. A target layer may be part of a semiconductor substrate. A target layer may include metal, semiconductor, and/or insulator.
It will also be appreciated that transferring a pattern from a first (e.g., masking) level to a second level involves forming features in the second level that generally correspond to features on the first level. For example, the path of lines in the second level will generally follow the path of lines on the first level. The location of other features on the second level will correspond to the location of similar features on the first level. The precise shapes and sizes of corresponding features can vary from the first level to the second level, however due, for example, to trim and growth steps. As another example, depending upon etch chemistries and conditions, the sizes of and relative spacings between the features forming the transferred pattern can be enlarged or diminished relative to the pattern on the first level, while still resembling the same initial “pattern.”
While “processing” through masks is described for some embodiments as etching to transfer a hard mask pattern into a target layer, the skilled artisan will appreciate that processing in other embodiments can comprise, e.g., oxidation, nitridation, selective deposition, doping, etc. through the masks.
In some embodiments, methods are provided for forming a masking pattern for an electronic device, such as an integrated circuit. First, mandrels defining a first pattern are formed in a first masking layer provided over a target layer. As nonlimiting examples, the mandrels may be formed of a resist, a hard mask material, or part of a substrate. A second masking layer is deposited in spaces between the mandrels. The second masking layer at least partly fills the spaces between the mandrels. In some embodiments, the second masking layer may bury the first pattern.
Before or after depositing the second masking layer, one or more sacrificial structures are formed to define a second pattern having a smaller pitch than the first pattern. In some embodiments, the one or more sacrificial structures may be formed by altering, e.g., chemically altering, portions of either or both of the mandrels and the second masking layer. In other embodiments, the one or more sacrificial structures may be formed by growing or depositing a layer of a material that is different, or selectively etchable relative to, those of the first and second masking layers before depositing the second masking layer. The resulting intermediate masking structures according to some embodiments are shown in
The sacrificial structures 150 are removed to create gaps between the mandrels 130 and the second masking layer 140. Such sacrificial structures are referred to as “anti-spacers” in the context of this document. The resulting masking structure may include the mandrels 130 and intervening mask features formed of the second masking layer 140 (
In some embodiments, the mandrels in the second pattern have a first pitch between two adjacent mandrels. The intervening mask features in the second pattern have a pitch substantially the same as the first pitch. The mandrels and intervening mask features are both used as masking features for the second pattern. The second pattern has a second pitch defined by the mandrels and an immediately adjacent one of the intervening mask features. The second pitch is about a half of the first pitch. Thus, the foregoing process and features provide pitch doubling, that is, the second pattern has a pitch that is half of the pitch of the first pattern. In other embodiments, the pitch of the second pattern may be further reduced by performing an additional process employing anti-spacers as described herein, or by blanket depositing and etching spacer material to form spacers on sidewalls of the mandrels and intervening mask features.
The methods described herein can be used for forming three dimensional structures in a target layer. The three dimensional structures include, but are not limited to, lines, trenches, vias, posts, pillars, troughs, moats, and two or more of the foregoing. In addition, the methods can form structures having different sizes and shapes, for example, variable width conductive lines and landing pads.
The methods discussed above and described below in the context of certain embodiments allow decreases in pitch and increases in the density of features. In addition, the methods allow forming features having various shapes and sizes with a low number of patterning steps.
With reference again to
UV cure (UVC)
Single layer etch (SLE)
UV bake (UVB)
Multi layer etch (MLE)
Physical vapor deposition
Vacuum bake (VB)
Diffusion limited shrink
Spin-on deposition (SO)
Plating process (PU)
Diffusion limited growth
Wet development (WD)
Thermal freeze (TF)
Plasma freeze (PF)
Dry development (DD)
Plasma shrink (PS)
Vapor freeze (VF)
Plasma etch (PE)
Chemical freeze (CF)
Plasma descum (PD)
Exposure freeze (EF)
Chemical descum (CD)
Plasma growth (PG)
Thermal reflow (TR)
Slim process (SL)
Chemical reflow (CR)
Image reversal (IR)
Atomic layer deposition
Reactive ion etch
Plasma deposition (PD)
Phase change (PC)
Selectivity change (SEC)
The processes and materials of Tables 1 and 2 will be understood by those of skill in the art, particularly in view of the present disclosure. In Table 1, the term “single level etch” refers to a process in which a single layer is provided and etched to form features of a pattern. The term “multi level etch” refers to a process in which multiple layers are provided and etched to form features of a pattern. The term “diffusion limited shrink” refers to a process in which a solubility change in a feature is caused by a coat, thereby allowing a decrease in a dimension of the feature. The term “diffusion limited growth” refers to a process in which a material is chemically attached to a pre-existing feature, e.g., through a reaction or adsorption, thereby increasing the dimension of the feature.
The term “freeze” refers to a surface treatment that protects a pattern by maintaining the integrity of the boundaries of the features forming the pattern; for example, freezing a pattern formed by a photoresist to prevent it from dissolving into an overlying photoresist layer. In some instances, a “freeze” process can be performed to change the chemical solubility of a material that is being “frozen.” After the freeze process, the frozen material no longer exhibits solubility to solvents which would otherwise dissolve the material before the freeze process. For example, a photoresist, after being subjected to a freeze process, would be insoluble to solvents, such as propylene glycol monomethyl ether acetate (PGMEA) or ethyl lactate.
The term “reflow” refers to a process inducing a feature size change, a line increase, and a space decrease, for example, a thermal process that is designed for such a feature size shift to occur. The term “deprotection process” refers to a process in which a feature protected from a chemical reaction or dissolution by a solvent is released and allowed to become reactive or soluble. The term “furnace” refers to a process that includes a thermal bake at a temperature ranging typically, but not limited to, from about 250° C. to about 1000° C. The term “solvent development” refers to a process in which an unconventional solvent-based developer (e.g., a solvent other than tetramethylammonium hydroxide (TMAH)) is used to define a pattern.
The term “descum” refers to a process for removing small portions or residues of a material. The term “slim process” refers to a process that induces a feature size change, namely, a size decrease and a space increase. The term “overcoating” refers to a process of depositing or spinning-on a layer over an existing layer. The term “anti-spacer formation” refers to a process of forming anti-spacers, as described herein. The term “selectivity change” refers to an etch process having the ability to differentiate the etch rate of a target material from the etch rate of a non-target material. The term “plating process” refers to an electrochemical process of depositing a metal on an existing layer(s). The term “shrink” refers to a process for reducing a size of a feature. The term “plasma growth” refers to a process designed to add additional material to an existing feature, with assistance of a plasma operation. The term “vapor treatment” refers to a process in which a gas phase material is used to interact with a substrate. The term “silation process” refers to a process of forming a silane compound. The term “phase change” refers to a process in which a substrate undergoes a phase change during the process. The term “solubility change” refers to a process that changes the solubility of a material in a specific solution.
The mandrels 130, the second masking layer 140, the sacrificial structures 150, and/or partial gap fillers 155 may be formed of various materials. Examples of such materials include, but are not limited to, those listed in Table 2.
Spin on glass (SOG)
silicon oxide (SiO)
Metal-containing hard mask (MHM)
Silicon hard mask (SHM)
Image reversal film (IRF)
Titanium polymer (TP)
(THAM) developer (TD)
Silicon polymer (SP)
Solvent developer (SD)
Deposited ARC - SiOxN
Bottom Antireflective Coating
Specific development chemistry
Spin on overcoat (SOO)
Deposited underlayer (DUL)
Deposited overcoat (DO)
Spin on underlayer (SUL)
Vapor freeze chemistry (VFC)
Reactivity promoter (RP)
Solvent suspensions (PGMEA or other)
In Table 2, the term “specific development chemistry” refers to a chemical or material, such as butyl acetate or other customized solvents for development. The term “underlayer” refers to a layer of material used for a pattern transfer into an underlying layer. The term “reactivity promoter” refers to a chemical agent that promotes the growth of an organic material on a feature. A reactivity promoter may or may not act as a catalyst to a reaction which it promotes. A reactivity promoter may contribute to the attachment of one material to the surface of another material. Thus, it will be appreciated that the various materials of Table 2 may be formed by one or more of the processes of Table 1. Advantageously, the materials can be combined together and possibly with other materials to form masks for defining patterns. This list is for illustrative purposes only, such that the application of the processes noted herein to some embodiments of the invention may be expressed. The list is not intended to be exhaustive, and as such materials and techniques used in the anti-spacer formation are not limited to this list.
For example, in certain embodiments, a method is provided for forming a masking pattern for an electronic device, such as an integrated circuit. First, mandrels defining a first pattern are formed in a first masking layer deposited over a target layer. As nonlimiting examples, the mandrels may be formed of a resist or a hard mask material. A second masking layer is deposited on and over the first masking layer to at least partly bury the first pattern while maintaining the first pattern. The first pattern may be maintained by subjecting the first pattern to a surface treatment using, for example, a so-called freeze technique, prior to depositing the second masking layer.
Portions of the second masking layer proximate to the mandrels are chemically altered such that the portions are more chemically removable (have higher etchability) than unaltered parts of the second masking layer. The chemically altered portions are immediately adjacent the mandrels and have a selected width, and can be referred to as “anti-spacers” in the context of this document. In some embodiments, the chemical alteration can be achieved by a bake that drives an acid- or base-initiated reaction using an acid or base diffused from the mandrels. The anti-spacers may not expand into the mandrels in this embodiment.
In some other embodiments, both portions of the mandrels immediately adjacent to the second masking layer and portions of the second masking layer immediately adjacent to the mandrels may be chemically altered. In such embodiments, the altered portions of both the mandrels and the second masking layer form anti-spacers. In yet other embodiments, portions of the mandrels immediately adjacent to the second masking layer may be chemically altered while substantially no portion of the second masking layer is chemically altered, thereby forming anti-spacers only in the altered portions of the mandrels.
The chemically altered portions are removed, exposing the mandrels. In certain embodiments, an additional step(s) can be performed to remove any material over the chemically altered portions to expose top surfaces of the chemically altered portions before removing the chemically altered portions. The remainder of the second masking layer forms intervening mask features. The mandrels and the intervening mask features together define a second pattern. The second pattern is transferred into the target layer.
Reference will now be made to the Figures, in which like numerals refer to like parts throughout.
The target layer 110 may be a layer in which various IC components, parts, and structures are to be formed through IC fabrication processes. Examples of the components, parts, and structures include transistors, capacitors, resistors, diodes, conductive lines, electrodes, spacers, trenches, etc. The identity of the target layer material depends on the type of device to be formed in the target layer 110. Examples of target layer materials include, but are not limited to, insulators, semiconductors, and metals. The target layer 110 may be formed over a substrate, for example, a semiconductor substrate in certain embodiments. In certain other embodiments, at least a portion of a semiconductor substrate forms the target layer 110.
The hard mask layer 120 is a layer that provides a pattern to be transferred into the target layer 110. As described herein, the hard mask layer 120 is patterned to form an array of features that serve as a mask for the target layer 110, e.g., in an etch step. While illustrated with one hard mask layer, the processes described herein can employ two or more hard mask layers. In certain embodiments, the hard mask layer 120 may be omitted.
In some embodiments, the hard mask layer 120 may be formed of an inorganic material. In the illustrated embodiment, the hard mask layer 120 is formed of a dielectric anti-reflective coating (DARC), for example, silicon-rich silicon oxynitride (SiOxNy). The DARC layer may contain silicon in an amount from about 30 wt % to about 80 wt % with reference to the total weight of the layer. The DARC layer may contain silicon in an amount from 35 wt % to about 70 wt % with reference to the total weight of the layer. In other embodiments, the hard mask layer 120 may be formed of silicon, silicon oxide (SiO2) or silicon nitride (Si3N4). In yet other embodiments, the hard mask layer 120 may be formed of an organic material. For example, the hard mask layer 120 may be formed of amorphous carbon. The skilled artisan will appreciate that various other hard mask materials can be used for the hard mask layer 120. In some embodiments, the hard mask layer 120 may have a thickness of between about 80 nm and about 800 nm, optionally between about 1 μm and about 3 μm.
The first resist layer 230 may be formed of a first resist material. The first resist material is selected based on the type of lithography used for patterning the first resist layer 230. Examples of such lithography include, but are not limited to, ultraviolet (UV) lithography, extreme ultraviolet (EUV) lithography, X-ray lithography and imprint contact lithography. In the illustrated embodiment, the first resist material is a photoresist, such as a positive resist. The skilled artisan will, however, appreciate that the material of the first resist layer 230 may be varied depending on lithography, availability of selective etch chemistries and IC design.
Optionally, a bottom anti-reflective coating (BARC) layer (not shown) may be provided between the first resist layer 230 and the hard mask layer 120. BARCs, which are typically organic, enhance resolution by preventing reflections of the ultraviolet (UV) radiation that activates the photoresist. BARCs are widely available, and are usually selected based upon the selection of the resist material and the UV wavelength. BARCs, which are typically polymer-based, are usually removed along with the overlying photoresist. The optional BARC layer may have a thickness of between about 200 Å and about 600 Å, optionally between about 300 Å and about 500 Å.
After the exposure to the pattern of light, the first resist layer 230 is subjected to development using any suitable developer. Examples of developers include, but are not limited to, sodium hydroxide and tetramethylammonium hydroxide (TMAH). In certain embodiments, rinsing solutions (e.g., propylene glycol monomethyl ether acetate (PGMEA) and/or propylene glycol monomethyl ether (PGME)) can also be used for the development. In certain embodiments, a post-exposure bake (PEB) may be performed after the exposure and before the development. In the illustrated embodiment, the exposed portions 232 of the first resist layer 230 are removed by the development.
The mandrels 234 can be frozen by various freeze techniques. In one embodiment, the mandrels 234 can be frozen by chemical freeze, using a commercially available fluid overcoat. An example of a chemical freeze technique is disclosed by JSR corporation of Tokyo, Japan in their present product line.
In another embodiment, the mandrels 234 can be frozen by a plasma freeze. A plasma freeze can be conducted, using a plasma directed to the mandrels 234. Examples of plasmas include a fluorine-containing plasma generated from, e.g., a fluorocarbon (e.g., CF4, C4F6, and/or C4F8), a hydrofluorocarbon (e.g., CH2F2, and/or CHF3), or NF3. An example plasma freeze technique is disclosed by U.S. patent application Ser. No. 12/201,744, filed Aug. 29, 2008, entitled “METHODS OF FORMING A PHOTORESIST-COMPRISING PATTEN ON A SUBSTRATE” (Inventors: Zhang et al.). In yet another embodiment, the mandrels 234 can be frozen by a thermal freeze. The thermal freeze can be conducted at a temperature between about 110° C. and about 180° C. An example of a thermal freeze technique is disclosed by Tokyo Ohka Kogyo Co., Ltd. of Kawasaki-shi, Kanagawa Prefecture, Japan in their commercially available products.
In some embodiments, the second resist material may include a chemically amplified photoresist. The chemically amplified photoresist may be an acid-catalyzed or base-catalyzed material. Examples of chemically amplified photoresists include, but are not limited to, 193 nm and 248 nm photo resists. Some Mine materials are also chemically amplified.
In certain embodiments, the second resist material may include a bottom anti-reflective coating (BARC) material modified to be suitable for a solubility change by acid or base diffusion. The skilled artisan will appreciate that any material showing a solubility change caused by the acid or base diffusion can be used in place of the second resist material.
The second resist layer 240 may be formed to have a thickness sufficient to cover the top surface 236 of the mandrels 234. Portions 242 of the second resist layer 240 overlying the top surfaces 236 of the mandrels 234 can be referred to as “top coat” in the context of this document. The top coats 242 may have a thickness selected such that all the resulting masking features have substantially the same height after the frozen mandrels 234 and other features that will be formed from portions of the second resist layer 240 are subjected to development. The resulting masking features will form a pattern to be transferred into the underlying target layer 110.
The acid-catalyzed reaction is initiated at or near the top and side surfaces 236, 238 of the mandrels 234 during the bake step. For example, an acid diffused into the mandrels 234 during the step of
In other embodiments where the second resist layer 240 is formed of a base-catalyzed chemically amplified resist, the bake drives a base-catalyzed reaction that may alter the solubility of the second resist layer 240 in a developer. In such an embodiment, a base solution is provided in the step of
In certain embodiments, other portions (not shown) of the second resist layer 240 may be optionally exposed to a pattern of light before or after the bake step. This exposure step can be used to form patterns in the other areas by photolithography, rather than by forming anti-spacers. During this optional exposure step, the structure shown in
This step exposes the pre-existing mandrels 234 while defining intervening mask features 248 formed of the second resist material. The illustrated intervening mask features 248 have a T-shaped top portion, but the skilled artisan will appreciate that the shape of the intervening mask features 248 can vary, depending on the conditions (e.g., temperature, duration, etc.) of the development. The mandrels 234 may have a first height H1 and the intervening mask features 248 may have a second height H2 that is greater than the first height H1.
The mandrels 234 and the intervening mask features 248 together provide a second pattern 260, as shown in
In certain embodiments, an etch stop layer (not pictured) can be used between the hard mask layer 120 and the target layer 110. The etch stop can be made of, for example, DARC or silicon nitride, depending upon the composition of the target layer 110. The etch stop avoids damage to the target layer 110 during the etching of the hard mask layer 120, such as during pattern transfer to the hard mask layer 120 or during removal of the hard mask layer 120. This may be particularly desirable when the target layer 110 is a metal, such as a metallization layer.
When processing (e.g., etching) of the target layer is completed, the hard mask layer 120 and the overlying features 234, 248 may be removed by etch processes, such as a wet etch. Subsequently, additional steps such as metallizations may be conducted to form integrated circuits.
A hard mask layer is formed over the target layer 110. In some embodiments, the hard mask layer may be formed of a silicon-containing organic material. The silicon-containing organic layer may contain silicon in an amount from about 10 wt % to about 35 wt % with reference to the total weight of the layer. An example of a silicon-containing organic materials includes, but is not limited to, SHB-A629 (available from Shin Etsu, Tokyo, Japan). In such an embodiment, the hard mask layer may have a thickness of between about 40 nm and about 800 nm, optionally between about 1 μm and about 3 μm.
The hard mask layer is then patterned to form mandrels 330, as shown in
In certain embodiments, other portions (not shown) of the resist layer 340 may be optionally exposed to a pattern of light before or after the bake step of
The developer can also remove at least part of the top portions of the intervening mask features 345. However, the mandrels 330, which are formed of a hard mask material, may not be eroded by the developer. Thus, after the completion of the development, the mandrels 330 and the intervening mask features 345 may have substantially the same height H3 as each other. As shown in
The mandrels 330 and the intervening mask features 345 together provide a second pattern 360, as shown in
In the illustrated embodiment, trenches or troughs 305 (or through-holes in other embodiments) are formed in the target layer 110. Because the mandrels 330 (formed of a hard mask material) may be etched at a faster rate than the intervening mask features 345 (formed of a photoresist) during the transfer step of
When processing (e.g., etching) of the target layer 110 is completed, the mandrels 330 and the intervening mask features 345 may be removed by known etch processes, such as a wet etch step. Subsequently, additional steps such as metallization may be conducted to complete integrated circuits.
Then, mandrels 430 are formed of a photoresist material on the hard mask layer 120. Details of forming the mandrels 430 can be as described above in connection with
Then, a chemically active species 432, for example, an acid or base solution, is deposited on the structure shown in
Subsequently, the reduced mandrels 430′ covered with the anti-spacers 450 may be subjected to a surface treatment. Surfaces of the anti-spacers 450 are modified such that the integrity of the mandrels is maintained while a second resist layer is formed thereon. The details of the surface treatment can be as described above in connection with
In the illustrated embodiment, the second masking layer 440 may be formed to have a thickness sufficient to cover the top portions 452 of the anti-spacers 450. Portions of the second masking layer 440 overlying the top portions 452 of the anti-spacers 450 may be referred to as “top coats” in the context of this document.
The reduced mandrels 430′ and the intervening mask features 448 together provide a second pattern 460. The second pattern 460 has a second pitch P2 between a reduced mandrel 430′ and a neighboring intervening mask feature 448. The second pitch P2 is about half of the first pitch P1 (
In some other embodiments, mandrels defining a first pattern are formed in a first masking layer provided over a target layer. One or more sacrificial structures may be formed by conformally growing or depositing a layer to cover at least exposed sidewall surfaces of the mandrels. The layer may be formed of a material that is different from that of the first masking layer.
A second masking layer is deposited to fill spaces defined by the mandrels covered with the sacrificial structures. In some embodiments, the second masking layer may cover top surfaces and sidewalls of the mandrels covered with the sacrificial structures. In such embodiments, an additional step(s), e.g., a descum step, can be performed to remove portions of the second masking layer over the sacrificial structures to expose top surfaces of the sacrificial structures. In other embodiments, the second masking layer may have a smaller height than the anti-spacers such that the second masking layer surrounds sidewalls of the anti-spacers while exposing top surfaces of the anti-spacers. The second masking layer may be formed of a material different from the material of the sacrificial structures.
Then, the sacrificial structures are removed, exposing the mandrels. The remaining parts of the second masking layer form intervening masking features. The mandrels and the intervening mask features together define a second pattern. The second pattern is transferred into the target layer.
The mandrels 330 and the intervening mask features 645 together define a second pattern 660. The second pattern 660 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 645. The second pitch P2 is about half of the first pitch P1 in the illustrated embodiment. Other details of this step can be as described above in connection with
The mandrels 330 and the intervening mask features 645 together define a second pattern 660. The second pattern 660 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 645. The second pitch P2 is about half of the first pitch P1 in the illustrated embodiment. Other details of this step can be as described above in connection with
The mandrels 330 and the intervening mask features 845 together define a second pattern 860. The second pattern 860 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 845. The second pitch P2 is about half of the first pitch P1 in the illustrated embodiment. Other details of this step can be as described above in connection with
In some embodiments, a masking pattern formed by the methods described herein may be used for further pitch multiplication. The pitch of the masking pattern may be further reduced by conducting an additional process using anti-spacers. For example, anti-spacers may be formed around the mask features left after anti-spacer removal, e.g., including the mandrels 234 and intervening mask features 248, as shown in
In such embodiments, a second set of anti-spacers are formed around and optionally over the mask features by repeating the steps of
Subsequently, the second set of anti-spacers are removed while leaving at least portions of the third masking layer to form additional intervening mask features. The mandrels, the intervening mask features, and the additional intervening mask features together define a third pattern having a pitch that is about a half of the pitch of the second pattern. The skilled artisan will appreciate that further pitch multiplication is also possible by repeating the process of forming and removing anti-spacers. The steps described above can be repeated if desired for more pitch reduction.
In other embodiments, a masking pattern formed by the methods described above may be used for additional pitch multiplication in combination with a process employing so-called spacers.
A first pattern 920 is formed on the target layer 110. The first pattern 920 may include mandrels 922 and intervening mask features 924. In the context of this embodiment, the mandrels 922 and the intervening mask features 924 may be collectively referred to as “first masking features.” The mandrels 922 and the intervening mask features 924 can be formed by the method described above in connection with
As shown in
Next, as shown in
The spacer material can be any material capable of use as a mask to transfer a pattern to the underlying target layer 110. The spacer material preferably: 1) can be deposited with good step coverage, 2) can be deposited at a temperature compatible with the target layer 110 and 3) can be selectively etched relative to the target layer 110. In one embodiment, the spacer material 930 is silicon oxide. In other non-limiting embodiments, the spacer material may be polysilicon or a low temperature oxide (LTO).
The spacer material may be deposited by any suitable method, including, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), spin-coating, or casting. ALD may have the advantages of both low temperature deposition and high conformality. The thickness of the layer 930 corresponds to the width of the spacers 935 and may be determined based upon the desired width of those spacers 935 (
In certain embodiments, the spacer material may be one of a class of materials available from Clariant International, Ltd. (so-called “AZ R” materials), such as the materials designated as AZ R200™, AZ R500™, and AZ R600™. In other embodiments, the spacer material may be an “AZ R” material with one or more inorganic components (e.g., one or more of titanium, carbon, fluorine, bromine, silicon, and germanium) dispersed therein. The “AZ R” materials contain organic compositions which cross-link upon exposure to acid released from chemically-amplified resist. Specifically, an “AZ R” material may be coated across photoresist, and subsequently the resist may be baked at a temperature of about 100° C. to about 120° C. to diffuse acid from the resist and into the “AZ R” material to form chemical cross-links within regions of the material proximate the resist. Portions of the material adjacent the resist are thus selectively hardened relative to other portions of material in which acids have not diffused. The material may then be exposed to conditions which selectively remove the non-hardened portions relative to the hardened portions. Such removal may be accomplished using, for example, 10% isopropyl alcohol in the ionized water, or a solution marketed as “SOLUTION C™” by Clariant International, Ltd. The processes using the “AZ R” materials are sometimes considered examples of RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) processes. Examples of spacers formed by RELACS processes are disclosed by U.S. patent application Ser. No. 12/125,725, filed May 22, 2008, entitled “METHODS OF FORMING STRUCTURES SUPPORTED BY SEMICONDUCTOR SUBSTRATES” (inventor: Anton deVilliers).
In the illustrated embodiment, the spacers 935 form a second pattern 950 having a third pitch P3. The third pitch P3 is roughly half of the second pitch P2 between neighboring first masking features 922, 924 in the first pattern 920. For example, where the first pitch P1 is about 200 nm, spacers 935 having a pitch of about 50 nm or less can be formed.
Next, the second pattern 950 provided by the spacers 935 is transferred into the target layer 110 (not shown). The pattern transfer can be performed using any suitable etch process selective for the target layer 110 relative to the spacers 935. Other details of this step can be as described above with reference to
In some embodiments, three dimensional structures can be formed by the methods described above. The three dimensional structures can include, but are not limited to, lines, trenches, vias, pillars, posts, troughs, and moats.
Subsequently, the structure shown in
Subsequently, the structure shown in
In certain embodiments, the holes 1005 can be filled with a material (e.g., a dielectric material, a conductive material, or a semiconductor) such that structures formed in the holes 1005 can serve as posts or pillars in a resulting electronic circuit. In other embodiments, the method described above may be adapted for forming isolated holes, e.g., contact vias or trenches, depending on the design of the electronic circuit.
In other embodiments, the mandrels 1020 and the intervening mask features 1048 extending in the y-direction can be formed by any of the methods described above in connection with
In other embodiments, the mandrels 1320 and the intervening mask features 1348 extending in the y-direction can be formed by any of the methods described above in connection with
Electronic devices, such as IC devices, typically include a plurality of conductive lines (for example, interconnects) and landing contact pads that electrically connect the conductive lines to other levels in the IC. The “landing contact pads” may also be referred to as “landing pads” or “contact tabs.” The conductive lines typically have a width narrower than the widths of the landing pads. A conventional pitch multiplication process using spacers allows formation of conductive lines having a narrower line-width than that allowed by an available photolithographic process. However, because a masking pattern defined by such spacers can only provide features having such a narrow line-width, it can be difficult to form larger width landing pads using spacers.
In some embodiments, a process involving anti-spacers may be used to simultaneously form conductive lines and landing pads integrated with the conductive lines. Such a process can provide a single masking pattern for forming pitch-multiplied conductive lines as well as landing pads wider than the conductive lines.
In the illustrated embodiment, the line mask features 1622 of the mandrels 1620 extend parallel to one another. In other embodiments, the configurations of the line mask features 1622 of the mandrels 1620 can vary, depending on the design of the electronic device formed by the method. The second width LW2 can be selected, depending on the size of a landing pad to be formed in the target layer 110, and is greater than the first width LW1.
In one embodiment, the second width LW2 is about 0.5 to about 5 times greater than the first width LW1. The illustrated landing pad mask feature 1624 has a substantially circular shape, but the skilled artisan will appreciate the landing pad mask feature 1624 can have various other shapes such as a square shape, a rectangular shape, an oval shape, or the like, depending on the desired shape of the landing pad. The mandrels 1620 can be formed as described above in connection with
In other embodiments, the mandrels 1620 and the intervening mask features 1630 can be formed by any of the methods described above in connection with
The mask 1650 is removed and the resulting features 1620, 1630 after the etch process are shown in
In another embodiment, a pattern formed by the features 1620, 1630 shown in
In the embodiments described above, the landing pads can be formed simultaneously with conductive lines, thus eliminating separate steps for defining and connecting the landing pads to conductive lines. Yet, the pitch of the conductive lines can be reduced at least to the same extent as in a conventional pitch multiplication process using spacers. While the embodiments above were described in connection with forming conductive lines and landing pads, the skilled artisan will appreciate that the embodiments can be adapted for forming various other structures or parts of electronic devices where different shapes or sizes of features are formed simultaneously.
In some embodiments, electronic devices, such as arrays in IC's, can be made by the methods described above. The electronic devices may also include a system including a microprocessor and/or a memory device, each of which includes features arranged in an array. Such a system may be a computer system, an electronic system, or an electromechanical system.
Examples of electronic devices include, but are not limited to, consumer electronic products, electronic circuits, electronic circuit components, parts of the consumer electronic products, electronic test equipments, etc. The consumer electronic products may include, but are not limited to, a mobile phone, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi functional peripheral device, a wrist watch, a clock, etc. Further, the electronic device may include unfinished intermediate products.
Thus, it will be understood that the invention can take the form of various embodiments, some of which are discussed above and below.
In one embodiment, a method of forming features in an electronic device includes forming mandrels defining a first pattern in a first masking layer on one or more underlying layers comprising a target layer. The first pattern includes spaces between the mandrels, and has a first pitch. The method also includes depositing a second masking layer to at least partly fill the spaces of the first pattern. The second masking layer contacts the one or more underlying layers through the spaces between the mandrels. The method further includes forming sacrificial structures to define gaps between at least parts of the mandrels and at least parts of the second masking layer; and after depositing the second masking layer and forming the sacrificial structures, removing the sacrificial structures to define a second pattern having a second pitch smaller than the first pitch. The second pattern includes the at least parts of the mandrels and intervening mask features alternating with the at least parts of the mandrels.
In another embodiment, a method of forming features in an electronic device includes photolithographically forming mandrels defining a first pattern in a first masking layer over a target layer. The first pattern includes spaces between the mandrels, and has a first pitch. The method also includes depositing a second masking layer to at least partially fill the spaces of the first pattern; forming sacrificial structures to define gaps between at least parts of the mandrels and at least parts of the second masking layer; and after depositing the second masking layer and forming the sacrificial structures, removing the sacrificial structures to define a second pattern having a second pitch smaller than the first pitch. The second pattern includes the at least parts of the mandrels and intervening mask features alternating with the at least parts of the mandrels.
In yet another embodiment, a method of forming an integrated circuit includes forming a first pattern comprising first lines extending substantially parallel to one another in a first direction over a target layer. Forming the first pattern includes: providing first mandrels in a first masking layer over the target layer, the first mandrels having spaces therebetween; depositing a second masking layer to at least partially fill the spaces between the first mandrels; and forming first sacrificial structures to define gaps between at least parts of the first mandrels and at least parts of the second masking layer. The method also includes forming a second pattern comprising second lines extending substantially parallel to one another in a second direction over the first pattern, the second direction being different from the first direction. Forming the second pattern includes: providing second mandrels in a third masking layer over the second masking layer, the second mandrels having spaces therebetween; depositing a fourth masking layer to at least partially fill the spaces between the second mandrels; and forming second sacrificial structures to define gaps between at least parts of the second mandrels and at least parts of the fourth masking layer. The method further includes: removing the first sacrificial structures; removing the second sacrificial structures; and etching the target layer through the first pattern, the second pattern, or a combination of the first and second patterns.
Although this invention has been described in terms of certain preferred embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Accordingly, the scope of the present invention is defined only by reference to the appended claims.
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|Classification aux États-Unis||438/694, 438/689|
|Classification internationale||H01L21/3213, H01L21/311, H01L21/768, H01L21/033, H01L21/308, H01L21/027, H01L27/105, H01L27/10|
|Classification coopérative||H01L27/1052, H01L21/76816, H01L27/10, H01L21/0273, H01L21/31144, H01L21/3088, H01L21/3086, H01L21/0338, H01L21/0337, H01L21/32139|
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