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Numéro de publicationUS9082880 B2
Type de publicationOctroi
Numéro de demandeUS 13/410,610
Date de publication14 juil. 2015
Date de dépôt2 mars 2012
Date de priorité10 mars 2011
Numéro de publication13410610, 410610, US 9082880 B2, US 9082880B2, US-B2-9082880, US9082880 B2, US9082880B2
InventeursDaisuke Matsubayashi
Cessionnaire d'origineSemiconductor Energy Laboratory Co., Ltd.
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes: USPTO, Cession USPTO, Espacenet
Memory device and method for manufacturing the same
US 9082880 B2
Résumé
A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor.
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Revendications(27)
What is claimed is:
1. A memory device comprising:
an insulating surface;
a transistor over the insulating surface, the transistor comprising a bit line, a semiconductor layer, a gate insulating layer, and a word line, the gate insulating layer being interposed between a side face of the semiconductor layer and the word line; and
a capacitor overlapping the transistor, the capacitor comprising an insulating layer interposed between a capacitor electrode and a capacitor line, the capacitor electrode being in electrical contact with the semiconductor layer,
wherein a top surface of the semiconductor layer, a top surface of the gate insulating layer, and a top surface of the word line are in a same horizontal plane,
wherein the bit line, the semiconductor layer, the capacitor electrode, the insulating layer, and the capacitor line are stacked in this order, and
wherein the semiconductor layer comprises a semiconductor material having a wider band gap than silicon.
2. The memory device according to claim 1,
wherein the semiconductor layer comprises a material having a band gap greater than or equal to 2.5 eV and less than or equal to 4 eV.
3. The memory device according to claim 1,
wherein the semiconductor layer has been formed by deposition of a thin film semiconductor material.
4. The memory device according to claim 1,
wherein the semiconductor layer comprises an oxide semiconductor.
5. The memory device according to claim 1,
wherein the semiconductor layer comprises a c-axis aligned crystalline oxide semiconductor.
6. The memory device according to claim 1, further comprising a driver circuit formed over a semiconductor substrate,
wherein the transistor and the capacitor are formed over the driver circuit and are functionally connected to the driver circuit.
7. The memory device according to claim 1, further comprising a driver circuit formed over a semiconductor substrate,
wherein the driver circuit is electrically connected to the bit line through a contact plug, and
wherein the transistor and the capacitor are formed over the driver circuit.
8. The memory device according to claim 1,
wherein the semiconductor layer is prism-shaped or cylinder-shaped, and
wherein the word line faces all of side faces or the whole side face of the semiconductor layer.
9. The memory device according to claim 1,
wherein the transistor and the capacitor are included in a memory cell and,
wherein, in the memory cell, a distance separating a lowest part of the capacitor from a highest part of the capacitor is smaller than a width of the memory cell.
10. The memory device according to claim 1,
wherein the bit line is a metal layer overlapping with the semiconductor layer.
11. The memory device according to claim 1,
wherein the top surface of the gate insulating layer and the top surface of the word line are formed by a planarization step stopped when the top surface of the gate insulating layer and the top surface of the word line are in the same horizontal plane as the top surface of the semiconductor layer.
12. A semiconductor device comprising:
an insulating surface;
a first conductive layer formed over the insulating surface;
a semiconductor layer formed over and in electrical contact with the first conductive layer;
a second conductive layer formed over and in electrical contact with the semiconductor layer;
an insulating layer formed over the second conductive layer;
a third conductive layer formed over the insulating layer and overlapping the second conductive layer and the semiconductor layer;
a fourth conductive layer facing a side face of the semiconductor layer; and
a gate insulating layer interposed between the fourth conductive layer and the semiconductor layer,
wherein a top surface of the semiconductor layer, a top surface of the gate insulating layer, and a top surface of the fourth conductive layer are in a same horizontal plane, and
wherein the semiconductor layer comprises a semiconductor material having a wider band gap than silicon.
13. The semiconductor device according to claim 12,
wherein the first conductive layer, the second conductive layer, and the fourth conductive layer form respectively a source, a drain, and a gate of a transistor including the semiconductor layer as a channel-formation layer; and
wherein the second conductive layer and the third conductive layer form two facing electrodes of a capacitor.
14. The semiconductor device according to claim 12,
wherein the semiconductor layer comprises a material having a band gap greater than or equal to 2.5 eV and less than or equal to 4 eV.
15. The semiconductor device according to claim 12,
wherein the semiconductor layer has been formed by deposition of a thin film semiconductor material.
16. The semiconductor device according to claim 12,
wherein the semiconductor layer comprises an oxide semiconductor.
17. The semiconductor device according to claim 12,
wherein the semiconductor layer comprises a c-axis aligned crystalline oxide semiconductor.
18. The semiconductor device according to claim 12, further comprising a driver circuit formed over a semiconductor substrate,
wherein the first conductive layer and the second conductive layer are formed over the driver circuit and are functionally connected to the driver circuit.
19. The semiconductor device according to claim 12, further comprising a driver circuit formed over a semiconductor substrate,
wherein the driver circuit is electrically connected to the first conductive layer through a contact plug, and
wherein the first conductive layer and the second conductive layer are formed over the driver circuit.
20. The semiconductor device according to claim 12,
wherein the semiconductor layer is prism-shaped or cylinder-shaped, and
wherein the fourth conductive layer faces all of side faces or the whole side face of the semiconductor layer.
21. The semiconductor device according to claim 12,
wherein the second conductive layer and the third conductive layer are at least partly included in a memory cell and,
wherein, in the memory cell, a distance separating a lowest bottom surface of the second conductive layer from a highest top surface of the third conductive layer is smaller than a width of the memory cell.
22. The semiconductor device according to claim 12,
wherein the semiconductor device is a memory device.
23. The semiconductor device according to claim 12,
wherein the first conductive layer is a metal layer overlapping with the semiconductor layer.
24. The semiconductor device according to claim 12,
wherein the top surface of the gate insulating layer and the top surface of the fourth conductive layer are formed by a planarization step stopped when the top surface of the gate insulating layer and the top surface of the fourth conductive layer are in the same horizontal plane as the top surface of the semiconductor layer.
25. A memory device comprising:
an insulating surface;
a first transistor over the insulating surface, the first transistor comprising a first bit line, a first semiconductor layer over the first bit line, a first capacitor electrode, and a first gate insulating layer, the first semiconductor layer being interposed between and in electrical contact with the first bit line and the first capacitor electrode;
a second transistor over the insulating surface, the second transistor comprising a second bit line, a second semiconductor layer over the second bit line, a second capacitor electrode, and a second gate insulating layer, the second semiconductor layer being interposed between and in electrical contact with the second bit line and the second capacitor electrode;
a word line facing a side surface of the first semiconductor layer and a side surface of the second semiconductor layer with the first gate insulating layer and the second gate insulating layer interposed between the word line and, respectively, the first semiconductor layer and the second semiconductor layer;
an insulating layer covering the first and the second capacitor electrodes;
a capacitor line over the insulating layer;
a capacitor comprising the first capacitor electrode, the insulating layer, and the capacitor line,
wherein the word line fills a space separating the first and the second semiconductor layers, except for a volume occupied by the first and the second gate insulating layers, and
wherein the first and the second semiconductor layers each comprise a semiconductor material having a wider band gap than silicon.
26. The memory device according to claim 25,
wherein the first bit line is a metal layer overlapping with the first semiconductor layer.
27. The memory device according to claim 25,
wherein the word line completely fills the space separating the first and the second semiconductor layers, except for the volume occupied by the first and the second gate insulating layers.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory device utilizing semiconductor properties and a method for manufacturing the memory device.

2. Description of the Related Art

A typical example of a widely used memory device is dynamic random access memory (DRAM), which is composed of one capacitor and one transistor (also referred to as cell transistor).

A planar transistor has been conventionally used to form a DRAM. More recently, a method using a recessed channel array transistor (RCAT) in which a gate is arranged three-dimensionally so as to prevent leakage current due to a short-channel effect is employed because of miniaturization of circuits (see Non-Patent Document 1).

REFERENCE

Non-Patent Document 1: K. Kim, “Technology for sub-50 nm DRAM and NAND flash manufacturing”, Technical Digest of International Electron Devices Meeting, pp. 333-336,2005.

SUMMARY OF THE INVENTION

In conventional DRAM, electric charge in a capacitor is lost when data is read out; thus, another write operation is necessary every time data is read out. Moreover, a transistor included in a storage element has a leakage current and electric charge flows into or out of a capacitor even when the transistor is not selected, so that a data retention period is short. For that reason, another write operation (refresh operation) is necessary at predetermined intervals.

In addition, the reduction in the area of memory elements is required along with higher integration of memory devices. However, it is difficult for the above-described planar transistor and RCAT, its variation, to further increase the degree of integration except by a reduction in the circuit line width. The area of a memory element utilizing such a conventional technique is 8 F2 or more (F: minimum feature size) or 6 F2 or more. A technique to achieve a much smaller area, for example, 4 F2 is therefore expected.

The present invention is made in view of the foregoing technical background. An object of one embodiment of the present invention is therefore to provide a memory device that is as small in area as possible and has an extremely long data retention period.

In order to achieve the above object, the present invention focuses on the use of a transistor with extremely low leakage current as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor.

That is, one embodiment of the present invention is a memory device in which a cell transistor and a capacitor are stacked over a substrate. The cell transistor includes a semiconductor layer over a bit line, and a gate insulating layer in contact with a side surface of the semiconductor layer. At least part of the side surface of the semiconductor layer is covered with a word line with the gate insulating layer placed between the part of the side surface of the semiconductor layer and the word line. The capacitor includes a capacitor electrode in contact with a top surface of the semiconductor layer, an insulating layer over the capacitor electrode, and a capacitor wiring over the insulating layer. The semiconductor layer in the cell transistor is formed using a semiconductor material having a wider band gap than silicon.

In the above manner, the cell transistor is formed in a region where the bit line and the word line intersect each other and the capacitor is formed to overlap with the cell transistor; therefore, the area of a memory element occupying the substrate can be extremely small. Further, in the cell transistor, a semiconductor material whose band gap is wider than that of silicon is used for the semiconductor layer in which a channel is formed, whereby the off-state current of the cell transistor is reduced and a data retention period can be extremely long.

According to another embodiment of the present invention, the semiconductor layer in the above memory device is formed using a material having a band gap greater than or equal to 2.5 eV and less than or equal to 4 eV.

According to another embodiment of the present invention, the semiconductor layer in the above memory device is formed using an oxide semiconductor.

The off-state current of the cell transistor can be extremely low particularly when a semiconductor having a band gap in the above range is used for the semiconductor layer in which a channel in the cell transistor is formed.

According to another embodiment of the present invention, the memory device further includes a driver circuit configured to drive the cell transistor and placed below the bit line.

By providing the driver circuit below the bit line as described above, the area occupied by the memory element can be reduced. The driver circuit is preferably formed using a single crystal semiconductor.

One embodiment of the present invention is a method for manufacturing a memory device including the following steps: forming a bit line on an insulating surface; forming a semiconductor layer over the bit line by using a semiconductor material having a wider band gap than silicon; forming a gate insulating layer covering the bit line and the semiconductor layer; forming a word line covering at least part of a side surface of the semiconductor layer with the gate insulating layer placed between the part of the side surface of the semiconductor layer and the word line; removing part of the gate insulating layer so as to expose a top surface of the semiconductor layer; forming a capacitor electrode in contact with the top surface of the semiconductor layer; and forming an insulating layer and a capacitor wiring to be stacked over the capacitor electrode.

According to the above-described method for manufacture, it is possible to fabricate a memory element that is very small in area and has an extremely long data retention period.

In this specification and the like, a bit line may be considered as a wiring connected to a sense amplifier or the like or as a wiring whose potential is amplified by a sense amplifier or the like. A word line may be considered as a wiring connected to a gate of a cell transistor.

The present invention can provide a semiconductor memory device that is as small in area as possible and has an extremely long data retention period.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B illustrate a memory device according to one embodiment of the present invention;

FIGS. 2A to 2C illustrate a method for manufacturing a memory device according to one embodiment of the present invention;

FIGS. 3A and 3B illustrate a method for manufacturing a memory device according to one embodiment of the present invention;

FIG. 4 illustrates a memory device according to one embodiment of the present invention;

FIG. 5 illustrates a memory device according to one embodiment of the present invention;

FIG. 6 illustrates a memory device according to one embodiment of the present invention;

FIGS. 7A to 7E are examples of oxide semiconductors;

FIGS. 8A to 8C are examples of oxide semiconductors;

FIGS. 9A to 9C are examples of oxide semiconductors;

FIG. 10 illustrates a relation between gate voltage and field-effect mobility;

FIGS. 11A to 11C each illustrate a relation between gate voltage and drain current;

FIGS. 12A to 12C each illustrate a relation between gate voltage and drain current;

FIGS. 13A to 13C each illustrate a relation between gate voltage and drain current;

FIGS. 14A to 14C each illustrate characteristics of a transistor;

FIGS. 15A and 15B each illustrate characteristics of a transistor;

FIGS. 16A and 16B each illustrate characteristics of a transistor; and

FIG. 17 illustrates temperature dependence of off-state current of a transistor.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated.

Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, the scale is not necessarily limited to that illustrated in the drawings.

In this specification, a source of a cell transistor refers to an electrode or a region on the bit line side, and a drain of a cell transistor refers to an electrode or a region on the capacitor side.

(Embodiment 1)

In this embodiment, an example of the structure of a semiconductor memory device which is one embodiment of the present invention will be described with reference to FIGS. 1A and 1B and FIG. 6.

FIG. 1A is a schematic top view of a memory device 100. FIG. 1B is a schematic cross-sectional view along line A-A′ in FIG. 1A. Note that a capacitor line 119 is not explicitly illustrated in FIG. 1A for clarity.

The memory device 100 includes a plurality of bit lines 103 arranged in parallel to each other and a plurality of word lines 105 perpendicular to the bit lines 103. A cell transistor 150 and a capacitor 160 are stacked in a region where the bit line 103 and the word line 105 overlap with each other.

The cell transistor 150 is formed over a base insulating layer 113 that covers a surface of a substrate 101. In the cell transistor 150, a semiconductor layer 109 and a capacitor electrode 107 are stacked over the bit line 103. Side surfaces of the semiconductor layer 109 are covered with the word line 105 with a gate insulating layer 111 placed therebetween. The cell transistor 150 is thus a vertical transistor in which the word line 105 that covers the side surfaces of the semiconductor layer 109 functions as a gate, the bit line 103 in contact with a bottom surface of the semiconductor layer 109 functions as a source, and the capacitor electrode 107 in contact with a top surface of the semiconductor layer 109 functions as a drain.

FIG. 6 is a schematic cross-sectional view along line B-B′, which is cut along the bit line 103 in FIG. 1A. As illustrated in FIG. 6, the word line 105 is formed without being interrupted so as to cover the side surfaces of the semiconductor layer 109 with the gate insulating layer 111 placed therebetween, so that the same potential can be applied to a plurality of cell transistors 150 that are connected to one word line 105 and arranged in one column. Adjacent word lines 105 are insulated from each other by an insulating layer.

The capacitor 160 is stacked above the cell transistor 150 and composed of the capacitor electrode 107, the capacitor line 119, and an insulating layer 117 interposed between the capacitor electrode 107 and the capacitor line 119.

In order to write data, electric charge is held in the capacitor 160 in the following manner: the cell transistor 150 is turned on, and a current corresponding to a difference in potential between the bit line 103 and the capacitor line 119 flows to the capacitor electrode 107 through a channel formed in the semiconductor layer 109. Then, the cell transistor 150 is turned off, whereby written data can be held.

When data is to be read out, the cell transistor 150 is turned on, so that a current corresponding to the electric charge held in the capacitor 160 flows to the bit line 103 through the channel formed in the semiconductor layer 109. Accordingly, a change in the potential of the bit line 103 at that time is detected by a readout circuit, such as a sense amplifier, connected to the bit line 103; thus, the data can be detected.

The widths of the cell transistor 150 and the capacitor 160 in the word line 105 direction can be substantially the same as the width of the bit line 103. The widths of the cell transistor 150 and the capacitor 160 in the bit line 103 direction can be substantially the same as the width of the word line 105. Consequently, the area of a surface of the substrate 101 occupied by the cell transistor 150 and the capacitor 160 can be extremely small.

The channel length of the cell transistor 150 can be controlled by a change in the thickness of the semiconductor layer 109. For that reason, the cell transistor 150 can have a given channel length even when the widths of the bit line 103, the word line 105, and the like are extremely small because of miniaturization, so that a short-channel effect can be reduced.

Although depending on the thickness of the gate insulating layer 111, the channel length of the cell transistor 150 is preferably, for example, 10 or more times, further preferably 20 or more times the length of the diagonal or the diameter of the semiconductor layer 109, in which case a short-channel effect can be reduced.

Note that FIGS. 1A and 1B and FIG. 6 show that the semiconductor layer 109 is prism-shaped; alternatively, the semiconductor layer 109 may be cylinder-shaped. For example, when the semiconductor layer 109 is prism-shaped, the effective width of the channel formed near the side surfaces of the semiconductor layer 109 can be large, so that the on-state current of the cell transistor 150 can be increased. In contrast, when the semiconductor layer 109 is cylinder-shaped, its side surface has no protrusion and thus a gate electric field is evenly applied to the side surface; consequently, the cell transistor 150 can have high reliability. In order to further increase the on-state current, the shape of the bottom surface of the semiconductor layer 109 may be, for example, a polygon that contains at least one interior angle larger than 180° (a concave polygon), such as a star polygon.

Although FIGS. 1A and 1B and FIG. 6 illustrate that the word line 105 covers the side surfaces of the semiconductor layer 109 with the gate insulating layer 111 placed therebetween, the word line 105 needs to be provided to cover at least part of the side surfaces of the semiconductor layer 109. For example, when the word line 105 is provided only on one of the side surfaces of the semiconductor layer 109 along the word line 105, the degree of integration in the bit line 103 direction can be increased. On the other hand, when the word line 105 covers the side surfaces of the semiconductor layer 109 as illustrated in FIGS. 1A and 1B and FIG. 6, the effective channel width of the cell transistor 150 can be large and the on-state current can be increased as a result.

Here, the use of a transistor with extremely low off-state current as the cell transistor 150 makes it possible for the capacitor 160 to retain electric charges for a long time. Thus, in the memory device 100, a data rewrite operation (refresh operation) at regular intervals is unnecessary or the frequency of refresh operations can be extremely low; consequently, the memory device 100 can substantially function as a non-volatile memory device.

An example of a transistor with extremely low off-state current is a transistor in which a semiconductor having a wider band gap than silicon is used for a semiconductor layer where a channel is formed. An example of the semiconductor having a wider band gap than silicon is a compound semiconductor, such as an oxide semiconductor and a nitride semiconductor.

Specifically, the band gap of silicon (1.1 eV) is not high enough to give very high off-resistance. It is necessary to use a wide band gap semiconductor with a band gap ranging from 2.5 eV to 4 eV, preferably from 3 eV to 3.8 eV. For example, an oxide semiconductor such as indium oxide or zinc oxide, a nitride semiconductor such as gallium nitride, a sulfide semiconductor such as zinc sulfide, or the like may be used.

For example, a transistor in which an oxide semiconductor layer is used for the semiconductor layer 109 where the channel is formed can be used as the cell transistor 150.

Since the cell transistor 150 is a transistor with extremely low off-state current, the size of the capacitor 160 for holding electric charge can be reduced. Further, the time needed for data writing and reading can be reduced with the reduction in the size of the capacitor 160, so that the memory device 100 can operate at high speed.

As described above, the memory device 100 exemplified in this embodiment is a memory device including a memory element which is composed of the cell transistor 150 and the capacitor 160 and occupies a very small area on the surface of the substrate 101. In addition, the use of a transistor with extremely low off-state current as the cell transistor 150 makes it possible for the memory device 100 to have an extremely long data retention period.

This embodiment can be combined with any of the other embodiments disclosed in this specification as appropriate.

(Embodiment 2)

In this embodiment, a method for manufacturing the memory device 100 exemplified in Embodiment 1 will be described with reference to FIGS. 2A to 2C and FIGS. 3A and 3B.

In this embodiment, with a few exceptions, just an outline is described. A known technique for manufacturing a semiconductor integrated circuit can be referred to for the details.

First, a base insulating layer 113 is formed over a substrate 101.

Although there is no particular limitation on a material that can be used as the substrate 101, the material needs to have at least heat resistance high enough to withstand heat treatment to be performed later. For example, the substrate 101 can be a glass substrate formed by a fusion process or a float process, a quartz substrate, a semiconductor substrate, a ceramic substrate, or the like. In the case where a glass substrate is used and the temperature of the heat treatment to be performed later is high, a glass substrate whose strain point is 730° C. or higher is preferably used.

The base insulating layer 113 has a function of inhibiting diffusion of impurities from the substrate 101. For example, an oxide insulating film, a nitride insulating film, or the like may be formed by a deposition method such as CVD or sputtering. When a semiconductor substrate is used as the substrate 101, the base insulating layer 113 may be formed by thermal oxidation of a surface of the substrate. The base insulating layer 113 does not have to be formed if not needed.

Then, a bit line 103 is formed over the base insulating layer 113. The bit line 103 is formed in such a manner that a conductive film is formed by a deposition method such as sputtering or CVD and processed by a known photolithography method.

Examples of a material used for the conductive film are an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, and the like; an alloy containing any of these elements as a component; and an alloy containing any of these elements in combination. The conductive film may have a single-layer structure or a stacked structure of two or more layers. Specifically, a film of refractory metal such as chromium, tantalum, titanium, molybdenum, or tungsten may be stacked on one or both of the bottom and top sides of a metal film of aluminum, copper, or the like. Further, one or more materials selected from manganese, magnesium, zirconium, beryllium, neodymium, and scandium may be used.

Then, a semiconductor film 129 is formed so as to cover the base insulating layer 113 and the bit line 103. Here, the semiconductor film 129 is preferably formed so that its thickness can be greater than the channel length of the cell transistor in advance in consideration of the fact that the thickness of the semiconductor film 129 over the bit line 103 is reduced in a later planarization step. In this embodiment, as the semiconductor film 129, an oxide semiconductor film is formed by sputtering, specifically, by sputtering with the use of an In—Ga—Zn-based oxide semiconductor target.

Note that the material used for the oxide semiconductor film is not limited to the above. An oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In particular, an oxide semiconductor preferably contains In and Zn.

As a stabilizer for reducing variation in electric characteristics of transistors containing an oxide semiconductor, one or more selected from gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and lanthanoid is/are preferably contained.

As lanthanoid, there are lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

Examples of an oxide semiconductor containing one kind of metal are indium oxide, tin oxide, and zinc oxide.

Examples of an oxide semiconductor containing two kinds of metal are In—Zn-based oxide, Sn—Zn-based oxide, Al—Zn-based oxide, Zn—Mg-based oxide, Sn—Mg-based oxide, In—Mg-based oxide, and In—Ga-based oxide.

Examples of an oxide semiconductor containing three kinds of metal are In—Ga—Zn-based oxide (also referred to as IGZO), In—Sn—Zn-based oxide, Sn—Ga—Zn-based oxide, In—Al—Zn-based oxide, In—Hf—Zn-based oxide, In—La—Zn-based oxide, In—Ce—Zn-based oxide, In—Pr—Zn-based oxide, In—Nd—Zn-based oxide, In—Sm—Zn-based oxide, In—Eu—Zn-based oxide, In—Gd—Zn-based oxide, In—Tb—Zn-based oxide, In—Dy—Zn-based oxide, In—Ho—Zn-based oxide, In—Er—Zn-based oxide, In—Tm—Zn-based oxide, In—Yb—Zn-based oxide, In—Lu—Zn-based oxide, Al—Ga—Zn-based oxide, and Sn—Al—Zn-based oxide.

Examples of an oxide semiconductor containing four kinds of metal are In—Sn—Ga—Zn-based oxide, In—Hf—Ga—Zn-based oxide, In—Al—Ga—Zn-based oxide, In—Sn—Al—Zn-based oxide, In—Sn—Hf—Zn-based oxide, and In—Hf—Al—Zn-based oxide.

Note that here, for example, an In—Ga—Zn-based oxide refers to an oxide containing In, Ga, and Zn as its main components, and there is no particular limitation on the ratio of In, Ga, and Zn. The In—Ga—Zn-based oxide may contain a metal element other than In, Ga, and Zn.

Alternatively, the oxide semiconductor film can be formed using an oxide semiconductor obtained by adding SiO2 to any of the above metal oxides.

Alternatively, the oxide semiconductor film can be formed using an oxide semiconductor represented by the chemical formula InMO3(ZnO)m (m>0). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co.

For example, it is possible to use an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1 or In:Ga:Zn=2:2:1, or an oxide with an atomic ratio close to the above atomic ratios.

Alternatively, an In—Sn—Zn-based oxide with an atomic ratio of In:Sn:Zn=1:1:1, In:Sn:Zn=2:1:3, or In:Sn:Zn=2:1:5, or an oxide with an atomic ratio close to the above atomic ratios may be used.

Without limitation to the materials given above, a material with an appropriate composition can be used in accordance with needed semiconductor characteristics (e.g., mobility, threshold voltage, and variation). In order to obtain the needed semiconductor characteristics, it is preferable that the carrier density, impurity concentration, defect density, atomic ratio of a metal element to oxygen, interatomic distance, density, and the like be set to appropriate values.

For example, high mobility can be obtained relatively easily in the case of using an In—Sn—Zn-based oxide. However, even with an In—Ga—Zn-based oxide, the mobility can be increased by a reduction in bulk defect density.

Note that the expression “the composition of an oxide with an atomic ratio of In:Ga:Zn=a:b:c (a+b+c=1) is close to the composition of an oxide with an atomic ratio of In:Ga:Zn=A:B:C (A+B+C=1)” means that a, b, and c satisfy the following relation: (a−A)2+(b−B)2+(c−C)2≦r2, where r is 0.05, for example. The same applies to other oxides.

The oxide semiconductor may be either single crystal or non-single-crystal.

A non-single-crystal oxide semiconductor may be either amorphous or polycrystalline. Further, the oxide semiconductor may have a structure including a crystalline portion in an amorphous portion. Since the amorphous structure has many defects, a non-amorphous structure is preferred.

An oxide semiconductor in an amorphous state can have a flat surface with relative ease. Consequently, when a transistor is formed using the oxide semiconductor in an amorphous state, interface scattering can be reduced, and relatively high mobility can be obtained with relative ease.

In an oxide semiconductor having crystallinity, defects in the bulk can be further reduced. When a surface flatness is improved, mobility higher than that of an oxide semiconductor in an amorphous state can be obtained. In order to improve the surface flatness, the oxide semiconductor is preferably formed on a flat surface. Specifically, the oxide semiconductor may be formed on a surface with an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, further preferably 0.1 nm or less.

Note that Ra is obtained by expanding centerline average roughness, which is defined by JIS B 0601, into three dimensions so as to be applicable to a plane. Moreover, Ra can be expressed as average value of the absolute values of deviations from a reference surface to a specific surface and is defined by Formula 1.

Ra = 1 S 0 y 1 y 2 x 1 x 2 f ( x , y ) - Z 0 x y [ Formula 1 ]

Note that in Formula 1, S0 represents the area of a measurement surface (a rectangular region defined by four points represented by the coordinates (x1,y1), (x1, y2), (x2,y1), and (x2,y2)), and Z0 represents average height of the measurement surface. Further, Ra can be measured using an atomic force microscope (AFM).

Here, it is preferable that the oxide semiconductor film be formed so as to contain impurities such as alkali metal, a hydrogen atom, a hydrogen molecule, water, a hydroxyl group, or a hydrogen compound as little as possible, for example, in such a manner that the impurities are prevented from being mixed into a sputtering target and a gas used for deposition. In addition, when a deposition apparatus is sufficiently evacuated during the deposition and the oxide semiconductor film is deposited while the substrate is heated, the concentration of impurities included in the deposited oxide semiconductor film can be lowered. After the oxide semiconductor is deposited, heat treatment may be performed to eliminate moisture or hydrogen in the oxide semiconductor film. The heat treatment may be performed at any time after the deposition of the oxide semiconductor film.

Next, an insulating film 143 is formed over the semiconductor film 129. The insulating film 143 is to be used as a hard mask for etching the semiconductor film 129 to form a semiconductor layer 109; therefore, for the insulating film 143, a material with high etching selectivity with the semiconductor film 129 and a thickness large enough to withstand the etching are employed.

After that, a resist 141 is formed so as to be on and in contact with the insulating film 143 and overlap with a region that is to be the semiconductor layer 109 later. FIG. 2A illustrates a schematic cross-sectional view at this stage.

Then, a hard mask 145 is formed by etching the insulating film 143 in a region that is not covered with the resist 141. The resist 141 may be removed after the formation of the hard mask 145. After that, the semiconductor film 129 in a region that is not covered with the hard mask 145 is subjected to anisotropic etching, thereby obtaining the semiconductor layer 109. Here, etching conditions under which the hard mask 145, the bit line 103, and the base insulating layer 113 are hardly etched are selected.

It is preferable that anisotropic etching under conditions where the hard mask 145 is not etched be performed for etching the semiconductor film 129 and that the formed semiconductor layer 109 have a substantially columnar shape (including a cylinder shape and a polygonal prism shape). If the semiconductor layer 109 has a cone or pyramid shape, for example, the effective channel width of a formed cell transistor 150 decreases when getting closer to a drain (a capacitor electrode); thus, the on-state current is decreased.

Here, in the case where the resist 141 is not removed after the formation of the hard mask 145, the resist 141 is removed after the semiconductor layer 109 is formed.

Next, an insulating film 147 is formed to cover exposed portions of the base insulating layer 113, the bit line 103, the semiconductor layer 109, and the hard mask 145. Since part of the insulating film 147 serves as a gate insulating layer 111 later, the insulating film 147 is formed so that a portion in contact with a side face of the semiconductor layer 109 has a uniform thickness. The insulating film 147 can be formed by a deposition method such as CVD or sputtering. It is preferable that the amount of impurities containing hydrogen atoms, such as water, hydrogen, and a hydrogen compound, be sufficiently small in the insulating film 147 and at the interface between the insulating film 147 and the semiconductor layer 109.

The insulating film 147 can be a single layer or a stack of layers containing silicon oxide, silicon nitride oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy (x>0, y>0)), hafnium silicate to which nitrogen is added (HfSixOyNz (x>0, y>0, z>0)), or hafnium aluminate (HfAlxOyNz to which nitrogen is added (x>0, y>0, z>0)), for example.

FIG. 2B illustrates a schematic cross-sectional view at this stage.

Then, a word line 105 is formed. First, a thick conductive film is deposited so as to fill regions where the semiconductor layer 109 is not formed. The conductive film can be formed by a deposition method such as sputtering or CVD with the use of a material similar to that of the conductive film forming the bit line 103. After that, a surface of the conductive film is planarized. Here, the planarization step is stopped when the insulating film 147 or the hard mask 145 is exposed.

The conductive film is selectively etched by a known photolithography method, thereby forming a pattern of the word lines 105 perpendicular to the bit lines 103.

Then, a thick insulating film is formed so as to fill spaces between the word lines 105 (not illustrated), and after that, a surface of the insulating film is planarized. The planarization step is stopped when the semiconductor layer 109 is exposed. Consequently, the hard mask 145 and part of the insulating film 147 above the semiconductor layer 109 are removed in this planarization step.

Through the above steps, the word line 105 and the gate insulating layer 111 are formed. FIG. 2C illustrates a schematic cross-sectional view at this stage.

Next, an insulating layer 115 is formed to cover a surface of the word line 105 and a top surface of the gate insulating layer 111. The insulating layer 115 is formed in such a manner that an insulating film is formed by a deposition method such as CVD or sputtering and then selectively etched so as to expose the semiconductor layer 109.

After that, a capacitor electrode 107 in contact with a top surface of the semiconductor layer 109 is formed. The capacitor electrode 107 can be formed in such a manner that a conductive film covering the insulating layer 115 and the semiconductor layer 109 is formed by a deposition method such as CVD or sputtering and then selectively etched. FIG. 3A illustrates a schematic cross-sectional view at this stage. The conductive film forming the capacitor electrode 107 can be formed using a material similar to that of the conductive film forming the bit line 103.

Next, an insulating layer 117 and a capacitor line 119 are formed, so that a capacitor 160 is formed over the semiconductor layer 109 (see FIG. 3B).

First, the insulating layer 117 is formed by a deposition method such as CVD, and the capacitor line 119 in contact with the insulating layer 117 is formed. The conductive film forming the capacitor line 119 can be formed using a material similar to that of the conductive film forming the bit line 103. Here, the capacitance of the capacitor 160 can be increased as the thickness of the insulating layer 117 is smaller and as the dielectric constant of the material used for the insulating layer 117 is higher. Note that the capacitor 160 may be formed to have relatively small capacitance because the off-state current of the cell transistor 150 fabricated in this embodiment is extremely low.

The capacitance of the capacitor 160 can be smaller as the off-state current of the cell transistor 150 is lower, that is, as the off-resistance of the cell transistor 150 is higher. For example, when the off-resistance of the cell transistor 150 is 100 times as high as that in general DRAM using silicon, the memory device can operate with the same frequency of refresh operations even if the capacitance of the capacitor 160 is reduced to one hundredth. On the other hand, when the capacitance of the capacitor 160 is the same as that in conventional DRAM, the frequency of refresh operations can be reduced up to one hundredth; consequently, power consumption of the device can be drastically reduced.

The off-resistance of the cell transistor 150 is inversely proportional to the concentration of carriers thermally excited in the semiconductor layer 109 in which the channel is formed. Since the band gap of silicon is 1.1 eV even in a state where there is no carrier caused by a donor or an acceptor (i.e., even in the case of an intrinsic semiconductor), the concentration of thermally excited carriers at room temperature (300 K) is approximately 1×1011 cm−3.

On the other hand, in the case of a semiconductor whose band gap is 3.2 eV, the concentration of thermally excited carriers is approximately 1×10−7 cm−3. When the electron mobility is the same, the resistivity is inversely proportional to the carrier concentration; therefore, the resistivity of the semiconductor whose band gap is 3.2 eV is 18 orders of magnitude higher than that of silicon.

The cell transistor 150 containing such a wide band gap semiconductor can have extremely low off-state current, so that electric charge held in the capacitor 160 can be retained for an extremely long time. Accordingly, the capacitance of the capacitor 160 can be reduced, and in addition, refresh operations can be eliminated or significantly reduced in frequency.

Through the above steps, it is possible to manufacture the memory device 100 including a plurality of memory elements which occupy a very small area on a substrate surface. Moreover, the memory device 100 manufactured through the above steps can have an extremely long data retention period; consequently, a data refresh operation is not needed or the frequency of data refresh operations is very low in the memory device 100.

This embodiment can be combined with any of the other embodiments disclosed in this specification as appropriate.

(Embodiment 3)

This embodiment describes a CAAC-OS (c-axis aligned crystalline oxide semiconductor) which has an amorphous portion and a crystalline portion where crystals are aligned in the c-axis direction.

The CAAC-OS is a new oxide semiconductor.

The CAAC-OS has a c-axis alignment and a triangular or hexagonal atomic arrangement when seen from the direction of an a-b plane, a top surface, or an interface.

In the CAAC-OS, metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner in the c-axis direction.

Further, in the CAAC-OS, the direction of the a-axis or the b-axis varies in the a-b plane (a rotation structure around the c-axis).

The CAAC-OS is a non-single-crystal in a broad sense.

The CAAC-OS has a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when seen from the direction perpendicular to the a-b plane.

In addition, the CAAC-OS is an oxide having a phase where metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction.

The CAAC-OS is not a single crystal, but this does not mean that the CAAC is composed of only an amorphous component.

Although the CAAC-OS includes a crystallized portion (crystalline portion), a boundary between one crystalline portion and another crystalline portion is not clear in some cases.

Nitrogen may be substituted for part of oxygen which is a constituent of the CAAC-OS.

The c-axes of the crystalline portions included in the CAAC-OS may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate where the CAAC-OS is formed or a surface of the CAAC-OS).

The normals of the a-b planes of the crystalline portions included in the CAAC-OS may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate where the CAAC-OS is formed or a surface of the CAAC-OS).

The CAAC-OS can be a conductor, a semiconductor, or an insulator depending on its composition or the like. The CAAC-OS transmits or does not transmit visible light depending on its composition or the like.

For example, the CAAC-OS which is formed into a film shape has a triangular or hexagonal atomic arrangement when observed from the direction perpendicular to a surface of the film or a surface of a substrate with an electron microscope.

Further, when the cross section of the film is observed with an electron microscope, metal atoms are arranged in a layered manner or metal atoms and oxygen atoms (or nitrogen atoms) are arranged in a layered manner.

Examples of a crystal structure of the CAAC-OS will be described with reference to FIGS. 7A to 7E, FIGS. 8A to 8C, and FIGS. 9A to 9C.

In FIGS. 7A to 7E, FIGS. 8A to 8C, and FIGS. 9A to 9C, the vertical direction corresponds to the c-axis direction and a plane perpendicular to the c-axis direction corresponds to the a-b plane.

In this embodiment, an “upper half” and a “lower half” refer to an upper half above the a-b plane and a lower half below the a-b plane (an upper half and a lower half with respect to the a-b plane).

FIG. 7A illustrates a structure A including one hexacoordinate In atom and six tetracoordinate oxygen (hereinafter referred to as tetracoordinate O) atoms proximate to the In atom.

In this specification, a structure showing only oxygen atoms proximate to one metal atom is referred to as a small group.

The structure A is actually an octahedral structure, but is illustrated as a planar structure for simplicity.

Three tetracoordinate O atoms exist in each of the upper half and the lower half in the structure A. The electric charge of the small group in the structure A is 0.

FIG. 7B illustrates a structure B including one pentacoordinate Ga atom, three tricoordinate oxygen (hereinafter referred to as tricoordinate O) atoms proximate to the Ga atom, and two tetracoordinate O atoms proximate to the Ga atom.

All the three tricoordinate O atoms exist on the a-b plane. One tetracoordinate O atom exists in each of the upper half and the lower half in the structure B.

An In atom can also have the structure B because the In atom can have five ligands. The electric charge of the small group in the structure B is 0.

FIG. 7C illustrates a structure C including one tetracoordinate Zn atom and four tetracoordinate O atoms proximate to the Zn atom.

In the structure C, one tetracoordinate O atom exists in the upper half and three tetracoordinate O atoms exist in the lower half. The electric charge of the small group in the structure C is 0.

FIG. 7D illustrates a structure D including one hexacoordinate Sn atom and six tetracoordinate O atoms proximate to the Sn atom.

In the structure D, three tetracoordinate O atoms exist in each of the upper half and the lower half.

The electric charge of the small group in the structure D is +1.

FIG. 7E illustrates a structure E including two Zn atoms.

In the structure E, one tetracoordinate O atom exists in each of the upper half and the lower half. The electric charge of the small group in the structure E is −1.

In this embodiment, a plurality of small groups form a medium group, and a plurality of medium groups form a large group (also referred to as a unit cell).

A rule of bonding between the small groups is described below.

The three O atoms in the upper half with respect to the hexacoordinate In atom in FIG. 7A each have three proximate In atoms in the downward direction, and the three O atoms in the lower half each have three proximate In atoms in the upward direction.

The one O atom in the upper half with respect to the pentacoordinate Ga atom in FIG. 7B has one proximate Ga atom in the downward direction, and the one O atom in the lower half has one proximate Ga atom in the upward direction.

The one O atom in the upper half with respect to the tetracoordinate Zn atom in FIG. 7C has one proximate Zn atom in the downward direction, and the three O atoms in the lower half each have three proximate Zn atoms in the upward direction.

In this manner, the number of tetracoordinate O atoms above a metal atom is equal to the number of metal atoms proximate to and below the tetracoordinate O atoms; similarly, the number of tetracoordinate O atoms below a metal atom is equal to the number of metal atoms proximate to and above the tetracoordinate O atoms.

Since the coordination number of the tetracoordinate O atom is 4, the sum of the number of metal atoms proximate to and below the O atom and the number of metal atoms proximate to and above the O atom is 4.

Accordingly, when the sum of the number of tetracoordinate O atoms above a metal atom and the number of tetracoordinate O atoms below another metal atom is 4, the two kinds of small groups including the metal atoms can be bonded to each other.

The reason therefor is described below. For example, in the case where the hexacoordinate metal (In or Sn) atom is bonded through three tetracoordinate O atoms in the lower half, it is bonded to the pentacoordinate metal (Ga or In) atom or the tetracoordinate metal (Zn) atom.

A metal atom whose coordination number is 4, 5, or 6 is bonded to another metal atom through a tetracoordinate O atom in the c-axis direction.

In addition, a medium group can also be formed in a different manner by combining a plurality of small groups so that the total electric charge of the layered structure is 0.

FIG. 8A illustrates a model of a medium group A included in a layered structure of an In—Sn—Zn—O-based material.

FIG. 8B illustrates a large group B including three medium groups.

FIG. 8C illustrates an atomic arrangement where the layered structure shown in FIG. 8B is observed from the c-axis direction.

In the medium group A, a tricoordinate O atom is omitted for simplicity, and only the number of tetracoordinate O atoms is shown in a circle.

For example, three tetracoordinate O atoms existing in each of the upper half and the lower half with respect to a Sn atom are denoted by circled 3.

Similarly, in the medium group A, one tetracoordinate O atom existing in each of the upper half and the lower half with respect to an In atom is denoted by circled 1.

In addition, in the medium group A, a Zn atom proximate to one tetracoordinate O atom in the lower half and three tetracoordinate O atoms in the upper half, and a Zn atom proximate to one tetracoordinate O atom in the upper half and three tetracoordinate O atoms in the lower half are shown.

In the medium group A included in the layered structure of the In—Sn—Zn—O-based material, in the order starting from the top, a Sn atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half is bonded to an In atom proximate to one tetracoordinate O atom in each of the upper half and the lower half.

The In atom is bonded to a Zn atom proximate to three tetracoordinate O atoms in the upper half.

The Zn atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half through one tetracoordinate O atom in the lower half with respect to the Zn atom.

The In atom is bonded to a small group that includes two Zn atoms and is proximate to one tetracoordinate O atom in the upper half.

The small group is bonded to a Sn atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half through one tetracoordinate O atom in the lower half with respect to the small group.

A plurality of such medium groups are bonded to form a large group.

Here, electric charge for one bond of a tricoordinate O atom and electric charge for one bond of a tetracoordinate O atom can be assumed to be −0.667 and −0.5, respectively.

For example, electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate or hexacoordinate) Sn atom are +3, +2, and +4, respectively. Accordingly, electric charge in a small group including a Sn atom is +1.

Therefore, electric charge of −1, by which the electric charge of +1 is canceled, is needed to form a layered structure including a Sn atom.

As a structure having electric charge of −1, the small group including two Zn atoms as in the structure E can be given.

For example, with one small group including two Zn atoms, electric charge of one small group including a Sn atom can be cancelled, so that the total electric charge of the layered structure can result in 0.

Specifically, by repeating the large group B, an In—Sn—Zn—O-based crystal (In2SnZn3O8) can be obtained.

The layered structure of the In—Sn—Zn—O-based crystal can be expressed by a composition formula, In2SnZn2O7(ZnO)m (m is 0 or a natural number).

The variable m is preferably large because the larger the variable m, the higher the crystallinity of the In—Sn—Zn—O-based crystal.

The same applies to the case where an oxide semiconductor other than the In—Sn—Zn—O-based material is used.

For example, FIG. 9A illustrates a model of a medium group L included in a layered structure of an In—Ga—Zn—O-based material.

In the medium group L included in the layered structure of the In—Ga—Zn—O-based material, in the order starting from the top, an In atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half is bonded to a Zn atom proximate to one tetracoordinate O atom in the upper half.

The Zn atom is bonded to a Ga atom proximate to one tetracoordinate O atom in each of the upper half and the lower half through three tetracoordinate O atoms in the lower half with respect to the Zn atom.

The Ga atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half through one tetracoordinate O atom in the lower half with respect to the Ga atom.

A plurality of such medium groups are bonded to form a large group.

FIG. 9B illustrates a large group M including three medium groups.

FIG. 9C illustrates an atomic arrangement where the layered structure shown in FIG. 9B is observed from the c-axis direction.

Here, since electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate) Ga atom are +3, +2, and +3, respectively, electric charge of a small group including any of the In atom, the Zn atom, and the Ga atom is 0.

As a result, the total electric charge of a medium group having a combination of these small groups always results in 0.

In order to form the layered structure of the In—Ga—Zn—O-based material, a large group can be formed using not only the medium group L but also a medium group in which the arrangement of the In atom, the Ga atom, and the Zn atom is different from that of the medium group L.

This embodiment can be combined with any of the other embodiments disclosed in this specification as appropriate.

(Embodiment 4)

The actually measured field-effect mobility of an insulated gate transistor is lower than its inherent mobility because of a variety of reasons, which occurs not only in the case of using an oxide semiconductor.

One of causes for reduction in the mobility is a defect inside a semiconductor or a defect at an interface between the semiconductor and an insulating film. With a Levinson model, the field-effect mobility based on the assumption that no defect exists inside the semiconductor can be calculated theoretically.

Assuming a potential barrier (such as a grain boundary) exists in a semiconductor, the measured field-effect mobility of the semiconductor, denoted by μ, can be expressed by Formula 2 where the inherent mobility of the semiconductor is μ0.

μ = μ 0 exp ( - E kT ) [ Formula 2 ]

In the formula, E denotes the height of the potential barrier, k denotes the Boltzmann constant, and T denotes the absolute temperature.

Further, on the assumption that the potential barrier is attributed to a defect, the height of the potential barrier can be expressed by Formula 3 according to the Levinson model.

E = e 2 N 2 8 ɛ n = e 3 N 2 t 8 ɛ C ox V g [ Formula 3 ]

In the formula, e denotes the elementary charge, N denotes the average defect density per unit area in a channel, ∈ denotes the permittivity of the semiconductor, n denotes the number of carriers per unit area in the channel, Cox, denotes the capacitance per unit area, Vg denotes the gate voltage, and t denotes the thickness of the channel.

In the case where the thickness of the semiconductor layer is less than or equal to 30 nm, the thickness of the channel can be regarded as being the same as the thickness of the semiconductor layer.

The drain current Id in a linear region is expressed by Formula 4.

I d = W μ V g V d C ox L exp ( - E kT ) [ Formula 4 ]

In the formula, L denotes the channel length and W denotes the channel width, and L and W are each 10 μm in this example.

In addition, Vd denotes the drain voltage.

Both sides of Formula 4 are divided by Vg and then logarithms of both the sides are taken, resulting in Formula 5.

ln ( I d V g ) = ln ( W μ V d C ox L ) - E kT = ln ( W μ V d C ox L ) - e 3 N 2 t 8 kT ɛ C ox V g [ Formula 5 ]

The right side of Formula 5 is a function of Vg.

From Formula 5, it is found that the average defect density N can be obtained from the slope of a line taken with ln(Id/Vg) as the ordinate and 1/Vg as the abscissa.

That is, the average defect density can be evaluated from the Id-Vg characteristics of the transistor.

The average defect density N of an oxide semiconductor in which the ratio of indium (In), tin (Sn), and zinc (Zn) is 1:1:1 is about 1×1012/cm2.

On the basis of the defect density obtained in this manner, or the like, μ0 can be calculated to be 120 cm2/Vs.

The measured mobility of an In—Sn—Zn oxide including a defect is about 35 cm2/Vs.

However, assuming that no defect exists inside an oxide semiconductor and at the interface between the oxide semiconductor and an insulating film, the mobility μ0 of the oxide semiconductor is estimated to be 120 cm2/Vs.

Note that even when no defect exists inside the semiconductor, scattering at an interface between a channel and a gate insulating layer affects the transport property of the transistor. In other words, the mobility μ1 at a position that is a distance x away from the interface between the channel and the gate insulating layer is expressed by Formula 6.

1 μ 1 = 1 μ 0 + D B exp ( - x G ) [ Formula 6 ]

In the formula, D denotes the electric field in the gate direction, and B and G are constants. The values of B and G can be obtained from actual measurement results; according to the above measurement results, B is 4.75×107 cm/s and G is 10 nm (the depth to which the influence of interface scattering reaches).

As D increases (i.e., as the gate voltage increases), the second term of Formula 6 is increased and accordingly the mobility μ1 is decreased.

FIG. 10 shows calculation results E of the mobility μ of a transistor whose channel is formed in an ideal oxide semiconductor without a defect inside the semiconductor.

For the calculation, device simulation software, Sentaurus Device manufactured by Synopsys, Inc. was used

For the calculation, the band gap, the electron affinity, the relative permittivity, and the thickness of the oxide semiconductor were set to 2.8 eV, 4.7 eV, 15, and 15 nm, respectively.

Those values were obtained according to measurement of a thin film of an oxide semiconductor that was formed by sputtering.

Further, the work functions of a gate, a source, and a drain of the transistor were set to 5.5 eV, 4.6 eV, and 4.6 eV, respectively.

The thickness of a gate insulating layer was set to 100 nm, and the relative permittivity thereof was set to 4.1. The channel length and the channel width were each 10 μm, and the drain voltage Vd was set to 0.1 V.

As shown in the calculation results E, the mobility has a peak of more than 100 cm2/Vs at a gate voltage that is a little over 1 V, and decreases as the gate voltage becomes higher because the influence of interface scattering is increased.

In order to reduce interface scattering, it is preferable that a surface of the semiconductor layer be flat at the atomic level (atomic layer flatness).

Characteristics of a minute transistor which was manufactured using an oxide semiconductor having such mobility were calculated.

The transistor used for calculation includes an oxide semiconductor film in which a channel formation region is provided between a pair of n-type semiconductor regions.

For the calculation, the resistivity of the pair of n-type semiconductor regions was set to 2×10−3 Ωcm.

The channel length was set to 33 nm and the channel width was set to 40 nm for the calculation.

Further, a sidewall is provided on a side face of the gate electrode.

The calculation was performed under the condition that part of the semiconductor region which overlaps with the sidewall is an offset region.

For the calculation, device simulation software, Sentaurus Device manufactured by Synopsys, Inc. was used.

FIGS. 11A to 11C show the gate voltage (Vg: a potential difference between the gate and the source) dependence of the drain current (Id, indicated by a solid line) and the mobility (μ, indicted by a dotted line) of the transistor.

The drain current Id was calculated under the assumption that the drain voltage (a potential difference between the drain and the source) was +1 V, and the mobility μ was calculated under the assumption that the drain voltage was +0.1 V.

FIG. 11A shows the calculation result where the thickness of the gate insulating layer was 15 nm.

FIG. 11B shows the calculation result where the thickness of the gate insulating layer was 10 nm.

FIG. 11C shows the calculation result where the thickness of the gate insulating layer was 5 nm.

As the gate insulating layer is thinner, the drain current Id in the off state (off-state current) in particular is significantly decreased.

In contrast, there is no remarkable change in the peak value of the mobility μ and the drain current Id in the on state (on-state current).

FIGS. 12A to 12C show the gate voltage Vg dependence of the drain current Id (indicated by a solid line) and the mobility μ (indicated by a dotted line) of the transistor where the offset length (sidewall length) Loff was 5 nm.

The drain current Id was calculated on the assumption the drain voltage was +1 V, and the mobility μ was calculated on the assumption the drain voltage was +0.1 V.

FIG. 12A shows the calculation result where the thickness of the gate insulating layer was 15 nm.

FIG. 12B shows the calculation result where the thickness of the gate insulating layer was 10 nm.

FIG. 12C shows the calculation result where the thickness of the gate insulating layer was 5 nm.

FIGS. 13A to 13C show the gate voltage dependence of the drain current Id (indicated by a solid line) and the mobility μ (indicated by a dotted line) of the transistor where the offset length (sidewall length) Loff was 15 nm.

The drain current Id was calculated on the assumption that the drain voltage was +1 V, and the mobility μ was calculated on the assumption that the drain voltage was +0.1 V.

FIG. 13A shows the calculation result where the thickness of the gate insulating layer was 15 nm.

FIG. 13B shows the calculation result where the thickness of the gate insulating layer was 10 nm.

FIG. 13C shows the calculation result where the thickness of the gate insulating layer was 5 nm.

In any of the structures, as the gate insulating layer is thinner, the off-state current is significantly decreased, whereas no remarkable change occurs in the peak value of the mobility μ and the on-state current.

The peak of the mobility μ is about 80 cm2/Vs in FIGS. 11A to 11C, about 60 cm2/Vs in FIGS. 12A to 12C, and about 40 cm2/Vs in FIGS. 13A to 13C; thus, the peak of the mobility μ decreases as the offset length Loff is increased.

The same applies to the off-state current.

The on-state current also decreases as the offset length Loff is increased; however, the decrease in the on-state current is much more gradual than the decrease in the off-state current.

Further, any of the graphs shows that the drain current exceeds 10 μA, which is needed for a memory element or the like, at a gate voltage of around 1 V.

This embodiment can be combined with any of the other embodiments disclosed in this specification as appropriate.

(Embodiment 5)

A transistor including an oxide semiconductor containing In, Sn, and Zn can have favorable characteristics by deposition of the oxide semiconductor while heating a substrate or by heat treatment after deposition of an oxide semiconductor film.

The oxide semiconductor preferably contains 5 atomic % or more of each of In, Sn, and Zn.

By intentionally heating the substrate after the deposition of the oxide semiconductor film containing In, Sn, and Zn, the field-effect mobility of the transistor can be increased.

Moreover, the threshold voltage of an n-channel transistor can be shifted in the positive direction.

The positive shift of the threshold voltage of the n-channel transistor makes the absolute value of a voltage used for keeping the n-channel transistor off to decrease, so that power consumption can be reduced.

Further, the n-channel transistor can become a normally-off transistor by a positive shift of the threshold voltage such that the threshold voltage is 0 V or more.

Characteristics of transistors using an oxide semiconductor containing In, Sn, and Zn will be described below.

(Common conditions of Samples A to C)

An oxide semiconductor film was formed over a substrate to have a thickness of 15 nm under the following conditions: a target having a composition ratio of In:Sn:Zn=1:1:1 was used; the gas flow rate was Ar/O2=6/9 sccm; the deposition pressure was 0.4 Pa; and the deposition power was 100 W.

Next, the oxide semiconductor film was etched in an island shape.

Then, a tungsten layer was deposited over the oxide semiconductor film to have a thickness of 50 nm and was etched, so that a source electrode and a drain electrode were formed.

Next, a silicon oxynitride film (SiON) was formed as a gate insulating layer to have a thickness of 100 nm by plasma-enhanced CVD using silane gas (SiH4) and dinitrogen monoxide (N2O).

Then, a gate electrode was formed in the following manner: a tantalum nitride layer was formed to a thickness of 15 nm; a tungsten layer was formed to a thickness of 135 nm; and the layers were etched.

Further, a silicon oxynitride film (SiON) was formed to a thickness of 300 nm by plasma-enhanced CVD and a polyimide film was formed to a thickness of 1.5 μm, thereby forming an interlayer insulating film.

Next, a pad for measurement was formed in the following manner: a contact hole was formed in the interlayer insulating film; a first titanium film was formed to a thickness of 50 nm; an aluminum film was formed to a thickness of 100 nm; a second titanium film was formed to a thickness of 50 nm; and the films were etched.

In this manner, a semiconductor device having a transistor was fabricated.

(Sample A)

In Sample A, heating was not performed to the substrate during the deposition of the oxide semiconductor film.

Furthermore, in Sample A, heat treatment was not performed after the deposition of the oxide semiconductor film and before the etching of the oxide semiconductor film.

(Sample B)

In Sample B, the oxide semiconductor film was deposited with the substrate heated at 200° C.

Further, in Sample B, heat treatment was not performed after the deposition of the oxide semiconductor film and before the etching of the oxide semiconductor film.

The oxide semiconductor film was deposited while the substrate was heated in order to remove hydrogen serving as a donor in the oxide semiconductor film.

(Sample C)

In Sample C, the oxide semiconductor film was deposited with the substrate heated at 200° C.

Further, in Sample C, after the oxide semiconductor film was deposited and before the oxide semiconductor film was etched, heat treatment in a nitrogen atmosphere was performed at 650° C. for one hour and then heat treatment in an oxygen atmosphere was performed at 650° C. for one hour.

The heat treatment at 650° C. for one hour in a nitrogen atmosphere was performed in order to remove hydrogen serving as a donor in the oxide semiconductor film.

Oxygen is also removed by the heat treatment for removing hydrogen, which serves as a donor in the oxide semiconductor film, causing oxygen vacancy serving as a carrier in the oxide semiconductor film.

Hence, heat treatment was performed at 650° C. for one hour in an oxygen atmosphere to reduce oxygen vacancy.

(Characteristics of transistors of Samples A to C)

FIG. 14A shows initial characteristics of a transistor of Sample A.

FIG. 14B shows initial characteristics of a transistor of Sample B.

FIG. 14C shows initial characteristics of a transistor of Sample C.

The field-effect mobility of the transistor of Sample A was 18.8 cm2/Vs.

The field-effect mobility of the transistor of Sample B was 32.2 cm2/Vs.

The field-effect mobility of the transistor of Sample C was 34.5 cm2/Vs.

According to observation of cross sections of oxide semiconductor films, which were formed by deposition methods similar to those of Samples A to C, with a transmission electron microscope (TEM), crystallinity was observed in samples formed by the deposition methods similar to those of Sample B and Sample C, substrates of which were heated during deposition.

Further, surprisingly, the samples, the substrates of which were heated during deposition, had a non-crystalline portion and a crystalline portion having a c-axis crystalline orientation.

In a conventional polycrystal, crystals in the crystalline portion are not aligned and point in different directions. This means that the samples, the substrates of which were heated during deposition, have a novel structure.

Comparison of FIGS. 14A to 14C brings understanding that heat treatment performed on the substrate during or after deposition can remove an hydrogen element serving as a donor, thereby shifting the threshold voltage of the n-channel transistor in the positive direction.

That is, the threshold voltage of Sample B with heating of the substrate during deposition is shifted in the positive direction as compared to the threshold voltage of Sample A without heating of the substrate during deposition.

In addition, it is found from comparison of Sample B and Sample C, the substrates of which were heated during deposition, that the threshold voltage of Sample C with the heat treatment after deposition is more shifted in the positive direction than the threshold voltage of Sample B without the heat treatment after deposition.

As the temperature of heat treatment is higher, a light element such as hydrogen is removed more easily; therefore, hydrogen is more likely to be removed as the temperature of heat treatment is higher.

Accordingly, it is likely that the threshold voltage can be more shifted in the positive direction by further increasing the temperature of the heat treatment during or after deposition.

(Results of Gate BT Stress Test of Sample B and Sample C)

A gate BT stress test was performed on Sample B (without heat treatment after deposition) and Sample C (with heat treatment after deposition).

First, the Vgs-Ids characteristics of each transistor were measured at a substrate temperature of 25° C. and Vds of 10 V to measure the characteristics of the transistor before heating and application of high positive voltage.

Next, the substrate temperature was set to 150° C. and Vds was set to 0.1 V.

After that, Vgs of 20 V was applied to the gate insulating layer and was kept for 1 hour.

Then, Vgs was set to 0 V.

Next, the Vgs-Ids characteristics of the transistor were measured at a substrate temperature of 25° C. and Vds of 10 V to measure the characteristics of the transistor after heating and application of high positive voltage.

Comparison of the characteristics of the transistor before and after heating and application of high positive voltage as described above is referred to as a positive BT test.

On the other hand, first, the Vgs-Ids characteristics of each transistor were measured at a substrate temperature of 25° C. and Vds of 10 V to measure the characteristics of the transistor before heating and application of high negative voltage.

Then, the substrate temperature was set to 150° C. and Vds was set to 0.1 V.

Next, Vgs of −20 V was applied to the gate insulating layer and was kept for 1 hour.

Next, Vgs was set to 0 V.

Then, the Vgs-Ids characteristics of the transistor were measured at a substrate temperature of 25° C. and Vds of 10 V to measure the characteristics of the transistor after heating and application of high negative voltage.

Comparison of the characteristics of the transistor before and after heating and application of high negative voltage as described above is referred to as a negative BT test.

FIG. 15A shows the result of the positive BT test of Sample B. FIG. 15B shows the result of the negative BT test of Sample B.

FIG. 16A shows the result of the positive BT test of Sample C. FIG. 16B shows the result of the negative BT test of Sample C.

Although the positive BT test and the negative BT test are tests for determining the deterioration degree of a transistor, it is found from FIG. 15A and FIG. 16A that the threshold voltage can be shifted in the positive direction by performing at least the positive BT test.

In particular, FIG. 15A reveals that the positive BT test made the transistor a normally-off transistor.

It is therefore found that performing the positive BT test in addition to the heat treatment in the fabrication process of the transistor makes it possible to promote a shift of the threshold voltage in the positive direction and consequently a normally-off transistor can be fabricated.

FIG. 17 shows the relation between the off-state current of the transistor of Sample A and the inverse of the substrate temperature (absolute temperature) at measurement.

In FIG. 17, the horizontal axis represents a value (1000/T) obtained by multiplying the inverse of the substrate temperature at measurement by 1000.

The amount of current in FIG. 17 is the amount of current per micrometer in the channel width.

The off-state current was less than or equal to 1×10−19 A at a substrate temperature of 125° C. (1000/T is about 2.51).

The off-state current was less than or equal to 1×10−20 A at a substrate temperature of 85° C. (1000/T is about 2.79).

In other words, it was found that the off-state current of the transistor containing an oxide semiconductor is extremely low as compared to a transistor containing a silicon semiconductor.

The off-state current is decreased as the temperature decreases; therefore, it is clear that the off-state current at ordinary temperature is still lower.

This embodiment can be combined with any of the other embodiments disclosed in this specification as appropriate.

(Embodiment 6)

In this embodiment, an example of a memory device in which memory elements are stacked over a substrate where a semiconductor circuit is formed will be described with reference to FIG. 4 and FIG. 5.

FIG. 4 is a schematic cross-sectional view of a memory device 200. In the memory device 200, a circuit (a driver circuit 203) for driving a memory element, such as a sense amplifier and a decoder, is formed over a surface of a single crystal semiconductor substrate 201 using a known technique for forming a semiconductor integrated circuit. A cell transistor layer 205 is formed over the driver circuit 203, and a capacitor layer 207 is formed over the cell transistor layer 205.

Cell transistors and capacitors illustrated in FIG. 4 can be formed according to Embodiment 2.

A bit line of the cell transistor is electrically connected to the driver circuit 203 positioned therebelow through a contact plug. Accordingly, a potential signal output from the driver circuit 203 is input to each of the cell transistors through a common bit line.

Although not illustrated, a word line in the cell transistor layer 205 is electrically connected to the driver circuit 203 through a contact plug or the like in a similar manner. Thus, the on/off state of the cell transistor can be controlled in accordance with the potential output from the driver circuit 203.

In the memory device 200 with such a structure, the cell transistors are controlled by the driver circuit 203 positioned below the cell transistors, whereby write and read operations can be performed.

The integrated cell transistor layer 205 and capacitor layer 207 are stacked over the single crystal semiconductor substrate 201 in the above manner, whereby a more highly integrated memory device 200 which occupies a very small area on a substrate surface can be provided.

Here, a cell transistor layer and a capacitor layer can be further stacked over an insulating layer formed over the cell transistor layer 205 and the capacitor layer 207.

As an example of the structure where cell transistor layers are stacked, FIG. 5 illustrates a schematic cross-sectional view of a memory device 220.

In the memory device 220, a cell transistor layer 205 a, a capacitor layer 207 a, a cell transistor layer 205 b, and a capacitor layer 207 b are stacked in this order over the driver circuit 203 formed over a surface of the single crystal semiconductor substrate 201.

FIG. 5 illustrates a schematic cross section including a region where a bit line in the cell transistor layer 205 b, which is the second layer from the substrate, is electrically connected to the driver circuit 203 through a contact plug.

An insulating layer is provided between the capacitor layer 207 a and the cell transistor layer 205 b. In order to reduce parasitic capacitance generated between a capacitor wiring in the capacitor layer and a bit line and between the capacitor wiring and a word line, the insulating layer may be formed to have a sufficiently large thickness or formed using an insulating material with a low dielectric constant.

Note that this embodiment exemplifies the structure where two layers of memory elements composed of cell transistors and capacitors are stacked; however, without limitation to this, a stack of three or more layers can be employed. In addition, the structure where the cell transistors in the second layer are provided directly above the cell transistors in the first layer is shown here; alternatively, the cell transistors in the second layer may be shifted in the direction parallel to the substrate surface.

As described above, the area of a substrate surface occupied by memory cells is further reduced in the memory device 220 having a multilayer structure in which memory elements are stacked with an insulating layer placed therebetween; thus, a highly integrated memory device 220 can be provided.

This embodiment can be combined with any of the other embodiments disclosed in this specification as appropriate.

This application is based on Japanese Patent Application serial No. 2011-052448 and No. 2011-112648 filed with Japan Patent Office on Mar. 10, 2011 and May 19, 2011, respectively, the entire contents of which are hereby incorporated by reference.

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