US9230967B2 - Method for forming self-aligned isolation trenches in semiconductor substrate and semiconductor device - Google Patents
Method for forming self-aligned isolation trenches in semiconductor substrate and semiconductor device Download PDFInfo
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- US9230967B2 US9230967B2 US14/251,765 US201414251765A US9230967B2 US 9230967 B2 US9230967 B2 US 9230967B2 US 201414251765 A US201414251765 A US 201414251765A US 9230967 B2 US9230967 B2 US 9230967B2
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000002955 isolation Methods 0.000 title claims abstract description 30
- 125000006850 spacer group Chemical group 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims description 25
- 230000000903 blocking effect Effects 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- 230000000873 masking effect Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 description 13
- 238000012545 processing Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- 238000000059 patterning Methods 0.000 description 1
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- 238000012876 topography Methods 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H01L27/10805—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H01L27/10885—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Abstract
The instant disclosure relates to a method for forming self-aligned isolation trenches in semiconductor substrate, comprising the following steps. The first step is providing a semiconductor substrate defined a plurality of active areas thereon. The next step is forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines. The next step is forming a self-aligned spacer on the sidewalls of each of the insulating structures. The last step is selectively removing the semiconductor substrate with the self-aligned spacers as masks to form a plurality of isolation trenches.
Description
1. Field of the Invention
The instant disclosure relates to a method of forming insolating structures; in particular, to a method for forming self-aligned isolation trenches in semiconductor substrate.
2. Description of Related Art
Dynamic random access memory (DRAM) is an electronic data storage device. In DRAM, each bit of binary data is stored in a tiny circuit called a memory cell consisting of a transistor and a capacitor. Generally, the better operating capability of computer software becomes, the greater memory capacitance of computer hardware need. Thus, the method for manufacturing DRAM capacitors is now an indispensable technology.
With the vigorous development of semiconductor industry, the dimension of integrated circuit elements nowadays range from micron size to submicron size. For DRAM, that is to say the cross-sectional area of each capacitor and each gap between capacitors become smaller. The traditional method for patterning the target layer on the substrate comprises the following steps. A photoresist material is spin-coated on the target layer in the first place. The photoresist material is exposed and developed through a patterned mask to form a patterned photoresist layer in the second place. Further, a process of etching is conducted to pattern the target layer by using the patterned photoresist layer as the etch mask.
However, in view of the resolution of pattern transfer is increased and the critical dimension of the line width is reduced. Limitation exists for improving lithography by only optical improvement.
In addition, MIM (Metal insulator Metal) capacitors basically a parasitic capacitor between the metal layers. Generally three or more reticles are used in the processing steps. In order to overcome its complex process, the design of DRAM will focus on a reduction in the number of reticles used.
The object of the instant disclosure is to provide a method for forming self-aligned isolation trenches in semiconductor substrate. The instant method can reduce the reticle requirements as well as accurately place well-defined isolation trenches in the semiconductor substrate.
In order to achieve the aforementioned objects, according to an embodiment of the instant disclosure, a method for forming self-aligned isolation trenches in semiconductor substrate includes the following steps: providing a semiconductor substrate defined a plurality of active areas thereon; forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines; forming a self-aligned spacer on the sidewalls of each of the insulating structures; selectively removing the semiconductor substrate with the self-aligned spacers as masks to form a plurality of isolation trenches.
In order to achieve the aforementioned objects, according to an embodiment of the instant disclosure, a semiconductor device is further provided. The semiconductor device includes a semiconductor substrate, a plurality of buried bit lines, a plurality of insulating structures, and a plurality of self-aligned spacers. The semiconductor substrate has a plurality of active areas defined thereon. The buried bit lines are disposed in the semiconductor substrate, wherein two of the buried bit lines are positioned in each of the active areas. The insulating structures are disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the two of the buried bit lines. The self-aligned spacers are disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate.
Based on the above, because the buried bit lines and the isolation trenches can be formed in the semiconductor substrate, the DRAM device having 4F2 size can be achieved. Moreover, the buried bit lines and the isolation trenches are formed via a self-aligned process which is used to substitute the lithography process. In other words, the buried bit lines and the isolation trenches can be accurately placed in the semiconductor substrate without any reticle. Hence, the instant method can reduce the reticle requirements to reduce the processing cost.
In order to further appreciate the characteristics and technical contents of the instant disclosure, references are hereunder made to the detailed descriptions and appended drawings in connection with the instant disclosure. However, the appended drawings are merely shown for exemplary purposes, rather than being used to restrict the scope of the instant disclosure.
The aforementioned illustrations and following detailed descriptions are exemplary for the purpose of further explaining the scope of the instant disclosure. Other objectives and advantages related to the instant disclosure will be illustrated in the subsequent descriptions and appended drawings.
The instant disclosure relates to a novel method for forming self-aligned isolation trenches in semiconductor substrate. The instant method not only can accurately place well-defined isolation trenches without any reticle, but also can help improve the alignment of the landing areas of capacitors and bit line contacts and buried bit line trenches. Hence, the instant method can increase the yield rate of DRAM modules.
Please refer to FIG. 1 as well as FIGS. 2-7 . FIG. 1 is a process diagram of the method for forming self-aligned isolation trenches in semiconductor substrate. FIGS. 2-7 are cross-sectional diagrams illustrating the processing steps of the instant method. Following will describe the method for forming self-aligned isolation trenches in semiconductor substrate. Thus, the instant disclosure can be performed by any person skilled in the art when understanding its features. Basically, the method comprises the following steps:
Step 10 is providing a semiconductor substrate 1 defined a plurality of active areas AA thereon. Referring to FIG. 2 , the step S11 further comprises, but not limited to, providing a substrate S, then sequentially forming a pad layer 11, a first mask layer 12, and a second mask layer 13 on the substrate S.
In practice, the substrate S can be a silicon substrate or any other suitable substrate. The pad layer 11 is made of oxide (pad oxide layer) or nitride (pad nitride layer). The first mask layer 12 and the second mask layer 13 are made of, but not limited to, silicon nitride and polysilicon respectively. In addition, the material of the first or second mask layers 12, 13 can be selected based on the etch selectivity either. For example, the material of the first or second mask layers 12, 13 is selected from the group consisting of silicon nitride, silicon oxide, and polysilicon.
Referring to FIG. 1A as well as FIGS. 3-5 , step S12 is forming at least two buried bit lines 2 a in each of the active areas AA and an insulating structure 2 b disposed above and opposite to the at least two buried bit line 2 a. It is notable that the step S12 is a key step of the instant disclosure. Concretely speaking, the step S12 further comprises, but not limited to, the following steps. First, a process of deposition is conducted to form a blocking layer 21 over the second mask layer 13, and a process of partial etch is then conducted to pattern the blocking layer 21 to define a plurality of bit line areas BL (step S121). Specifically, each of the bit line areas BL is among and vertically overlapped with each of the active areas AA. Second, another process of deposition is conducted to form a sacrificial layer 22 that conformally covers the patterned blocking layer 21 (step S122). That is, the sacrificial layer 22 can define a plurality of first openings 220 therein, and the first openings 220 are among the bit line areas BL respectively.
Third, still another process of deposition is conducted to form a masking material over the patterned blocking layer 21 and fill the first openings 220, then a process of etch is conducted remove a portion of the masking material outside the first openings 220 to form a plurality of masking structures 23, and then a process of etch back is conducted to etch each of the masking structures 23 to have a desired thickness (step S123). Fourth, another process of partial etch is conducted to selectively remove the sacrificial layer 22, the second mask layer 13, the first mask layer 12, the pad layer 11, and the substrate S in order with the patterned blocking layer 21 and the masking structures 23 as self-aligned masks to form two bit line trenches 10 a in each of the bit line areas BL (step S124).
After that, the masking structures 23 and the remained sacrificial layer 22 are completely removed, and still another process of partial etch id conducted to selectively remove the second mask layer 13 with the patterned blocking layer 21 as mask to form a plurality of second openings 130 (step S125). Specifically, each of the second openings 130 is opposite to the two bit line trenches 10 a. Finally, a dielectric body 24 is formed to fill each of the second openings 130 and the corresponding two bit line trenches 10 a (step S126). Consequently, there are two buried bit lines 2 a in each of the bit line areas BL, and there is an insulating structure 2 b disposed above and opposite to the at least two buried bit lines 2 a.
In the step S120, the blocking layer 21 can be made of oxide rich material, and be patterned via a selective etch process. That is to say, a patterned photoresist layer (not shown) is formed to partially cover the surface of the blocking layer 21 in the first place. A process of etch is conducted to pattern the blocking layer 21 through the patterned photoresist layer in the second place. In the step S121, the sacrificial layer 22 can be made of silicon rich material such as silicon nitride, and be formed along topography via atomic layer deposition (ALD). In this way, the thickness of the sacrificial layer 22 can be controlled at sub-micron level, and the uniformity of the sacrificial layer 22 can be improved. In the step S122, the masking structures 23 can be made of silicon rich material either.
Consequently, in the step S123, a portion of the sacrificial layer 22 made of silicon rich material and the semiconductor substrate 1 can be removed via a plasma etching process or a reactive ion etching process with the patterned blocking layer 21 and the masking structures 23 as self-aligned masks to form the bit line trenches 10 a without any reticle. Specifically, the etching gas can be selected to exhibit high selectivity for silicon such as the mixing gas of HBr and O2. Thus, over-etching effect on the other layer can be prevented in the etching process.
Referring to FIG. 6 , step S14 is forming a self-aligned spacer 3 on the sidewalls of each of the insulating structures 2 b. It is notable that the step S13 is another key step of the instant disclosure. In practice, the self-aligned spacers 3 can be made of silicon nitride, silicon oxide, or silicon carbon. Concretely speaking, the step S13 further comprises, but not limited to, the following steps. A spacer material (not shown) is conformally deposited over the semiconductor substrate 1 in the first place. Further, a process of etch back is performed on the spacer material to form the self-aligned spacers 3 to partially expose the surface of the semiconductor substrate 1.
Referring to FIG. 7 , step S16 is selectively removing the semiconductor substrate 1 with the self-aligned spacers 3 as masks to form a plurality of isolation trenches 10 b that isolate the buried bit lines 2 a in different active areas AA. Most importantly, the landing areas of capacitor and bit line contact C, BLC are defined while the formation of the isolation trenches 10 b. For each active area AA, a landing area of bit line contact BLC is positioned between two buried bit lines 2 a. Moreover, two landing areas of capacitor are positioned between each of the two buried bit lines 2 a and the adjacent isolation trench 10 b. Specifically, the dimension of each landing area of capacitor C can be adjusted according to the thickness of each self-aligned spacer 3.
Please refer to FIGS. 6 and 7 again, the technical features of the method for forming self-aligned isolation trenches in semiconductor substrate are mentioned above. So the instant disclosure further relates to a semiconductor device which includes a semiconductor substrate 1, a plurality of buried bit lines 2 a, a plurality of insulating structures 2 b, and a plurality of self-aligned spacers 3.
In this embodiment, the semiconductor substrate 1 has a plurality of active areas AA defined thereon. The buried bit lines 2 a are disposed in the semiconductor substrate 1, wherein two of the buried bit lines 2 a are positioned in each of the active areas AA. The insulating structures 2 b are disposed on the semiconductor substrate 1, wherein each of the insulating structures 2 b is positioned on and opposite to the two of the buried bit lines 2 a. The self-aligned spacers 3 are disposed on the sidewalls of the insulating structures 2 b respectively to partially expose the surface of the semiconductor substrate 1. By the way, the processing steps for forming the semiconductor substrate 1, the buried bit lines 2 a, the insulating structures 2 b, and the self-aligned spacers 3 are mentioned above. No attention is given to said processing steps.
Based on above, the instant method for forming self-aligned isolation trenches in semiconductor substrate, in comparison with the traditional one, has the following advantages.
Firstly, because the buried bit lines and the isolation trenches can be formed in the semiconductor substrate, the DRAM device having 4F2 size can be achieved. Moreover, the buried bit lines and the isolation trenches are formed via a self-aligned process which is used to substitute the lithography process. In other words, the buried bit lines and the isolation trenches can be accurately placed in the semiconductor substrate without any reticle. Hence, the instant method can reduce the reticle requirements to reduce the processing cost.
Further, the isolation trenches are formed through the self-aligned spacers. Thus, the instant method not only can simplify the processing steps, but also can prevent the offset of the landing areas of capacitor due to the misalignment of reticle or the smaller dimension. In this way, the instant method can increase the yield rate of the DRAM device and miniaturize the DRAM device.
Furthermore, the instant method can easily control the dimension of the landing areas of capacitor by setting the process parameters. Consequently, the uniformity of the subsequently formed capacitors can be improved.
The descriptions illustrated supra set forth simply the preferred embodiments of the instant disclosure; however, the characteristics of the instant disclosure are by no means restricted thereto. All changes, alternations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the instant disclosure delineated by the following claims.
Claims (3)
1. A method for forming self-aligned isolation trenches in semiconductor substrate, comprising the following steps:
providing a semiconductor substrate defined a plurality of active areas thereon, wherein the step of providing a semiconductor substrate comprises:
forming a pad layer on a substrate;
forming a first mask layer on the pad layer; and
forming a second mask layer on the first hard mask layer;
forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines, wherein the step of forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines further comprises:
forming a patterned blocking layer on the second mask layer to define a plurality of bit line areas, each of which is among and vertically overlapped with each of the active areas;
conformally forming a sacrificial layer over the patterned blocking layer, wherein the sacrificial layer has a plurality of first openings defined therein, and the first openings are among the bit line areas respectively;
forming a plurality of masking structures in the first openings respectively;
selectively removing the sacrificial layer, the second mask layer, the first mask layer, the pad layer, and the substrate with the patterned blocking layer and the masking structures as masks to form two bit line trenches in each of the bit line areas;
completely removing the masking structures and the remained sacrificial layer, and selectively removing the second mask layer with the patterned blocking layer as mask to form a plurality of second openings, each of which is opposite to the two bit line trenches; and
filling a dielectric body into each of the second openings and the corresponding two bit line trenches;
forming a self-aligned spacer on the sidewalls of each of the insulating structures; and
selectively removing the semiconductor substrate with the self-aligned spacers as masks to form a plurality of isolation trenches.
2. The method for forming self-aligned isolation trenches in semiconductor substrate according to claim 1 , wherein the step of forming a plurality of masking structures in the first openings respectively further comprises etching back each of the masking structures to a desired thickness.
3. The method for forming self-aligned isolation trenches in semiconductor substrate according to claim 1 , wherein the step of forming a self-aligned spacer on the sidewalls of each of the insulating structures further comprises:
conformally depositing a spacer material on the semiconductor substrate; and
selectively removing the spacer material to form the self-aligned spacer on the sidewalls of each of the insulating structures via a dry etch-back process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/733,047 US20150294972A1 (en) | 2013-12-18 | 2015-06-08 | Semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102146985 | 2013-12-18 | ||
| TW102146985A | 2013-12-18 | ||
| TW102146985A TWI520265B (en) | 2013-12-18 | 2013-12-18 | Method for forming self-aligned trench isolation in semiconductor substrate and semiconductor device |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US14/733,047 Continuation US20150294972A1 (en) | 2013-12-18 | 2015-06-08 | Semiconductor device |
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| Publication Number | Publication Date |
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| US20150171162A1 US20150171162A1 (en) | 2015-06-18 |
| US9230967B2 true US9230967B2 (en) | 2016-01-05 |
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| US14/733,047 Abandoned US20150294972A1 (en) | 2013-12-18 | 2015-06-08 | Semiconductor device |
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| US14/733,047 Abandoned US20150294972A1 (en) | 2013-12-18 | 2015-06-08 | Semiconductor device |
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| TW (1) | TWI520265B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9911652B1 (en) * | 2017-03-29 | 2018-03-06 | International Business Machines Corporation | Forming self-aligned vias and air-gaps in semiconductor fabrication |
| TWI830489B (en) * | 2022-11-09 | 2024-01-21 | 華邦電子股份有限公司 | Dynamic random access memory and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080265303A1 (en) * | 2007-04-27 | 2008-10-30 | Samsung Electronics Co., Ltd. | Methods of forming shallow trench isolation structures with buried bit lines in non-volatile memories and devices, cards, and systems so formed |
| US8207583B2 (en) * | 2006-03-02 | 2012-06-26 | Micron Technology, Inc. | Memory device comprising an array portion and a logic portion |
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2013
- 2013-12-18 TW TW102146985A patent/TWI520265B/en active
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2014
- 2014-04-14 US US14/251,765 patent/US9230967B2/en active Active
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2015
- 2015-06-08 US US14/733,047 patent/US20150294972A1/en not_active Abandoned
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8207583B2 (en) * | 2006-03-02 | 2012-06-26 | Micron Technology, Inc. | Memory device comprising an array portion and a logic portion |
| US20080265303A1 (en) * | 2007-04-27 | 2008-10-30 | Samsung Electronics Co., Ltd. | Methods of forming shallow trench isolation structures with buried bit lines in non-volatile memories and devices, cards, and systems so formed |
Also Published As
| Publication number | Publication date |
|---|---|
| US20150294972A1 (en) | 2015-10-15 |
| TW201526159A (en) | 2015-07-01 |
| TWI520265B (en) | 2016-02-01 |
| US20150171162A1 (en) | 2015-06-18 |
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