US9583594B2 - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device Download PDF

Info

Publication number
US9583594B2
US9583594B2 US14/829,649 US201514829649A US9583594B2 US 9583594 B2 US9583594 B2 US 9583594B2 US 201514829649 A US201514829649 A US 201514829649A US 9583594 B2 US9583594 B2 US 9583594B2
Authority
US
United States
Prior art keywords
forming
pattern
semiconductor device
spacers
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14/829,649
Other versions
US20170025519A1 (en
Inventor
Duan Quan Liao
Yikun Chen
Ching Hwa Tey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, YIKUN, LIAO, DUAN QUAN, TEY, CHING HWA
Priority to US15/401,086 priority Critical patent/US20170117150A1/en
Publication of US20170025519A1 publication Critical patent/US20170025519A1/en
Application granted granted Critical
Publication of US9583594B2 publication Critical patent/US9583594B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body

Definitions

  • the invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device being formed through a sidewall image transference process and a method of forming the same.
  • the sidewall image transfer process includes firstly forming a plurality of sacrificial patterns on a substrate, wherein the dimension of such sacrificial patterns is substantially greater or equal to the critical dimension of photolithography. Then, spacers are formed on sidewalls of the sacrificial patterns through a deposition and an etching process. Since the dimension of the spacers may be smaller than the critical dimension, patterns of the spacers may be transferred into the substrate by using the spacers as mask to form a smaller fin structure.
  • the electrical and physical requirements in each part of the devices become critical, like the dimensions and shapes of the wiring and the transistor and the spacing therebetween for example. Thus, how to achieve standard requirements and overcome the physical limitations has become an important issue in the industry of the semiconductor.
  • the present invention provides a semiconductor device including a mask layer and a plurality of spacers.
  • the mask layer is disposed on a target layer and includes a first material and a second material.
  • the spacers are disposed on the mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.
  • the present invention provides a method of forming a semiconductor device, including following steps. First of all, a first pattern is formed on a target layer. Next, a plurality of second patterns is formed on the target layer, wherein at least one of the second patterns crosses the first pattern. Then, a plurality of the spacers is formed to surround the second patterns, wherein the spacers are disposed on the first pattern. Finally, a removing process is performed to remove a portion of the target layer by using the spacers and the first pattern as a mask.
  • the semiconductor device and the forming method thereof in the present invention mainly replaces a portion of the hard mask layer with the blocking pattern, and then forms the sacrificial patterns and the spacers on the hard mask layer, for blocking a portion of the patterns of the spacers.
  • the semiconductor device formed accordingly may obtain specific layout.
  • the blocking pattern of the present embodiment is formed below the spacers, and being defined by an opening pattern, the critical dimension of the blocking pattern may be precisely controlled, substantially being 20 nm to 60 nm for example.
  • the present invention is able to form blocking patter in relative smaller dimension, so that, the semiconductor device formed accordingly may obtain further specific layout.
  • FIG. 1 to FIG. 4 are schematic diagrams illustrating a method of forming a semiconductor device according to a first embodiment of the present invention.
  • FIG. 5 to FIG. 13 are schematic diagrams illustrating a method of forming a semiconductor device according to a second embodiment of the present invention, wherein FIG. 5 , FIG. 8 , and FIG. 13 show top views of the semiconductor device in forming steps, and FIG. 6 and FIG. 9 show cross-sectional views taken along a cross line A-A′ in FIG. 5 and FIG. 8 .
  • FIG. 14 is a schematic diagram illustrating a method of forming a semiconductor device according to a third embodiment of the present invention.
  • FIG. 1 to FIG. 4 are schematic diagrams illustrating a method of forming a semiconductor device according to the first embodiment of the present invention.
  • the substrate 100 may include a dielectric material, such as a dielectric layer, as shown in FIG. 1 .
  • the dielectric layer may include a multilayer structure, for example a composite structure consisted of low dielectric constant (low-k) materials (having a dielectric constant less than 3.9), such as silicon oxide, silicon oxynitride and silicon carbonitride, but is not limited thereto.
  • low-k low dielectric constant
  • the substrate 100 may include a semiconductor material, like, a silicon substrate, a silicon-containing substrate or a silicon-on-insulator (SOI) substrate for example, or a non-semiconductor material, like a glass substrate for example.
  • the substrate 100 may include other semiconductor device formed therein or thereon.
  • MOS metal oxide semiconductor
  • the substrate may include at least one metal oxide semiconductor (MOS) transistor (not shown in the drawings) may be formed on the silicon substrate, or at least one dielectric material layer (not shown in the drawings) is formed on the silicon substrate and at least one metal oxide semiconductor transistor (not shown in the drawings) may be formed in the dielectric material layer, but is not limited thereto.
  • the conductive layer 120 is formed in the substrate 100 , and the conductive layer 120 may include any conductive unit or metal contact, such as a contact plug, via plug or wiring, as shown in FIG. 1 .
  • the conductive layer 120 of the present invention is not limited to the aforementioned types, and in the embodiment of having silicon substrate or other semiconductor substrate (not shown in the drawings), the conductive layer may include a gate electrode (not shown in the drawings) formed on the silicon substrate, or a source/drain region (not shown in the drawings) formed in the silicon substrate.
  • the target layer 140 may include an inter-layer dielectric (ILD) layer, for example including a low dielectric constant (less than 3.9) material, like silicon oxide, silicon oxynitride or silicon carbonitride for example, but is not limited thereto.
  • the target layer 140 may also include other suitable materials, such as semiconductor materials, conductive materials or non-conductive materials.
  • the hard mask layer 160 preferable includes a multilayer structure, for example being a composite structure consisted of a silicon oxide layer 161 , a metal nitride layer 162 and a silicon oxide layer 163 , as shown in FIG. 1 , but is not limited thereto.
  • the hard mask layer 160 may be optionally omitted, so that, a sacrificial pattern (not shown in the drawings) may be formed directly on the target layer 140 .
  • the formation of the sacrificial pattern 180 may be integrated into a conventional semiconductor process, for example, a general photolithographic etching pattern (PEP) process or a multi-patterning process may be performed to form a plurality of the sacrificial patterns 180 on the hard mask layer 160 .
  • the sacrificial patterns 180 may include polysiliocn or other materials having etching selectivity relative to the hard mask layer 160 underneath, such as silicon oxide or silicon nitride.
  • the forming method, as well as the materials, of the sacrificial patterns 180 are not limited thereto, and may include other processes or materials which are well known in the art and will not be further detailed herein.
  • an etching stop layer 110 may be optionally formed on the substrate 100 , before the target layer 140 is formed, as shown in FIG. 1 .
  • the forming method of the spacers 200 may includes firstly forming a spacer material layer (not shown in the drawings) on the substrate 100 to cover the sacrificial patterns 180 , and performing an etching back process to completely remove the spacer material layer on top surfaces of the sacrificial patterns 180 , so as to form the spacers 200 surrounding the sacrificial patterns 180 and adjacent thereto.
  • the spacers 200 preferably include titanium dioxide (TiO 2 ) or other materials having etching selectivity relative to the sacrificial patterns 180 and the hard mask layer 160 , such as tungsten (W), tantalum nitride (TaN) or titanium nitride (TiN), but are not limited thereto.
  • TiO 2 titanium dioxide
  • other materials having etching selectivity relative to the sacrificial patterns 180 and the hard mask layer 160 such as tungsten (W), tantalum nitride (TaN) or titanium nitride (TiN), but are not limited thereto.
  • a blocking pattern 220 is formed on the hard mask layer 160 to cross and to cover at least one of the spacer 200 .
  • a sacrificial layer 400 may be formed previously, before the blocking pattern 220 is formed, and the sacrificial layer 400 may include materials having etching selectivity relative to the hard mask layer 160 and better gap-filling ability, like anti-reflective coating (ARC) materials, polysilicon or oxide materials for example, so as to completely cover the hard mask layer 160 and the spacers 200 formed on the hard mask layer 160 .
  • ARC anti-reflective coating
  • the sacrificial layer 400 may optionally include a composite structure, for example including a silicon-containing hard mask (SHB) layer 401 and an organic dielectric (ODL) layer 402 , as shown in FIG. 3 , wherein the organic dielectric layer 402 may be made of 365 nm I-line photoresist material or novolac resin, but is not limited thereto.
  • SHB silicon-containing hard mask
  • ODL organic dielectric
  • an etching process such as a dry etching process, a wet etching or a sequentially performed dry and wet etching process, is performed by using the spacers 200 and the blocking pattern 220 as a mask, to transfer patterns of the spacers 200 which are not blocked by the blocking pattern 220 to the hard mask layer 160 underneath.
  • the patterns of the spacers 200 may be firstly transferred to a portion of the hard mask layer 160 , for example, only the silicon oxide layer 163 and the metal nitride layer 162 , but not limited thereto.
  • the patterns of the spacers 200 may also be transferred to the whole hard mask layer 160 , optionally.
  • a portion of the spacers 200 is blocked by the blocking pattern 220 , so that, only the patterns of the spacers 200 which are not blocked by the blocking pattern 220 may be successfully transferred to the hard mask layer 160 , as shown in FIG. 4 .
  • patterns of the hard mask layer 160 may be further transferred to the target layer 140 formed below, thereby forming at least one opening (not shown in the drawings) directly connecting to the conductive layer 120 . It is noted that, since the blocking pattern 220 has partially blocked the patterns of the spacers 220 in the aforementioned process, the opening formed according to the spacers 220 may be divided into two parts, or be formed only in particular region.
  • a semiconductor process such as a silicidation process or a plug process
  • a semiconductor device such as a contact plug, a wiring or a transistor, directly contacting to the conductive layer 120 , thereby forming the semiconductor device having specific layout in the following processes.
  • the semiconductor device according to the first embodiment of the present invention is obtained.
  • the detailed dimensions and relative ratio of the sacrificial pattern, the spacers and the blocking pattern of the present invention are not limited to that shown in FIGS. 1-4 , and may be further adjusted according to practical requirements.
  • the forming method thereof utilizes the blocking pattern to block a portion of the spacers, for partially blocking the patterns of the spacers, such that, the semiconductor device formed accordingly may obtain specific layout.
  • optical proximity effects may easily occur in the photolithographic process during the formation of the blocking pattern especially while the size of semiconductor device has shrunk to a particular degree, thereby causing overexposure or underexposure to the blocking patterns which may not meet the practical requirements of the processes.
  • the dimension of the blocking pattern may not be properly controlled, so that, the deformed or dislocated blocking patterns may be formed accordingly, damaging to the expected layout, and even affecting the performance of the semiconductor device.
  • FIG. 5 to FIG. 13 are schematic diagrams illustrating a method of forming a semiconductor device according to the second embodiment of the present invention, wherein FIG. 5 , FIG. 8 , and FIG. 13 show the top views of the semiconductor device in forming steps, and FIG. 6 and FIG. 9 show the cross-sectional views taken along the cross line A-A′ in FIG. 5 and FIG. 8 .
  • the formal steps in the present embodiment are similar to those in the first embodiment, which include sequentially forming the etching stop layer 110 , the target layer 140 , the hard mask layer 160 and at least one sacrificial pattern 182 on the substrate 100 , and forming the at least one conductive layer 120 in the substrate 100 .
  • the detailed materials and forming method of the etching stop layer 110 , the conductive layer 120 , the target layer 140 , the hard mask layer 160 and the sacrificial pattern 182 are all similar to those in the aforementioned first embodiment substantially, or are well known in the art and will not be further detailed herein.
  • a blocking pattern 222 is firstly formed on the substrate 100 before the at least one sacrificial pattern 182 is formed. Precisely, in the present embodiment, at least one portion of the hard mask layer 160 is replaced with the blocking pattern 222 .
  • the forming method of the blocking pattern 222 may include firstly removing a portion of the hard mask layer 160 , like a portion of the silicon oxide layer 163 for example, so as to form an opening 164 in the hard mask layer 160 , as shown in FIG. 5 and FIG. 6 . Next, the blocking pattern 222 is formed in the opening 164 , wherein the blocking pattern 222 is level with the hard mask layer 160 (namely the silicon oxide layer 163 ), as shown in FIG.
  • the blocking pattern 222 may include a material having etching selectivity relative to the silicon oxide layer 163 , such as a tungsten containing material or the same material as the metal nitride layer 162 , like tantalum nitride or titanium nitride.
  • the formation of the blocking pattern 222 may include forming a blocking material layer (not shown in the drawings) on the silicon oxide layer 163 , to fill the opening 164 , and performing a planarization process, such as a chemical mechanical polishing (CMP), an etching process or a combination thereof, to level the blocking material layer and the silicon oxide layer 163 for forming the blocking pattern 222 , but is not limited thereto.
  • CMP chemical mechanical polishing
  • the blocking pattern 222 formed therein the opening 164 may also be formed through a selectively deposition process or an oxidation process.
  • At least one self-aligned double-patterning process also known as sidewall image transfer process is performed, to form a plurality of the sacrificial patterns 182 paralleled to each other on the hard mask layer 160 and spacers 202 surrounding the sacrificial patterns 182 , as shown in FIG. 8 and FIG. 9 .
  • each of the sacrificial patterns 182 and each of the spacers 202 surrounding the sacrificial patterns 182 cross above the hard mask layer 160 and the blocking pattern 222 , and overlap at least one of the sacrificial patterns 182 and one spacer 202 surrounding the at least one sacrificial pattern 182 in a projecting direction being perpendicular to the substrate 100 .
  • the blocking pattern 222 may have a length L being greater than a pitch P between the sacrificial patterns 182 , as shown in FIG. 8 .
  • the sacrificial patterns 182 may be completely removed as shown in FIG. 10 , and an etching process, for example a dry etching process, a wet etching or a sequentially performed dry and wet etching process, may be performed then by using the spacers 202 and the blocking pattern 222 underneath as a mask, to transfer patterns of the spacers 202 and the blocking pattern 222 to the hard mask layer 160 underneath.
  • the patterns of the spacers 202 may be firstly transferred to a portion of the hard mask layer 160 , for example, only the silicon oxide layer 163 and the metal nitride layer 162 , but not limited thereto.
  • a portion of the hard mask layer 160 (namely, the silicon oxide layer 163 ) has been replaced with the blocking pattern 222 , so that, while the patterns of the spacers 202 is transferred, the blocking pattern may only be slightly etched due to different etching selectivity, as shown in FIG. 11 .
  • the silicon oxide layer 163 and the metal nitride layer 162 exposed from the spacers 202 may be completely removed, but the blocking patterns 222 exposed from the spacers 202 may only be partially removed, thereby being formed in a battlement-shape shown in FIG. 11 .
  • the metal nitride layer 162 disposed under the blocking pattern 222 may be shelter from the etching, and may not be removed during the etching process, so that, the patterns of the spacers 202 may not be successfully transferred to the metal nitride layer 162 under the blocking pattern 222 . In other words, only a portion of the hard mask layer 160 is patterned.
  • the spacers 202 may be optionally removed or remained, and another etching process, for example a dry etching process, a wet etching or a sequentially performed dry and wet etching process, may be performed by using the patterned hard mask layer 160 as a mask, to form at least one opening 240 in the target layer 140 to connect to the conductive layer 120 underneath and to define at least one fin shaped structure simultaneously, as shown in FIG. 12 .
  • a portion of the hard mask layer 160 for example, the silicon oxide layer 163
  • the spacers 202 are removed, as shown in FIG. 12 .
  • the forming method of the present invention mainly utilizes the blocking pattern 222 to block at least one portion of the patterns of the spacers 202 , so that, the openings 240 paralleledly arranged and spaced from each other may be defined accordingly, as shown in FIG. 13 . Also, a portion of the openings 240 may be divided into two parts due to being blocked by the blocking pattern 222 . In this manner, the fin shaped structures 260 formed between the openings 240 may have a portion being connected with each other, as shown in FIG. 13 . In other words, the fin shaped structures 264 formed below the blocking pattern 222 may cross the fin shaped structures 262 formed below the patterned hard mask layer 160 , so as to form fin shaped structures 262 , 264 which are interlace from each other.
  • the blocking pattern 222 may not be completely removed due to different etching selectivity. Thus, a portion of the blocking pattern 222 still remains on the fin shaped structures 264 , as shown in FIG. 12 . Precisely speaking, only a portion of the patterned hard mask layer 160 (namely, the metal nitride layer 162 and the silicon oxide layer 161 ) remains on the fin shaped structures 262 , and the portion of the patterned hard mask layer 160 may be etched to plural units 160 a disposing on each of the fin shaped structures 262 .
  • the portion of the blocking pattern 222 and a portion of the hard mask layer 160 remain on the fin shaped structures 264 , so that, the fin shaped structures 264 have a relative thicker film remained on top, in comparison with that of the fin shaped structures 262 .
  • a cleaning process may be optionally performed, for example, using argon to clean surfaces of the openings 240 in the target layer 140 (namely, the inter-layer dielectric layer).
  • other semiconductor processes such as a silicidation process or a plug process, may be optionally performed in the subsequent process, to form a semiconductor device (not shown in the drawings) which directly contacts the conductive layer 120 , like a contact plug or a wiring, for example.
  • a dual-gate transistor device (not shown in the drawings) may be formed subsequently, to cross the fin shaped structures 262 , 264 , wherein the dual-gate transistor device may be formed on fin shaped structures 262 , 264 having different thickness of films disposed thereon.
  • the semiconductor device according to the second embodiment of the present invention is obtained.
  • the forming method thereof replaces a portion of the hard mask layer with the blocking pattern, and then forms the sacrificial patterns and the spacers on the hard mask layer, for blocking a portion of the patterns of the spacers.
  • the semiconductor device formed accordingly may obtain specific layout.
  • the blocking pattern of the present embodiment is formed below the spacers, and being defined by an opening pattern, the critical dimension of the blocking pattern may be precisely controlled, substantially being 20 nm to 60 nm for example. According to these, the present invention is able to form blocking patter in a relative smaller dimension, so that, the semiconductor device formed accordingly may obtain further specific layout.
  • FIG. 14 is a schematic diagram illustrating a method of forming a semiconductor device according to the third embodiment of the present invention.
  • the formal steps in the present embodiment are similar to those in the second embodiment shown in FIGS. 5-10 , and the differences between the present embodiment and the aforementioned second embodiment are that, in addition to form the blocking pattern 222 in the opening 164 , a blocking pattern 224 may also be formed on the spacers 202 , after removing the sacrificial patterns 182 .
  • the blocking pattern 224 may cross and cover at least one of the spacers 202 , as shown in FIG. 14 .
  • the blocking patter 224 may not overlap the blocking pattern 222 in a projecting direction being perpendicular to the substrate 100 , but is not limited thereto.
  • the etching process may be performed by simultaneously using the blocking pattern 224 , spacers 202 and the blocking pattern 222 as a mask.
  • the blocking pattern 224 is formed on the hard mask layer 160 and the spacers 202 through the photolithography process, which may obtain a relative greater dimension in comparison with the blocking pattern 222 , for example, being substantially greater than 60 nm, and preferably being between 60 nm to 90 nm, but is not limited thereto.
  • the semiconductor device according to the third embodiment of the present invention is obtained.
  • the forming method thereof mainly forms blocking patterns having different dimensions below and above the spacers respectively, such that, the semiconductor device formed accordingly may obtain specific layout.
  • the present invention enables to form blocking pattern in a ranged dimension, so as to form semiconductor device in further specific layout.

Abstract

A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device being formed through a sidewall image transference process and a method of forming the same.
2. Description of the Prior Art
In recent years, as the continuous decrease of the sizes of semiconductor devices and the increase of the stacking and integration density of semiconductor devices, the photolithography process approaches physical limitation such that the costs of design, process development, and photomask rise dramatically. Therefore, many traditional process and fabrication method cannot meet the fabrication requirement anymore. In current techniques, in order to achieve sub-lithographic features, an immersion photolithography process in corporation with the argon fluoride (ArF) laser tool is performed for further improve the resolution. In addition, the manufacturer also provides self-aligned double-patterning (SADP) process, also known as sidewall image transfer (SIT) technique, to form required microminiature components.
Generally, the sidewall image transfer process includes firstly forming a plurality of sacrificial patterns on a substrate, wherein the dimension of such sacrificial patterns is substantially greater or equal to the critical dimension of photolithography. Then, spacers are formed on sidewalls of the sacrificial patterns through a deposition and an etching process. Since the dimension of the spacers may be smaller than the critical dimension, patterns of the spacers may be transferred into the substrate by using the spacers as mask to form a smaller fin structure. However, as the size of the semiconductor devices shrink, the electrical and physical requirements in each part of the devices become critical, like the dimensions and shapes of the wiring and the transistor and the spacing therebetween for example. Thus, how to achieve standard requirements and overcome the physical limitations has become an important issue in the industry of the semiconductor.
SUMMARY OF THE INVENTION
It is one of the primary objectives of the present invention to provide a semiconductor device and a method of forming the same, which may enable to improve the critical dimension of the device.
To achieve the purpose described above, the present invention provides a semiconductor device including a mask layer and a plurality of spacers. The mask layer is disposed on a target layer and includes a first material and a second material. The spacers are disposed on the mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.
To achieve the purpose described above, the present invention provides a method of forming a semiconductor device, including following steps. First of all, a first pattern is formed on a target layer. Next, a plurality of second patterns is formed on the target layer, wherein at least one of the second patterns crosses the first pattern. Then, a plurality of the spacers is formed to surround the second patterns, wherein the spacers are disposed on the first pattern. Finally, a removing process is performed to remove a portion of the target layer by using the spacers and the first pattern as a mask.
According to the above, the semiconductor device and the forming method thereof in the present invention mainly replaces a portion of the hard mask layer with the blocking pattern, and then forms the sacrificial patterns and the spacers on the hard mask layer, for blocking a portion of the patterns of the spacers. In this way, the semiconductor device formed accordingly may obtain specific layout. Since the blocking pattern of the present embodiment is formed below the spacers, and being defined by an opening pattern, the critical dimension of the blocking pattern may be precisely controlled, substantially being 20 nm to 60 nm for example. According to these, the present invention is able to form blocking patter in relative smaller dimension, so that, the semiconductor device formed accordingly may obtain further specific layout.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 to FIG. 4 are schematic diagrams illustrating a method of forming a semiconductor device according to a first embodiment of the present invention.
FIG. 5 to FIG. 13 are schematic diagrams illustrating a method of forming a semiconductor device according to a second embodiment of the present invention, wherein FIG. 5, FIG. 8, and FIG. 13 show top views of the semiconductor device in forming steps, and FIG. 6 and FIG. 9 show cross-sectional views taken along a cross line A-A′ in FIG. 5 and FIG. 8.
FIG. 14 is a schematic diagram illustrating a method of forming a semiconductor device according to a third embodiment of the present invention.
 DETAILED DESCRIPTION
To provide a better understanding of the present invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.
Please refer to FIG. 1 to FIG. 4, which are schematic diagrams illustrating a method of forming a semiconductor device according to the first embodiment of the present invention. First of all, a substrate 100 is provided. The substrate 100 may include a dielectric material, such as a dielectric layer, as shown in FIG. 1. In one embodiment, the dielectric layer may include a multilayer structure, for example a composite structure consisted of low dielectric constant (low-k) materials (having a dielectric constant less than 3.9), such as silicon oxide, silicon oxynitride and silicon carbonitride, but is not limited thereto. In another embodiment, the substrate 100 may include a semiconductor material, like, a silicon substrate, a silicon-containing substrate or a silicon-on-insulator (SOI) substrate for example, or a non-semiconductor material, like a glass substrate for example. The substrate 100 may include other semiconductor device formed therein or thereon. For example, in the embodiment of having the silicon substrate (not shown in the drawings), at least one metal oxide semiconductor (MOS) transistor (not shown in the drawings) may be formed on the silicon substrate, or at least one dielectric material layer (not shown in the drawings) is formed on the silicon substrate and at least one metal oxide semiconductor transistor (not shown in the drawings) may be formed in the dielectric material layer, but is not limited thereto.
Precisely speaking, at least one conductive layer 120 is formed in the substrate 100, and the conductive layer 120 may include any conductive unit or metal contact, such as a contact plug, via plug or wiring, as shown in FIG. 1. However, People skilled in the art shall easily realize that the conductive layer 120 of the present invention is not limited to the aforementioned types, and in the embodiment of having silicon substrate or other semiconductor substrate (not shown in the drawings), the conductive layer may include a gate electrode (not shown in the drawings) formed on the silicon substrate, or a source/drain region (not shown in the drawings) formed in the silicon substrate.
Next, a target layer 140, a hard mask layer 160 and at least one sacrificial pattern 180 are formed sequentially on the substrate 100. In one embodiment, the target layer 140 may include an inter-layer dielectric (ILD) layer, for example including a low dielectric constant (less than 3.9) material, like silicon oxide, silicon oxynitride or silicon carbonitride for example, but is not limited thereto. In another embodiment, the target layer 140 may also include other suitable materials, such as semiconductor materials, conductive materials or non-conductive materials. The hard mask layer 160 preferable includes a multilayer structure, for example being a composite structure consisted of a silicon oxide layer 161, a metal nitride layer 162 and a silicon oxide layer 163, as shown in FIG. 1, but is not limited thereto. In another embodiment, the hard mask layer 160 may be optionally omitted, so that, a sacrificial pattern (not shown in the drawings) may be formed directly on the target layer 140.
In the present embodiment, the formation of the sacrificial pattern 180 may be integrated into a conventional semiconductor process, for example, a general photolithographic etching pattern (PEP) process or a multi-patterning process may be performed to form a plurality of the sacrificial patterns 180 on the hard mask layer 160. The sacrificial patterns 180 may include polysiliocn or other materials having etching selectivity relative to the hard mask layer 160 underneath, such as silicon oxide or silicon nitride. However, people skilled in the art shall easily realize that the forming method, as well as the materials, of the sacrificial patterns 180 are not limited thereto, and may include other processes or materials which are well known in the art and will not be further detailed herein. Furthermore, in one embodiment, an etching stop layer 110 may be optionally formed on the substrate 100, before the target layer 140 is formed, as shown in FIG. 1.
Then, a plurality of spacers 200 is formed to surround the sacrificial patterns 180, as shown in FIG. 2. Precisely, the forming method of the spacers 200 may includes firstly forming a spacer material layer (not shown in the drawings) on the substrate 100 to cover the sacrificial patterns 180, and performing an etching back process to completely remove the spacer material layer on top surfaces of the sacrificial patterns 180, so as to form the spacers 200 surrounding the sacrificial patterns 180 and adjacent thereto. In one embodiment, the spacers 200 preferably include titanium dioxide (TiO2) or other materials having etching selectivity relative to the sacrificial patterns 180 and the hard mask layer 160, such as tungsten (W), tantalum nitride (TaN) or titanium nitride (TiN), but are not limited thereto.
Following these, the sacrificial patterns 180 are completely removed, and a blocking pattern 220 is formed on the hard mask layer 160 to cross and to cover at least one of the spacer 200. Specifically, a sacrificial layer 400 may be formed previously, before the blocking pattern 220 is formed, and the sacrificial layer 400 may include materials having etching selectivity relative to the hard mask layer 160 and better gap-filling ability, like anti-reflective coating (ARC) materials, polysilicon or oxide materials for example, so as to completely cover the hard mask layer 160 and the spacers 200 formed on the hard mask layer 160. In a preferably embodiment, the sacrificial layer 400 may optionally include a composite structure, for example including a silicon-containing hard mask (SHB) layer 401 and an organic dielectric (ODL) layer 402, as shown in FIG. 3, wherein the organic dielectric layer 402 may be made of 365 nm I-line photoresist material or novolac resin, but is not limited thereto.
After that, an etching process, such as a dry etching process, a wet etching or a sequentially performed dry and wet etching process, is performed by using the spacers 200 and the blocking pattern 220 as a mask, to transfer patterns of the spacers 200 which are not blocked by the blocking pattern 220 to the hard mask layer 160 underneath. In the present embodiment, the patterns of the spacers 200 may be firstly transferred to a portion of the hard mask layer 160, for example, only the silicon oxide layer 163 and the metal nitride layer 162, but not limited thereto. In another embodiment (not shown in the drawings), the patterns of the spacers 200 may also be transferred to the whole hard mask layer 160, optionally. However, it is worth noting that, a portion of the spacers 200 is blocked by the blocking pattern 220, so that, only the patterns of the spacers 200 which are not blocked by the blocking pattern 220 may be successfully transferred to the hard mask layer 160, as shown in FIG. 4.
In the following, after completely removing the blocking pattern 220, the rest of the sacrificial layer 400 and spacers 200, patterns of the hard mask layer 160 may be further transferred to the target layer 140 formed below, thereby forming at least one opening (not shown in the drawings) directly connecting to the conductive layer 120. It is noted that, since the blocking pattern 220 has partially blocked the patterns of the spacers 220 in the aforementioned process, the opening formed according to the spacers 220 may be divided into two parts, or be formed only in particular region. According to these, other semiconductor process, such as a silicidation process or a plug process, may be optionally performed in the subsequent process, to form a semiconductor device (not shown in the drawings), such as a contact plug, a wiring or a transistor, directly contacting to the conductive layer 120, thereby forming the semiconductor device having specific layout in the following processes.
Through the aforementioned processes, the semiconductor device according to the first embodiment of the present invention is obtained. Please note that, the detailed dimensions and relative ratio of the sacrificial pattern, the spacers and the blocking pattern of the present invention are not limited to that shown in FIGS. 1-4, and may be further adjusted according to practical requirements. In the first embodiment of the present invention, the forming method thereof utilizes the blocking pattern to block a portion of the spacers, for partially blocking the patterns of the spacers, such that, the semiconductor device formed accordingly may obtain specific layout. However, due to the critical dimensions of the blocking pattern probably being limited by the photolithography and etching process, optical proximity effects (OPCs) may easily occur in the photolithographic process during the formation of the blocking pattern especially while the size of semiconductor device has shrunk to a particular degree, thereby causing overexposure or underexposure to the blocking patterns which may not meet the practical requirements of the processes. Thus, in some cases, the dimension of the blocking pattern may not be properly controlled, so that, the deformed or dislocated blocking patterns may be formed accordingly, damaging to the expected layout, and even affecting the performance of the semiconductor device.
The following description will detail the different embodiments of the semiconductor device and the forming method thereof of the present invention. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.
Please refer to FIG. 5 to FIG. 13, which are schematic diagrams illustrating a method of forming a semiconductor device according to the second embodiment of the present invention, wherein FIG. 5, FIG. 8, and FIG. 13 show the top views of the semiconductor device in forming steps, and FIG. 6 and FIG. 9 show the cross-sectional views taken along the cross line A-A′ in FIG. 5 and FIG. 8. The formal steps in the present embodiment are similar to those in the first embodiment, which include sequentially forming the etching stop layer 110, the target layer 140, the hard mask layer 160 and at least one sacrificial pattern 182 on the substrate 100, and forming the at least one conductive layer 120 in the substrate 100. Also, it is noted that, the detailed materials and forming method of the etching stop layer 110, the conductive layer 120, the target layer 140, the hard mask layer 160 and the sacrificial pattern 182 are all similar to those in the aforementioned first embodiment substantially, or are well known in the art and will not be further detailed herein.
The differences between the present embodiment and the aforementioned first embodiment are that, a blocking pattern 222 is firstly formed on the substrate 100 before the at least one sacrificial pattern 182 is formed. Precisely, in the present embodiment, at least one portion of the hard mask layer 160 is replaced with the blocking pattern 222. The forming method of the blocking pattern 222 may include firstly removing a portion of the hard mask layer 160, like a portion of the silicon oxide layer 163 for example, so as to form an opening 164 in the hard mask layer 160, as shown in FIG. 5 and FIG. 6. Next, the blocking pattern 222 is formed in the opening 164, wherein the blocking pattern 222 is level with the hard mask layer 160 (namely the silicon oxide layer 163), as shown in FIG. 7. In one embodiment, the blocking pattern 222 may include a material having etching selectivity relative to the silicon oxide layer 163, such as a tungsten containing material or the same material as the metal nitride layer 162, like tantalum nitride or titanium nitride. Specifically, the formation of the blocking pattern 222 may include forming a blocking material layer (not shown in the drawings) on the silicon oxide layer 163, to fill the opening 164, and performing a planarization process, such as a chemical mechanical polishing (CMP), an etching process or a combination thereof, to level the blocking material layer and the silicon oxide layer 163 for forming the blocking pattern 222, but is not limited thereto. In another embodiment, according to the material exposed from the opening 164, like the characterization of the metal nitride layer 164 for example, the blocking pattern 222 formed therein the opening 164 may also be formed through a selectively deposition process or an oxidation process.
Then, similar to the processes shown in FIGS. 1-2 of the aforementioned first embodiment, at least one self-aligned double-patterning process, also known as sidewall image transfer process is performed, to form a plurality of the sacrificial patterns 182 paralleled to each other on the hard mask layer 160 and spacers 202 surrounding the sacrificial patterns 182, as shown in FIG. 8 and FIG. 9. Please note that, each of the sacrificial patterns 182 and each of the spacers 202 surrounding the sacrificial patterns 182 cross above the hard mask layer 160 and the blocking pattern 222, and overlap at least one of the sacrificial patterns 182 and one spacer 202 surrounding the at least one sacrificial pattern 182 in a projecting direction being perpendicular to the substrate 100. Also, in one embodiment, the blocking pattern 222 may have a length L being greater than a pitch P between the sacrificial patterns 182, as shown in FIG. 8.
Following these, the sacrificial patterns 182 may be completely removed as shown in FIG. 10, and an etching process, for example a dry etching process, a wet etching or a sequentially performed dry and wet etching process, may be performed then by using the spacers 202 and the blocking pattern 222 underneath as a mask, to transfer patterns of the spacers 202 and the blocking pattern 222 to the hard mask layer 160 underneath. In the present embodiment, the patterns of the spacers 202 may be firstly transferred to a portion of the hard mask layer 160, for example, only the silicon oxide layer 163 and the metal nitride layer 162, but not limited thereto. It is worth noting that, a portion of the hard mask layer 160 (namely, the silicon oxide layer 163) has been replaced with the blocking pattern 222, so that, while the patterns of the spacers 202 is transferred, the blocking pattern may only be slightly etched due to different etching selectivity, as shown in FIG. 11. In other words, while the etching process is performed, the silicon oxide layer 163 and the metal nitride layer 162 exposed from the spacers 202 may be completely removed, but the blocking patterns 222 exposed from the spacers 202 may only be partially removed, thereby being formed in a battlement-shape shown in FIG. 11. Meanwhile, the metal nitride layer 162 disposed under the blocking pattern 222 may be shelter from the etching, and may not be removed during the etching process, so that, the patterns of the spacers 202 may not be successfully transferred to the metal nitride layer 162 under the blocking pattern 222. In other words, only a portion of the hard mask layer 160 is patterned.
After that, the spacers 202 may be optionally removed or remained, and another etching process, for example a dry etching process, a wet etching or a sequentially performed dry and wet etching process, may be performed by using the patterned hard mask layer 160 as a mask, to form at least one opening 240 in the target layer 140 to connect to the conductive layer 120 underneath and to define at least one fin shaped structure simultaneously, as shown in FIG. 12. It is noted that, in the embodiment of completely removing the spacers 202 before the etching process, a portion of the hard mask layer 160 (for example, the silicon oxide layer 163) may also be optionally removed while the spacers 202 are removed, as shown in FIG. 12.
In addition, it is worth noting that, the forming method of the present invention mainly utilizes the blocking pattern 222 to block at least one portion of the patterns of the spacers 202, so that, the openings 240 paralleledly arranged and spaced from each other may be defined accordingly, as shown in FIG. 13. Also, a portion of the openings 240 may be divided into two parts due to being blocked by the blocking pattern 222. In this manner, the fin shaped structures 260 formed between the openings 240 may have a portion being connected with each other, as shown in FIG. 13. In other words, the fin shaped structures 264 formed below the blocking pattern 222 may cross the fin shaped structures 262 formed below the patterned hard mask layer 160, so as to form fin shaped structures 262, 264 which are interlace from each other.
It is also worth noting that, while removing the rest spacers 202 and the hard mask layer 160, the blocking pattern 222 may not be completely removed due to different etching selectivity. Thus, a portion of the blocking pattern 222 still remains on the fin shaped structures 264, as shown in FIG. 12. Precisely speaking, only a portion of the patterned hard mask layer 160 (namely, the metal nitride layer 162 and the silicon oxide layer 161) remains on the fin shaped structures 262, and the portion of the patterned hard mask layer 160 may be etched to plural units 160 a disposing on each of the fin shaped structures 262. On the other hands, the portion of the blocking pattern 222 and a portion of the hard mask layer 160 (namely, the metal nitride layer 162 and the silicon oxide layer 161) remain on the fin shaped structures 264, so that, the fin shaped structures 264 have a relative thicker film remained on top, in comparison with that of the fin shaped structures 262.
Finally, a cleaning process may be optionally performed, for example, using argon to clean surfaces of the openings 240 in the target layer 140 (namely, the inter-layer dielectric layer). After that, other semiconductor processes, such as a silicidation process or a plug process, may be optionally performed in the subsequent process, to form a semiconductor device (not shown in the drawings) which directly contacts the conductive layer 120, like a contact plug or a wiring, for example. Please note that, in the embodiment of having the target layer 140 of the semiconductor material, a dual-gate transistor device (not shown in the drawings) may be formed subsequently, to cross the fin shaped structures 262, 264, wherein the dual-gate transistor device may be formed on fin shaped structures 262, 264 having different thickness of films disposed thereon.
Through the aforementioned processes, the semiconductor device according to the second embodiment of the present invention is obtained. In the second embodiment of the present invention, the forming method thereof replaces a portion of the hard mask layer with the blocking pattern, and then forms the sacrificial patterns and the spacers on the hard mask layer, for blocking a portion of the patterns of the spacers. Thus, the semiconductor device formed accordingly may obtain specific layout. Since the blocking pattern of the present embodiment is formed below the spacers, and being defined by an opening pattern, the critical dimension of the blocking pattern may be precisely controlled, substantially being 20 nm to 60 nm for example. According to these, the present invention is able to form blocking patter in a relative smaller dimension, so that, the semiconductor device formed accordingly may obtain further specific layout.
Please refer to FIG. 14, which is a schematic diagram illustrating a method of forming a semiconductor device according to the third embodiment of the present invention. The formal steps in the present embodiment are similar to those in the second embodiment shown in FIGS. 5-10, and the differences between the present embodiment and the aforementioned second embodiment are that, in addition to form the blocking pattern 222 in the opening 164, a blocking pattern 224 may also be formed on the spacers 202, after removing the sacrificial patterns 182. The blocking pattern 224 may cross and cover at least one of the spacers 202, as shown in FIG. 14. Also, in a preferred embodiment, the blocking patter 224 may not overlap the blocking pattern 222 in a projecting direction being perpendicular to the substrate 100, but is not limited thereto. With such arrangement, in the subsequent etching process (not shown in the drawings), the etching process may be performed by simultaneously using the blocking pattern 224, spacers 202 and the blocking pattern 222 as a mask. Also, please note that, since the blocking pattern 224 is formed on the hard mask layer 160 and the spacers 202 through the photolithography process, which may obtain a relative greater dimension in comparison with the blocking pattern 222, for example, being substantially greater than 60 nm, and preferably being between 60 nm to 90 nm, but is not limited thereto.
Through the aforementioned processes, the semiconductor device according to the third embodiment of the present invention is obtained. In the third embodiment of the present invention, the forming method thereof mainly forms blocking patterns having different dimensions below and above the spacers respectively, such that, the semiconductor device formed accordingly may obtain specific layout. In this manner, the present invention enables to form blocking pattern in a ranged dimension, so as to form semiconductor device in further specific layout.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (15)

What is claimed is:
1. A method of forming a semiconductor device, comprising:
forming a first pattern on a target layer;
forming a plurality of second patterns on the target layer, wherein a portion of the second patterns crosses the first pattern, and another portion of the second patterns does not cross the first pattern;
forming a plurality of the spacers surrounding the second patterns, and disposed on the first pattern; and
performing a removing process to remove a portion of the target layer by using the spacers and the first pattern as a mask.
2. The method of forming the semiconductor device according to claim 1, wherein the first pattern overlaps at least one of the second patterns in a projecting direction.
3. The method of forming the semiconductor device according to claim 1, further comprising:
forming a hard mask layer on the target layer; and
replacing a portion of the hard mask layer with the first pattern.
4. The method of forming the semiconductor device according to claim 3, wherein the first pattern comprises tungsten, tantalum nitride, or titanium nitride.
5. The method of forming the semiconductor device according to claim 3, wherein the first pattern is level with the hard mask layer.
6. The method of forming the semiconductor device according to claim 1, wherein the first pattern has a dimension of about 20 nm to 60 nm.
7. The method of forming the semiconductor device according to claim 1, further comprising:
removing the second patterns before the removing process.
8. The method of forming the semiconductor device according to claim 7, after removing the second patterns further comprising:
forming a third pattern on the spacers, wherein the third pattern covers and crosses at least one of the spacers.
9. The method of forming the semiconductor device according to claim 8, wherein the third pattern has a dimension of about 60 nm to 90 nm.
10. The method of forming the semiconductor device according to claim 8, wherein the third pattern does not overlap the first pattern in a projecting direction.
11. The method of forming the semiconductor device according to claim 8, wherein in the removing process, the portion of the target layer is removed by using the third pattern, the spacers and the first pattern as a mask.
12. The method of forming the semiconductor device according to claim 1, wherein the target layer comprises semiconductor material, conductive material or non-conductive material.
13. The method of forming the semiconductor device according to claim 1, wherein in the removing process further comprises:
forming a plurality of openings paralleled to each other in the target layer, and a plurality of fin shaped structures between the openings.
14. The method of forming the semiconductor device according to claim 13, wherein the first pattern is disposed on one of the fin shaped structures.
15. The method of forming the semiconductor device according to claim 1, wherein the spacers comprise tungsten, tantalum nitride, titanium nitride, titanium dioxide or titanium dioxide.
US14/829,649 2015-07-22 2015-08-19 Method of fabricating semiconductor device Active US9583594B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/401,086 US20170117150A1 (en) 2015-07-22 2017-01-08 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201510432534.6 2015-07-22
CN201510432534 2015-07-22
CN201510432534.6A CN106373880B (en) 2015-07-22 2015-07-22 Semiconductor device and method for forming the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/401,086 Division US20170117150A1 (en) 2015-07-22 2017-01-08 Semiconductor device

Publications (2)

Publication Number Publication Date
US20170025519A1 US20170025519A1 (en) 2017-01-26
US9583594B2 true US9583594B2 (en) 2017-02-28

Family

ID=57837871

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/829,649 Active US9583594B2 (en) 2015-07-22 2015-08-19 Method of fabricating semiconductor device
US15/401,086 Abandoned US20170117150A1 (en) 2015-07-22 2017-01-08 Semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/401,086 Abandoned US20170117150A1 (en) 2015-07-22 2017-01-08 Semiconductor device

Country Status (2)

Country Link
US (2) US9583594B2 (en)
CN (1) CN106373880B (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US9892917B2 (en) * 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
US8637411B2 (en) 2010-04-15 2014-01-28 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
SG2013083654A (en) 2012-11-08 2014-06-27 Novellus Systems Inc Methods for depositing films on sensitive substrates
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US10566187B2 (en) 2015-03-20 2020-02-18 Lam Research Corporation Ultrathin atomic layer deposition film accuracy thickness control
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
CN107731737B (en) * 2016-08-12 2020-06-09 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
US10217633B2 (en) * 2017-03-13 2019-02-26 Globalfoundries Inc. Substantially defect-free polysilicon gate arrays
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
CN111564364B (en) * 2018-03-23 2023-05-02 联华电子股份有限公司 Patterning method
CN112768351B (en) * 2019-11-06 2022-06-10 长鑫存储技术有限公司 Pattern forming method
CN113948462B (en) * 2020-07-17 2024-03-19 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013680A (en) 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5102815A (en) * 1990-12-19 1992-04-07 Intel Corporation Method of fabricating a composite inverse T-gate metal oxide semiconductor device
US5429988A (en) 1994-06-13 1995-07-04 United Microelectronics Corporation Process for producing high density conductive lines
US20050282318A1 (en) * 2004-06-18 2005-12-22 Dao Thuy B Method of forming a transistor with a bottom gate
US20060194378A1 (en) * 2004-11-05 2006-08-31 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US20070117310A1 (en) * 2005-03-15 2007-05-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US20070249103A1 (en) * 2006-04-19 2007-10-25 Dao Thuy B Method of making a multi-gate device
US20120329268A1 (en) * 2011-03-28 2012-12-27 Ibm Corporation Method of making a semiconductor device
US8901016B2 (en) 2010-12-28 2014-12-02 Asm Japan K.K. Method of forming metal oxide hardmask
US20150096958A1 (en) * 2013-10-07 2015-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Forming Multiple Patterning Spacer Structures

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6150261A (en) * 1999-05-25 2000-11-21 United Microelectronics Corp. Method of fabricating semiconductor device for preventing antenna effect
US6191001B1 (en) * 1999-08-25 2001-02-20 Lucent Technologies, Inc. Shallow trench isolation method
KR100476924B1 (en) * 2002-06-14 2005-03-17 삼성전자주식회사 Method Of Forming Fine Pattern Of Semiconductor Device
US6893938B2 (en) * 2003-04-21 2005-05-17 Infineon Technologies Ag STI formation for vertical and planar transistors
US7429536B2 (en) * 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7709275B2 (en) * 2008-04-10 2010-05-04 United Microelectronics Corp. Method of forming a pattern for a semiconductor device and method of forming the related MOS transistor
KR101515907B1 (en) * 2008-10-23 2015-04-29 삼성전자주식회사 Method of forming patterns of semiconductor device
KR101093905B1 (en) * 2010-08-04 2011-12-13 주식회사 하이닉스반도체 Method of manufacturing fine patterns
FR2968122B1 (en) * 2010-11-30 2012-12-07 Commissariat Energie Atomique IMPROVED PATTERN REALIZATION METHOD FROM LATERAL SPACER TRANSFER
CN103594337B (en) * 2012-08-14 2016-05-25 中芯国际集成电路制造(上海)有限公司 Double-patterning method
US9613850B2 (en) * 2014-12-19 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lithographic technique for feature cut by line-end shrink

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013680A (en) 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5102815A (en) * 1990-12-19 1992-04-07 Intel Corporation Method of fabricating a composite inverse T-gate metal oxide semiconductor device
US5429988A (en) 1994-06-13 1995-07-04 United Microelectronics Corporation Process for producing high density conductive lines
US20050282318A1 (en) * 2004-06-18 2005-12-22 Dao Thuy B Method of forming a transistor with a bottom gate
US20060194378A1 (en) * 2004-11-05 2006-08-31 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US20070117310A1 (en) * 2005-03-15 2007-05-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US20070249103A1 (en) * 2006-04-19 2007-10-25 Dao Thuy B Method of making a multi-gate device
US8901016B2 (en) 2010-12-28 2014-12-02 Asm Japan K.K. Method of forming metal oxide hardmask
US20120329268A1 (en) * 2011-03-28 2012-12-27 Ibm Corporation Method of making a semiconductor device
US20150096958A1 (en) * 2013-10-07 2015-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Forming Multiple Patterning Spacer Structures

Also Published As

Publication number Publication date
US20170117150A1 (en) 2017-04-27
US20170025519A1 (en) 2017-01-26
CN106373880B (en) 2021-05-25
CN106373880A (en) 2017-02-01

Similar Documents

Publication Publication Date Title
US9583594B2 (en) Method of fabricating semiconductor device
TWI596766B (en) Semiconductor device and manufacturing method thereof
CN109904120B (en) Semiconductor device and method for manufacturing the same
US9034762B2 (en) Triple patterning method
US10170307B1 (en) Method for patterning semiconductor device using masking layer
US10410913B2 (en) Multi-layer metal contacts
JP6903114B2 (en) Manufacturing method of semiconductor devices
TWI628746B (en) Semiconductor structure and fabricating method thereof
KR102128515B1 (en) Method of removing an etch mask
US10699943B2 (en) Method of forming contacts in a semiconductor device
US9564371B2 (en) Method for forming semiconductor device
US8304175B2 (en) Patterning method
US20140342553A1 (en) Method for Forming Semiconductor Structure Having Opening
US20200098578A1 (en) Extreme ultraviolet lithography patterning with directional deposition
TWI579899B (en) A method of making semiconductor device
US11121026B2 (en) Semiconductor device and method of manufacture
CN110931354B (en) Semiconductor structure and method for manufacturing semiconductor structure
US9748139B1 (en) Method of fabricating dual damascene structure
US9779942B1 (en) Method of forming patterned mask layer
US10685871B2 (en) Method for forming semiconductor structure
JP6272949B2 (en) Pattern formation method
US9653345B1 (en) Method of fabricating semiconductor structure with improved critical dimension control
US10103019B1 (en) Manufacturing method for forming a semiconductor structure
CN112447708A (en) Structure and method for improved fin critical dimension control
US10170310B1 (en) Method of forming patterned structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIAO, DUAN QUAN;CHEN, YIKUN;TEY, CHING HWA;REEL/FRAME:036353/0374

Effective date: 20150814

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4