USH368H - Field-effect transistor - Google Patents

Field-effect transistor Download PDF

Info

Publication number
USH368H
USH368H US06/187,672 US18767280A USH368H US H368 H USH368 H US H368H US 18767280 A US18767280 A US 18767280A US H368 H USH368 H US H368H
Authority
US
United States
Prior art keywords
source
effect transistor
active region
concentration
schottky barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US06/187,672
Inventor
Max N. Yoder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Department of Navy
Original Assignee
US Department of Navy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by US Department of Navy filed Critical US Department of Navy
Priority to US06/187,672 priority Critical patent/USH368H/en
Assigned to NAVY, THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE reassignment NAVY, THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: YODER MAX N.
Application granted granted Critical
Publication of USH368H publication Critical patent/USH368H/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes

Definitions

  • This invention relates to an improved field-effect transistor (FET) and especially to improvement of FET's by tailoring the source-gate channel resistivity to be high in the upper layer and lower in the lower layer.
  • FET field-effect transistor
  • Transconductance, gate capacitance, source parasitics, and source-gate channel resistance are the factors universally known to affect the performance of field-effect transistors. Previous work in the field has done much to improve transconductance by improving materials' quality and materials' interfaces. Gate capacitance has been reduced by using submicrometer resolution lithography. Source parasitics have been greatly reduced by better metallization for ohmic contacts by "via" technology and by monolithic, Class B, push-pull circuit techniques. Only source-gate channel resistance has evaded a solution enabling it to be reduced without adversely affecting gate leakage characteristics.
  • Another object is to raise the resistivity of a shallow layer of the source-gate channel in an FET, which layer is in contact with the Schottky-barrier portion of the gate, without increasing the resistivity of the remainder of the source-gate channel.
  • the above and other objects of the invention are accomplished in a GaAs FET by selectively bombarding the N+ doped source-gate channel region with boron ions to raise the resistivity of a shallow upper layer of the channel which is in contact with the Schottky-barrier film of the gate without increasing the resistivity of the underlying channel region.
  • the technique makes use of the virtual non-existence of ionicity in the boron-arsenide bond to induce arsenic vacancies within the crystal which may, in part, be filled with column IV acceptors (e.g., silicon) with the result that deep-level compensating centers are formed (probably by silicon-silicon complexes) thereby transforming the material so treated into semi-insulating material.
  • FIG. 1 is a schematic illustration of a prior-art FET made by an epitaxial growth technique.
  • FIG. 2. is a schematic illustration of a prior-art FET made by an ion implantation technique.
  • FIG. 3 is a schematic illustration of an embodiment of the present invention.
  • FIGS. 1 and 2 illustrate the construction of typical priorart FET's.
  • the FET of FIG. 1 is produced by the growth of epitaxial layers 12 and 14 on a semi-insulating GaAs substrate 10.
  • Layer 14 has a higher concentration of donor impurity ions (approximatel 1 ⁇ 10 17 /cm 3 ) than lower layer 12 and therefore has higher conductivity.
  • the active layer 14 in FIG. 2 is produced by implantation of donor ions.
  • the device also includes a source 16, a drain 18 and a gate 20. In both cases, the active channel, which may, for example, be about 0.5 microns deep, is uniformly doped in the horizontal direction (i.e., along the direction of charge-carrier movement).
  • the source-gate channel region 28, including a top portion 26 and a bottom portion 26', between source 16 and gate 20 (Schottky barrier gate) should be of much lower resistivity than a region 24 lying beneath the gate 20 and between the gate 20 and the drain 18. If the source-gate channel region 28 is heavily doped, however, the leakage of the Schottky barrier gate 20 is excessive. Techniques to create a vertical gradient of resistivity in this region have thus far been unsuccessful since there has been no ion implantation technology capable of reproducibly creating such a gradient.
  • the ideal characteristic is one in which the electrically active impurity concentration at the top portion 26 of the source-gate channel region 28 is less than or equal to that of the region 24 directly beneath the gate 20, while the electrically active impurity concentration in the lower portion 26' of the source-gate channel region 28 is at least an order of magnitude greater than the impurity concentration in the same region 24 directly beneath the gate 20.
  • an impurity ion is selected (e.g., Si, or Si and S) and selectively implanted into the source-gate channel region 28. This may be done simultaneously with the N+ selective source and drain implants in regions 22 and 30, respectively. (In this context, the term "selectively" applies to the particular region selected for any ion implantation.) As shown, the region 24 is implanted only to the N state, or a concentration of about 1 ⁇ 10 17 /cm 3 .
  • the other regions 22, 28 and 30, as aforementioned, are implanted to the N+ state, or a concentration of about 1 ⁇ 10 18 /cm 3 .
  • These implants are then followed by a much shallower (i.e., done with a lower implantation voltage) implant (e.g., 200-500 ⁇ ) of boron into the top portion 26 of source-gate channel region 28.
  • a much shallower implant e.g., 200-500 ⁇
  • the concentration of the boron implant should exceed the concentration of the N+ impurity by a factor of 2 or more to ensure that some As vacancies remain in the top portion 26 after other As vacancies are filled by the acceptor (silican) ions previously implanted.
  • the maximum concentration of boron should be below that which would cause the GaAs to become amorphous; thus, the concentration should not be more than about 5 ⁇ 10 19 /cm 3 .
  • Activation/annealing of the implanted ions may then proceed in a conventional manner chosen by the fabricator (i.e., thermal, laser and/or electron beam).
  • the annealing ambient must be chosen so that the boron-implanted region, i.e., top portion 26, is not etched away in the process (e.g., use flowing arsine, proximity capping or a good silicon nitride encapsulant).

Abstract

A method of improving field-effect transistors, and the product thereof, wherein the resistivity of the upper layer of the source-gate channel region of a GaAs field-effect transistor (FET) may be selectively raised is disclosed. Impurity ions are implanted in the source-gate channel region followed by a much shallower implantation of boron in the same region. The boron ion concentration should exceed the N+ impurity ion concentration by a factor of 2 or more.

Description

BACKGROUND OF THE INVENTION
This invention relates to an improved field-effect transistor (FET) and especially to improvement of FET's by tailoring the source-gate channel resistivity to be high in the upper layer and lower in the lower layer.
Transconductance, gate capacitance, source parasitics, and source-gate channel resistance are the factors universally known to affect the performance of field-effect transistors. Previous work in the field has done much to improve transconductance by improving materials' quality and materials' interfaces. Gate capacitance has been reduced by using submicrometer resolution lithography. Source parasitics have been greatly reduced by better metallization for ohmic contacts by "via" technology and by monolithic, Class B, push-pull circuit techniques. Only source-gate channel resistance has evaded a solution enabling it to be reduced without adversely affecting gate leakage characteristics.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to reduce the source-gate channel resistance in an FET without adversely affecting the gate leakage characteristic.
Another object is to raise the resistivity of a shallow layer of the source-gate channel in an FET, which layer is in contact with the Schottky-barrier portion of the gate, without increasing the resistivity of the remainder of the source-gate channel.
The above and other objects of the invention are accomplished in a GaAs FET by selectively bombarding the N+ doped source-gate channel region with boron ions to raise the resistivity of a shallow upper layer of the channel which is in contact with the Schottky-barrier film of the gate without increasing the resistivity of the underlying channel region. The technique makes use of the virtual non-existence of ionicity in the boron-arsenide bond to induce arsenic vacancies within the crystal which may, in part, be filled with column IV acceptors (e.g., silicon) with the result that deep-level compensating centers are formed (probably by silicon-silicon complexes) thereby transforming the material so treated into semi-insulating material.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic illustration of a prior-art FET made by an epitaxial growth technique.
FIG. 2. is a schematic illustration of a prior-art FET made by an ion implantation technique.
FIG. 3 is a schematic illustration of an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1 and 2 illustrate the construction of typical priorart FET's. The FET of FIG. 1 is produced by the growth of epitaxial layers 12 and 14 on a semi-insulating GaAs substrate 10. Layer 14 has a higher concentration of donor impurity ions (approximatel 1×1017 /cm3) than lower layer 12 and therefore has higher conductivity. The active layer 14 in FIG. 2 is produced by implantation of donor ions. The device also includes a source 16, a drain 18 and a gate 20. In both cases, the active channel, which may, for example, be about 0.5 microns deep, is uniformly doped in the horizontal direction (i.e., along the direction of charge-carrier movement).
Referring now to FIG. 3, the source-gate channel region 28, including a top portion 26 and a bottom portion 26', between source 16 and gate 20 (Schottky barrier gate) should be of much lower resistivity than a region 24 lying beneath the gate 20 and between the gate 20 and the drain 18. If the source-gate channel region 28 is heavily doped, however, the leakage of the Schottky barrier gate 20 is excessive. Techniques to create a vertical gradient of resistivity in this region have thus far been unsuccessful since there has been no ion implantation technology capable of reproducibly creating such a gradient. The ideal characteristic is one in which the electrically active impurity concentration at the top portion 26 of the source-gate channel region 28 is less than or equal to that of the region 24 directly beneath the gate 20, while the electrically active impurity concentration in the lower portion 26' of the source-gate channel region 28 is at least an order of magnitude greater than the impurity concentration in the same region 24 directly beneath the gate 20. The achievement of such an impurity gradient profile virtually eliminates the source-gate channel resistance as a significant factor adversely affecting FET performance and the gradient does not adversely affect the characteristics of the Schottky-barrier gate 20.
To achieve this optimum gradient profile in the source-gate channel region 28 without adversely changing the impurity profile elsewhere requires a new approach based on an understanding of how impurity complexes can be used to reproducibly and reliably control the properties of semiconductors. The implantation of boron is known to render GaAs semi-insulating since it compensates, or neutralizes, other impurities which render the GaAs more conductive. Thus the effect of the boron is to render the doped GaAs more insulative. Only recently has it been found that the boron implant dose need not be excessive to the extent of rendering the semiconductor amorphous but, instead, need only exceed the concentration of other impurities within the GaAs. More recently, it has been shown that boron implanted in GaAs does not diffuse within the GaAs at elevated temperatures as do most other impurities.
Still referring to FIG. 3, to the optimum gradient profile in the source-gate channel region 28 of the improved ion-implanted FET shown, an impurity ion is selected (e.g., Si, or Si and S) and selectively implanted into the source-gate channel region 28. This may be done simultaneously with the N+ selective source and drain implants in regions 22 and 30, respectively. (In this context, the term "selectively" applies to the particular region selected for any ion implantation.) As shown, the region 24 is implanted only to the N state, or a concentration of about 1×1017 /cm3. However, the other regions 22, 28 and 30, as aforementioned, are implanted to the N+ state, or a concentration of about 1×1018 /cm3. These implants are then followed by a much shallower (i.e., done with a lower implantation voltage) implant (e.g., 200-500 Å) of boron into the top portion 26 of source-gate channel region 28. By so doing, As vacancies are created in the top portion 26 but not in the bottom portion 26' of the source-gate channel region 28. The concentration of the boron implant should exceed the concentration of the N+ impurity by a factor of 2 or more to ensure that some As vacancies remain in the top portion 26 after other As vacancies are filled by the acceptor (silican) ions previously implanted. The maximum concentration of boron should be below that which would cause the GaAs to become amorphous; thus, the concentration should not be more than about 5×1019 /cm3.
Activation/annealing of the implanted ions may then proceed in a conventional manner chosen by the fabricator (i.e., thermal, laser and/or electron beam). The annealing ambient must be chosen so that the boron-implanted region, i.e., top portion 26, is not etched away in the process (e.g., use flowing arsine, proximity capping or a good silicon nitride encapsulant).
Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the invention can be practiced otherwise than as specifically described.

Claims (5)

What is claimed is:
1. An improved field-effect transistor of the type having a semi-insulating GsAs substrate, an active layer ion implanted into said semi-insulating GaAs substrate, a source fashioned on one end of said semi-insulating GaAs substrate, a drain fashioned on the other end thereof and a Schottky barrier gate fashioned therebetween, said source, said drain and said Schottky barrier gate being fashioned contiguous to the top of said active layer so as to define a first active region underlying said source, a second active region lying between said source and said Schottky barrier gate, a third active region having a portion underlying said Schottky barrier gate and a portion lying between said Schottky barrier gate and said drain, and a fourth active region underlying said drain, wherein the improvement comprises:
selectively implanting said semi-insulating GaAs substrate with impurity ions to the N+ state to form said first, second and fourth active regions, and implanting said semi-insulating GaAs substrate with said impurity ions to the N state to form said third active region; and
selectively implanting a top portion of said second active region to a predetermined depth with a predetermined concentration of boron ions so as to raise the resistivity of said top portion thereof, said top portion extending from said source to said Schottky barrier gate.
2. The improved field-effect transistor of claim 1 wherein the N state corresponds to a concentration of approximately 1×1017 /cm3 and the N+ state corresponds to a concentration of approximately 1×1018 /cm3.
3. The improved field-effect transistor of claim 2 wherein the predetermined concentration of boron ions is at least two times the concentration of the N+ state but less than that which cause said top portion of said second active region to become amorphous.
4. The improved field-effect transistor of claim 3 wherein the predetermined depth of said top portion is in the range of 200-500 Å.
5. The improved field-effect transistor of claim 4 wherein said impurity ions are selected from the group consisting of Si and a mixture of Si and S.
US06/187,672 1980-09-16 1980-09-16 Field-effect transistor Abandoned USH368H (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US06/187,672 USH368H (en) 1980-09-16 1980-09-16 Field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/187,672 USH368H (en) 1980-09-16 1980-09-16 Field-effect transistor

Publications (1)

Publication Number Publication Date
USH368H true USH368H (en) 1987-11-03

Family

ID=22689965

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/187,672 Abandoned USH368H (en) 1980-09-16 1980-09-16 Field-effect transistor

Country Status (1)

Country Link
US (1) USH368H (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019875A (en) * 1988-09-29 1991-05-28 Sumitomo Electric Industries, Ltd. Semiconductor device radiation hardened MESFET
US5087950A (en) * 1990-02-26 1992-02-11 Nec Corporation Schottky barrier junction gate field effect transistor
US20080272409A1 (en) * 2007-05-03 2008-11-06 Dsm Solutions, Inc.; JFET Having a Step Channel Doping Profile and Method of Fabrication
WO2011068663A1 (en) 2009-12-04 2011-06-09 Exxonmobil Research And Engineering Company Method for increasing color quality and stability of fuel field of the invention
US20130026541A1 (en) * 2011-07-25 2013-01-31 Renesas Electronics Corporation Semiconductor integrated circuit device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3804681A (en) 1967-04-18 1974-04-16 Ibm Method for making a schottky-barrier field effect transistor
US3997908A (en) 1974-03-29 1976-12-14 Siemens Aktiengesellschaft Schottky gate field effect transistor
US4196439A (en) 1978-07-03 1980-04-01 Bell Telephone Laboratories, Incorporated Semiconductor device drain contact configuration
US4244097A (en) 1979-03-15 1981-01-13 Hughes Aircraft Company Schottky-gate field-effect transistor and fabrication process therefor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3804681A (en) 1967-04-18 1974-04-16 Ibm Method for making a schottky-barrier field effect transistor
US3997908A (en) 1974-03-29 1976-12-14 Siemens Aktiengesellschaft Schottky gate field effect transistor
US4196439A (en) 1978-07-03 1980-04-01 Bell Telephone Laboratories, Incorporated Semiconductor device drain contact configuration
US4244097A (en) 1979-03-15 1981-01-13 Hughes Aircraft Company Schottky-gate field-effect transistor and fabrication process therefor

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Das et al, IEEE Trans. on Electron Devices, vol. ED24, No. 6, Jun. 1977, pp. 757-761.
Kung et al, Electronics Letters, vol. 13, No. 7, 31 Mar. 1977, pp. 187-188.
Rao et al, "Ion Implantation in Semiconductors", (Plenum Press, 1976, pp. -88.

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019875A (en) * 1988-09-29 1991-05-28 Sumitomo Electric Industries, Ltd. Semiconductor device radiation hardened MESFET
US5087950A (en) * 1990-02-26 1992-02-11 Nec Corporation Schottky barrier junction gate field effect transistor
US20080272409A1 (en) * 2007-05-03 2008-11-06 Dsm Solutions, Inc.; JFET Having a Step Channel Doping Profile and Method of Fabrication
WO2008137293A1 (en) * 2007-05-03 2008-11-13 Dsm Solutions, Inc. A jfet having a step channel doping profile and method of fabrication
US20090137088A1 (en) * 2007-05-03 2009-05-28 Dsm Solutions, Inc. JFET Having a Step Channel Doping Profile and Method of Fabrication
WO2011068663A1 (en) 2009-12-04 2011-06-09 Exxonmobil Research And Engineering Company Method for increasing color quality and stability of fuel field of the invention
US20130026541A1 (en) * 2011-07-25 2013-01-31 Renesas Electronics Corporation Semiconductor integrated circuit device
US9362268B2 (en) * 2011-07-25 2016-06-07 Renesas Electronics Corporation Semiconductor integrated circuit device with transistor and non-transistor regions

Similar Documents

Publication Publication Date Title
US5792679A (en) Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant
US5599724A (en) FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same
US7061058B2 (en) Forming a retrograde well in a transistor to enhance performance of the transistor
US4737471A (en) Method for fabricating an insulated-gate FET having a narrow channel width
US5272365A (en) Silicon transistor device with silicon-germanium electron gas hetero structure channel
US5382538A (en) Method for forming MOS transistors having vertical current flow and resulting structure
US4038107A (en) Method for making transistor structures
US4729001A (en) Short-channel field effect transistor
US5770503A (en) Method of forming low threshold voltage vertical power transistor using epitaxial technology
US4746964A (en) Modification of properties of p-type dopants with other p-type dopants
US4662058A (en) Self-aligned gate process for ICS based on modulation doped (Al,Ga) As/GaAs FETs
US4596068A (en) Process for minimizing boron depletion in N-channel FET at the silicon-silicon oxide interface
US4490182A (en) Semiconductor processing technique for oxygen doping of silicon
JPH0259624B2 (en)
USH368H (en) Field-effect transistor
JPH0642465B2 (en) Method of forming shallow junction
US6064077A (en) Integrated circuit transistor
JPS5916427B2 (en) Junction field effect transistor
KR920017242A (en) Manufacturing method of bi CMOS device
EP0530046A1 (en) Integrated circuit transistor
JPH03220774A (en) Mos field effect transistor
JPS63226072A (en) Manufacture of semiconductor device
US6274915B1 (en) Method of improving MOS device performance by controlling degree of depletion in the gate electrode
JPS6314871B2 (en)
KR900008154B1 (en) Field effect transistor

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE