Recherche Images Maps Play YouTube Actualités Gmail Drive Plus »
Connexion
Les utilisateurs de lecteurs d'écran peuvent cliquer sur ce lien pour activer le mode d'accessibilité. Celui-ci propose les mêmes fonctionnalités principales, mais il est optimisé pour votre lecteur d'écran.

Brevets

  1. Recherche avancée dans les brevets
Numéro de publicationUSRE28386 E
Type de publicationOctroi
Date de publication8 avr. 1975
Date de dépôt22 déc. 1972
Date de priorité11 avr. 1968
Autre référence de publicationDE1918556A1, US3556880
Numéro de publicationUS RE28386 E, US RE28386E, US-E-RE28386, USRE28386 E, USRE28386E
InventeursFrederic P. Heinian
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes: USPTO, Cession USPTO, Espacenet
Method of treating semiconductor devices to improve lifetime
US RE28386 E
Résumé  disponible en
Images(1)
Previous page
Next page
Revendications  disponible en
Description  (Le texte OCR peut contenir des erreurs.)

April 8, 1975 P. HEIMAN 21 A1. Re. 28,386

IIETHOD OI TREATING SEMICONDUCTOR DEVICES TO IHPRD E LIFETIME ori inal Filed April 11, 1968 Ward awn/r Z/Mr M146? IN VEN TORS Frederic .Qfeiman Qaul 9L obmson WM BY ATMUEY "United States Patent Re. 28,386 Reissued Apr. 8, 1975 28,386 METHOD OF TREATING SEMICONDUCTOR DEVICES TO IMPROVE LIFETIME Frederic P. Heiman, East Brunswick, and Paul H. Robinson, Trenton, N.J., assignors to RCA Corporation Original No. 3,556,880, dated Jan. 19, 1971, Ser. No. 720,538, Apr. 11, 1968. Application for reissue Dec. 22, 1972, Ser. No. 317,743

Int. Cl. H011 7/34, 7/44 US. Cl. 148-191 14 Claims Matter enclosed in heavy brackets [II appears in the original patent but forms no part of this reissue specification; matter printed in italics indicates the additions made by reissue.

ABSTRACT OF THE DISCLOSURE The stability and lifetime of a device comprising a semiconductor body covered by an insulating layer is improved by thermally growing at least part of the insulating layer in an atmosphere comprising oxygen and hydrogen chloride, and substantially free of water vapor. The device is heated in this atmosphere to establish a gradient for out-dilfusion of certain deleterious metals from the device.

BACKGROUND OF THE INVENTION This invention relates to a method for treating semiconductor devices so as to improve the carrier lifetime thereof.

Many semiconductor devices include at least one region of semiconductor material covered by an overlying layer of insulating material. In particular, metal-oxide-semiconductor field effect devices, as well as planar devices (in which a protective insulating layer overlies the semiconductor surface at points where one or more P-N junction regions within the semiconductor material extend to the surface), employ this construction.

In many semiconductor devices of this type, it is important that instabilities due to surface states at the semiconductor-insulator interface and to trapped charges in the insulating layer be substantially eliminated. This requirement is especially severe in field effect devices employing the insulating layer as a biased dielectric.

In other applications, such as the recently introduced silicon vidicon structure (see. e.g., E. I. Gordon, A Solid-State Electron Tube for the Picturephone Set. Bell Laboratories Record. June 1967, pp. 1759), it is important that the semiconductor material exhibit a relatively long carrier lifetime. A technique has been developed for improving the stability of semiconductor-insulator structures of the type described by treating the insulating layer with an atmosphere which includes hydrogen chloride. This technique is described in US. patent application Ser. No. 714,577, filed Mar. 21, 1968; now Pat. No. 3,556,879, by Alfred Mayer, and assigned to the assignee of the instant application.

The specific example set forth in application Ser. No. 714,577 involves subjecting the semiconductor surface to an atmosphere comprising water vapor and hydrogen chloride. The water vapor rapidly oxidizes the semiconductor surface to (i) form the (silicon dioxide) insulating layer by thermal oxidation of the underlying silicon material, so that the insulating layer protects the semiconductor surface from undesirable etching by the hydrogen chloride gas, and the hydrogen chloride acts to (ii) convert certain deleterious metals to volatile chlorides at the exposed surface of the insulating layer, so that these chlorides leave the exposed surface to establish a gradient for outdiffusion of such deleterious metals from the semiconductor device.

While the treatment process described in application Ser. No. 714,577 substantially eliminates instability due to surface states and residual charge or polarization, it produces only a limited improvement in carrier lifetime.

Accordingly, an object of the present invention is to provide an improved method for treating semiconductor devices of the type described to considerably increase the carrier lifetime thereof.

SUMMARY OF THE INVENTION The invention is applicable to a semiconductor device manufacturing process in which a layer of insulating material is formed on at least a part of an operating semiconductor region of an active semiconductor element. The invention relates to an improvement in which the insulating layer is exposed to an atmosphere comprising a hydrogen halide, the atmosphere being maintained substantially free of Water vapor.

The semiconductor device is heated in this atmosphere at a temperature sufficient to convert a deleterious metal in the device to the metal halide. The temperature is sufficient to volatilize the halide at the exposed surface of the insulating layer so as to establish a gradient for out-diffusion of the deleterious metal from the semiconductor device toward the exposed insulating surface.

In the drawing:

FIG. 1 shows a silicon vidicon target structure manufactured according to the invention.

DETAILED DESCRIPTION In order to provide a substantial increase in the carrier lifetime of a semiconductor material, it is necessary to remove from the material any contaminants which degrade lifetime. Such contaminants are usually present in the form of heavy metals such as gold, copper and iron which act as trapping or recombination sites.

We have found that heat treatment of the semiconductor material in an atmosphere comprising hydrogen chloride and substantially free of water vapor produces a considerable improvement in lifetime.

In a particular process, a monocrystalline silicon wafer is cleaned by conventional methods. The wafer is then gas etched at 1100 C. in an atmosphere comprising hydrogen and including a volumetric concentration of hydrogen chloride on the order of 1%. This etching treatment is carried out for a sufiicient time to remove approximately 4 microns of silicon from the exposed surface of the wafer.

The wafer is then allowed to cool, and the hydrogen/ hydrogen chloride atmosphere is replaced by dry oxygen. The silicon wafer is exposed to the dry oxygen for approximately 3 minutes at a temperature on the order of 1200 C. in order to form a thin protective thermally grown silicon dioxide layer on the semiconductor surface. The purpose of this thin initial layer is to preclude undesirable etching of the silicon surface when hydrogen chloride gas is subsequently introduced into the oxygen atmosphere.

After the initial 3 minute oxidation, a 1% volumetric concentration of hydrogen chloride is introduced into the dry oxygen atmosphere, and the semiconductor wafer is treated in this atmosphere at the 1200 C. temperature for approximately 4 hours. During this time, the thickness of the oxide layer increases, and the hydrogen chloride acts to remove deleterious lifetime killing contaminants from the semiconductor-insulator structure.

After the 4 hour treatment, the atmosphere is changed to helium in order to remove any residual hydrogen chloride from the treated wafer.

The Wafer is allowed to cool and then annealed in a hydrogen atmosphere at a temperature on the order of 500 C. for a time on the order of 15 minutes.

The annealing process improves performance of devices manufactured from the silicon/silicon dioxide composite by reducing or eliminating surface states at the semiconductor-insulator interface.

A capacitance-voltage curve obtained from a wafer processed according to the method described above showed no measurable oxide charge, surface states or polarization.

The carrier lifetime of a wafer processed as described above was measured by applying an evaporated aluminum electrode to the exposed surface of the silicon dioxide layer, and subjecting the resultant structure to a large voltage pulse, applied between the aluminum electrode and the semiconductor material, in a polarity so as to establish a large depletion region at the semiconductor surface adjacent the electrode. The carrier lifetime was determined by measuring the time constant associated with relaxation of the depletion region to its equilibrium condition. This measuring technique is described in detail in a paper by F. P. Heiman entitled On the Determination of Minority Carrier Lifetime From the Transient Response of an MOS Capacitor," published in the IEEE Transactions on Electron Devices, November 1967, p. 781.

This measurement technique indicated a carrier lifetime on the order of to 300 microseconds, whereas the same measurement, when taken on a wafer processed as described above but without the addition of hydrogen chloride to the oxygen atmosphere, yielded a lifetime of 0.2 to 1.0 microsecond.

While the preferred embodiment of our process is directed to the use of hydrogen chloride, any hydrogen halide which does not remove the silicon dioxide insulating layer may be employed In particular, hydrogen bromide and hydrogen iodide may be substituted for the hydrogen chloride.

While we prefer to carry out the heat treatment step in the hydrogen chloride /oxygen atmosphere at a temperature in the range of 1000 to 1200 0, this treatment may be satisfactorily accomplished at temperatures in the range of 800 to 1350" C. While our heat treatment step is carried out at an oxygen flow rate on the order of 1000 to 3000 cc. per minute, and at atmospheric pressure, other pressures and flow rates may be employed. While the preferred volumetric concentration of hydrogen chloride is on the order of 1%, good results are obtained with a volumetric concentration of 0.5%, and other concentrations in the range of 0.1 to 2% may be employed. On the other hand, a volumetric concentration of 10% results in reaction of the hydrogen chloride with the oxygen to produce water vapor; devices treated in the 10% hydrogen chloride atmosphere show negligible improvement in carrier lifetime, and pitting of the silicon surface.

The process of our invention may, e.g., be carried out in either a resistance heated or a cold wall (induction heated) furnace. Based upon the aforementioned and other data which we have obtained, heat treatment in an atmosphere comprising dry oxygen and hydrogen chloride, the atmosphere being substantially free of water vapor, results in an increase of carrier lifetime by a factor of 10 to 1000 or more. The absence of water vapor during our heat treatment process was confirmed by monitoring the oxidation rate of the silicon semiconductor material, it being well known that silicon oxidizes much more rapidly in water vapor than in a dry oxygen atmosphere.

Our process is particularly applicable to the manufacture of a light sensitive image pickup tube (hereinafter referred to as a silicon vidicon) which employs an electron beam addressed silicon diode array of the type shown in FIG. 1. Such a structure requires relatively high (on the order of 10 micro seconds or more) carrier lifetimes in the semiconductor material; such lifetimes may be reproducibly attained by the process of our invention.

In a silicon vidicon tube, a target 1 is scanned by a low velocity electron beam 2 emanating from a cathode 3. The electron beam 2 is formed, collimated, focussed, deflected and accelerated by a suitable electrongun structure (not shown). Typically the electron beam 2 may have a circular cross-section with a diameter on the order of 1 mil.

The target 1 comprises a substrate 4 of monocystalline semiconductor material, preferably silicon, of one conductivity type into which a large number of small regions 5 of opposite conductivity type are diffused. Preferably, the substrate 4 is of N type conductivity and the diffused regions 5 are of P type conductivity. The diffused P type regions 5 are of a diameter substantially smaller than the diameter of the electron beam 2, so that the beam 2 subtends a number of the regions 5, thus making it unnecessary to register the beam 2 with the individual regions.

Each of the diffused P type regions has a small P-N junction 6 to form a diode in conjunction with the substrate 4. The exposed surface of the substrate 4 adjacent the P type regions 5 is provided with a thin silicon dioxide coating 7 which overlies and protects the P-N junctions 6 where they extend to the semiconductor surface.

A thin surface layer 8 of relatively high electrical conductivity is disposed adjacent the opposite surface of the substrate 4, i.e. the surface which may be illuminated by a light image to be scanned. The conductive layer 8 may comprise a layer of N+ conductivity type formed by diffusion of a suitable donor impurity into the substrate 4. The conductive layer 8 and the substrate 4 are sufficiently thin so that carriers generated by the light incident upon the exposed surface of the layer 8 may penetrate the substrate 4 to reach the P-N junctions 6.

The substrate 4 is supported by a ring 9 of relatively thick semiconductor material, which may be secured to the inside envelope of the silicon vidicon tube.

Each of the P-N junctions 6 is reverse biased by means of (i) a voltage source 10, which may typically have a value on the order of 10 volts, and (ii) a load resistor 11, which may typically have a value on the order of several hundred thousand ohms. When the electron beam 2 is not scanning a particular P type region 5, the P-N junction 6 associated with that region is discharged by incident photons from the light image, the amount of discharge being dependent upon the photon flux. When the scanning electron beam 2 returns to this particular P-N junction, electrons flow to the P type region to provide a current which recharges the associated diode. This recharging current is directly related to the photon flux (light intensity) from the light image incident upon the P-N junction 6, and a corresponding voltage signal is developed across the load resistor 11. This signal is coupled to suitable amplified circuitry by means of a capacitor 12.

The incident light discharges the individual diodes by generating electron-hole pairs in the vicinity of the associated P-N junctions. These generated electrons and holes diffuse into the P-N junction region and are swept across the junction by the associated space charge field therein, thus serving to discharge the associated diodes. A number of the carriers created by the incident photons recombine and are lost, so that they do not contribute to discharge of the associated diodes. This recombination reduces the collection efiiciency of the target 1, and directly degrades the sensitivity of the Cilicon Vidicon.

The collection efficiency may be improved by increasing the bulk carrier lifetime and the surface recombination velocity of the semiconductor material comprising the target 1. Specifically, long carrier lifetimes and low recombination velocities provide high collection efiiciency and therefore improve optical sensitivity.

The target 1 may be manufactured by providing a silicon substrate 4 of N type conductivity, having an N+ surface layer 8 diffused therein. To form the P type regions 5, the corresponding surface of the substrate 4 is coated with a thermally grown silicon dioxide layer 7, which may typically have a thickness on the order of 0.5 to 1 micron. The silicon dioxide layer 7 is grown in an atmosphere comprising dry oxygen and a volumetric concentration of hydrogen chloride on the order of 1%, in the manner previously described.

After the silicon dioxide layer has been grown, holes are etched therein exposing small regions of the substrate 4. A thin glassy layer containing a suitable acceptor impurity material is deposited on the semiconductor surface, and subsequently heated to form the diffused P type regions 5. Preferably, borosilicate glass may be employed as the impurity source. During or after the diffusion process, the borosilicate glass may be exposed to an atmosphere comprising hydrogen chloride, the atmosphere being substantially free of water vapor, in order to further improve the carrier lifetime of the semiconductor material in the manner previously described.

Thereafter, the portion of the borosilicate glass layer overlying the active P type regions 5 may be removed by 'photoetching.

We claim:

1. In a process for manufacturing a semiconductor device, comprising the steps of:

providing a substrate having a number of operating semiconductor regions forming at least one active semiconductor element, at least one of said regions being contiguous with a given surface of said substrate;

forming a layer of insulating material on said given surface overlying at least a part of said at least one region, said device including at least one deleterious metal ingredient;

exposing said layer to an atmosphere comprising a hydrogen halide; and

heating said substrate to a given temperature sufficient to convert said metal to the metal halide and to volatilize the halide at the exposed surface of said insulating layer, thereby establishing a gradient for out-diffusion of said metal from said device toward said exposed surface,

the improvement wherein said atmosphere is maintained substantially free of water vapor.

2. The improvement according to claim 1, wherein said atmosphere comprises (i) substantially dry oxygen and (ii) hydrogen chloride, hydrogen bromide or hydrogen iodide.

3. The improvement according to claim 1, wherein said semiconductor material comprises silicon and said insulating layer comprises silicon dioxide, at least a part of said silicon dioxide layer being thermally grown during at least a part of said exposing step.

4. The improvement according to claim 3, wherein said atmosphere includes dry oxygen and the volumetric concentration of said halide is less than 10%.

5. The improvement according to claim 4, wherein said halide comprises hydrogen chloride at a. volumetric concentration in the range of 0.1 to 2%.

6. The improvement according to claim 4, wherein said halide comprises hydrogen chloride at a volumetric concentration on the order of 1%, said atmosphere being maintained at normal atmospheric pressure.

7. The improvement according to claim 3, wherein said atmosphere comprises dry oxygen and hydrogen chloride, and said thermally grown silicon dioxide is grown at a specified temperature in the range of 800' to 1350' C., said given temperature also being in the range of 800 to 1350 C.

8. The improvement according to claim 7, wherein said temperatures are in the range of 1000 to 1200' C.

9. The improvement according to claim 7, comprising the additional step of, after said insulating layer forming and exposing steps, annealing said device by heating said substrate in an atmosphere comprising hydrogen gas.

10. The improvement according to claim 9, wherein said atmosphere comprises hydrogen and said annealing step is carried out at a temperature on the order of 500 C. for a time on the order of at least 15 minutes.

11. A process for manufacturing an electron beam addressed semiconductor diode array target structure, comprising the steps of:

providing a substrate of monocrystalline semiconductor material of one conductivity type, said substrate including at least one deleterious metal ingredient;

forming an insulating layer on one surface of said substrate, said insulating layer having a plurality of apertures therein exposing corresponding areas of the substrate;

diffusing into said areas through said apertures a conductivity type determining impurity material to form in said areas a corresponding plurality of semiconductor regions of opposite conductivity type, with a P-N junction between each of said regions and said substrate;

exposing said insulating layer to an atmosphere comprising a hydrogen halide and substantially free of water vapor; and

heating said substrate to a given temperature suflicient to convert said metal to the metal halide and to volatilize the halide at the exposed surface of said insulating layer, thereby establishing a gradient for out-diffusion for said metal from said exposed surface.

12. A target manufacturing process according to claim 11, wherein said semiconductor material comprises silicon.

13. A target manufacturing process according to claim 12, wherein said insulating layer comprises borosilicate glass or silicon dioxide.

14. In a method of thermally growing a silicon dioxide layer on the surface of a silicon material comprising the step of:

heating the silicon material to a temperature of between about 800' C. and I 350' C. in the presence of oxygen;

the improvement comprising the step of:

introducing into the oxygen gaseous hydrogen chloride in a concentration between about 0.1% to 2.07 by volume relative to the oxygen to new tralize the electrical efiects of mobile ions in the silicon dioxide layer.

References Cited The following references, cited by the Examiner, are of record in the patented file of this patent or the original patent.

UNITED STATES PATENTS 2,953,486 9/1960 Atalla 148-191 3,007,820 11/1961 McNamara et al. 148-191 3,085,033 4/1963 Handelman 148-191 3,162,557 12/1964 Brook et a1. 148-191 3,183,128 5/1965 Leistiko Ir., et a1. 148-108 UX 3,243,323 3/1966 Corrigan et al. 148-188 UX 3,373,051 3/1968 Chu et al. 11-48-15 UX 3,518,134 6/1970 Preist 148-15 X 3,562,033 2/1971 Jansen et al. 148-189 CHARLES E. VAN HORN, Primary Examiner B. J. LEWRIS, Assistant Examiner U.S. Cl. X.R.

Citations de brevets
Brevet cité Date de dépôt Date de publication Déposant Titre
US2953486 *1 juin 195920 sept. 1960Bell Telephone Labor IncJunction formation by thermal oxidation of semiconductive material
US3007820 *26 févr. 19607 nov. 1961Motorola IncDecontamination process
US3085033 *8 mars 19609 avr. 1963Bell Telephone Labor IncFabrication of semiconductor devices
US3162557 *13 déc. 196122 déc. 1964IbmSelective removal of impurities from semiconductor bodies
US3183128 *11 juin 196211 mai 1965Fairchild Camera Instr CoMethod of making field-effect transistors
US3243323 *1 sept. 196529 mars 1966Motorola IncGas etching
US3373051 *16 mars 196712 mars 1968Westinghouse Electric CorpUse of halogens and hydrogen halides in insulating oxide and nitride deposits
US3518134 *14 août 196730 juin 1970Stanford Research InstGaseous etching of molybdenum
US3562033 *12 févr. 19689 févr. 1971Asea AbMethod of doping silicon with group iii substance
Référencé par
Brevet citant Date de dépôt Date de publication Déposant Titre
US5529937 *20 juil. 199425 juin 1996Semiconductor Energy Laboratory Co., Ltd.Process for fabricating thin film transistor
US5843225 *7 juin 19951 déc. 1998Semiconductor Energy Laboratory Co., Ltd.Process for fabricating semiconductor and process for fabricating semiconductor device
US6168980 *26 sept. 19962 janv. 2001Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the same
US618043916 janv. 199730 janv. 2001Semiconductor Energy Laboratory Co., Ltd.Method for fabricating a semiconductor device
US622515220 janv. 19991 mai 2001Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and fabrication method thereof
US623262117 juin 199915 mai 2001Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating the same
US631678919 févr. 199913 nov. 2001Semiconductor Energy Laboratory Co. Ltd.Semiconductor device and method for producing the same
US63168109 juil. 199913 nov. 2001Semiconductor Energy Laboratory Co., Ltd.Display switch with double layered gate insulation and resinous interlayer dielectric
US631976121 juil. 199720 nov. 2001Semiconductor Energy Laboratory Co., Ltd.Method of fabricating a thin film transistor
US637686015 avr. 199923 avr. 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor device
US641380525 juin 19962 juil. 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor device forming method
US64138424 mai 20012 juil. 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating the same
US645540123 mai 200024 sept. 2002Semiconductor Energy Laboratory Co., Ltd.Methodology for producing thin film semiconductor devices by crystallizing an amorphous film with crystallization promoting material, patterning the crystallized film, and then increasing the crystallinity with an irradiation
US646528716 janv. 199715 oct. 2002Semiconductor Energy Laboratory Co., Ltd.Method for fabricating a semiconductor device using a metal catalyst and high temperature crystallization
US64758401 avr. 19975 nov. 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the same
US647826328 oct. 199912 nov. 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and its manufacturing method
US65010949 juin 199831 déc. 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor device comprising a bottom gate type thin film transistor
US650417428 mars 20007 janv. 2003Semiconductor Energy Laboratory Co., Ltd.Thin film transistor; crystal silicon thin film formed on a substrate such as a glass and quartz; containing a metal element which promotes crystallization of silicon
US652835828 mars 20004 mars 2003Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for fabricating the same
US652882017 janv. 19974 mars 2003Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating same
US654131521 févr. 20011 avr. 2003Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and fabrication method thereof
US661014224 nov. 199726 août 2003Semiconductor Energy Laboratory Co., Ltd.Process for fabricating semiconductor and process for fabricating semiconductor device
US671333021 juil. 199730 mars 2004Semiconductor Energy Laboratory Co., Ltd.Method of fabricating a thin film transistor
US674406917 janv. 19971 juin 2004Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and its manufacturing method
US679111120 déc. 200214 sept. 2004Semiconductor Energy Laboratory Co., Ltd.Semiconductor device
US68756286 mars 19975 avr. 2005Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and fabrication method of the same
US692421324 sept. 20022 août 2005Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and process for fabricating the same
US698728327 juin 200217 janv. 2006Semiconductor Energy Laboratory Co., Ltd.Semiconductor device structure
US699798518 déc. 199614 févr. 2006Semiconductor Energy Laboratory Co., Ltd.Semiconductor, semiconductor device, and method for fabricating the same
US703781131 oct. 20002 mai 2006Semiconductor Energy Laboratory Co., Ltd.Method for fabricating a semiconductor device
US705638116 janv. 19976 juin 2006Semiconductor Energy Laboratory Co., Ltd.Fabrication method of semiconductor device
US70567755 juil. 20056 juin 2006Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and process for fabricating the same
US707872713 janv. 200318 juil. 2006Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and its manufacturing method
US713574124 mars 200014 nov. 2006Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a semiconductor device
US714149119 déc. 200528 nov. 2006Semiconductor Energy Laboratory Co., Ltd.Method for fabricating a semiconductor device
US71732821 juin 20046 févr. 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having a crystalline semiconductor film
US719281713 août 200420 mars 2007Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing a semiconductor device
US732990622 déc. 200412 févr. 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the same
US739105130 déc. 200524 juin 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device forming method
US741690728 juil. 200426 août 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for forming the same
US74226305 juin 20069 sept. 2008Semiconductor Energy Laboratory Co., Ltd.Fabrication method of semiconductor device
US742778014 nov. 200323 sept. 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating same
US74560566 nov. 200225 nov. 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for fabricating the same
US767506014 févr. 20079 mars 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for producing it
US76790879 août 200216 mars 2010Semiconductor Energy Laboratory Co., Ltd.Semiconductor active region of TFTs having radial crystal grains through the whole area of the region
US770983710 juil. 20064 mai 2010Semiconductor Energy Laboratory Co., LtdSemiconductor device and its manufacturing method
US794393020 juin 200817 mai 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor device forming method
US795209731 juil. 200131 mai 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating the same
WO1981000487A1 *7 août 198019 févr. 1981Ncr CoHydrogen annealing process for silicon gate memory device
Classifications
Classification aux États-Unis438/58, 427/255.37, 438/477, 148/DIG.600, 148/DIG.970, 148/DIG.118
Classification internationaleH01L23/29, H01L27/00, H01J29/45, H01L21/00
Classification coopérativeH01L21/00, H01J29/455, H01J9/233, H01L27/00, Y10S148/053, Y10S148/049, H01L23/291, Y10S148/043, Y10S148/118
Classification européenneH01L27/00, H01L23/29C, H01L21/00, H01J9/233, H01J29/45B2B