|Numéro de publication||USRE33829 E|
|Type de publication||Octroi|
|Numéro de demande||US 07/487,482|
|Date de publication||25 févr. 1992|
|Date de dépôt||2 mars 1990|
|Date de priorité||19 juil. 1985|
|État de paiement des frais||Payé|
|Autre référence de publication||DE3687488D1, DE3687488T2, EP0209113A2, EP0209113A3, EP0209113B1, US4804953|
|Numéro de publication||07487482, 487482, US RE33829 E, US RE33829E, US-E-RE33829, USRE33829 E, USRE33829E|
|Inventeurs||Donald E. Castleberry|
|Cessionnaire d'origine||General Electric Company|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Citations de brevets (9), Citations hors brevets (16), Référencé par (39), Classifications (17), Événements juridiques (3)|
|Liens externes: USPTO, Cession USPTO, Espacenet|
This application is a continuation of application Ser. No. 756,640, filed 7/19/85 now abandoned.
The present invention is generally directed to the construction of liquid crystal display devices. More particularly, the present invention is directed to redundant conductor structures provided for x and y address lines in liquid crystal display (LCD) devices.
A liquid crystal display device typically comprises a pair of flat panels sealably containing a quantity of liquid crystal material. These liquid crystal materials typically fall into two categories: dichroic dyes in a guest/host system or twisted nematic materials. The flat panels generally possess transparent electrode material disposed on their inner surfaces in predetermined patterns. One panel is often covered completely by a single transparent "ground plane" electrode. The opposite panel is configured with an array of transparent electrodes, referred to herein as "pixel" (picture element) electrodes. Thus, the typical cell in a liquid crystal display includes liquid crystal material disposed between a pixel electrode and a ground electrode forming, in effect, a capacitor-like structure disposed between transparent front and back panels. In general, however, transparency is only required for one of the two panels and the electrodes disposed thereon.
In operation, the orientation of liquid crystal material is affected by voltages applied across the electrodes on either side of the liquid crystal material. Typically, a voltage applied to the pixel electrode effects a change in the optical properties of the liquid crystal material. This optical change causes the display of information on the liquid crystal display (LCD) screen. In conventional digital watch displays and in newer LCD screens used in miniature television receivers, the visual effect is typically produced by variations in reflected light. However, the utilization of transparent front and back panels and transparent electrodes also permit the visual effects to be produced by transmissive effects. These transmissive effects may be facilitated by separately powered light sources for the display, including fluorescent light type devices. LCD display screens may also be employed to produce color images through the incorporation of color filter mosaics in registration with the pixel electrode array. Some of these structures may employ polarizing filters to either enhance or provide the desired visual effect.
Various electrical mechanisms are employed to sequentially turn on and off individual pixel elements in an LCD display. For example, metal oxide varistor devices have been employed for this purpose. However, the utilization of thin film semiconductor switch elements is most relevant herein. In particular, a preferable switch element comprises a thin film field effect transistor (FET). These devices are preferred in LCD displays because of their potentially small size, low power consumption, switching speeds, ease of fabrication, and compatibility with conventional LCD structures.
The pixel elements in an LCD are typically arranged in a rectangular array of rows and columns. Each pixel electrode is associated with its own FET switch device. Each switch device is connected to a data line and a gate line. Electrical signals applied simultaneously to each of these lines permit each pixel to be addressed independently. Accordingly, the LCD is typically provided with a set of parallel data lines which can be made to address cells in a horizontal or x direction. Likewise, gate lines are provided for accessing cells in a vertical or y direction. In operation, the image on the LCD device may be refreshed at a rate which is typically approximately 60 Hz.
More particularly, amorphous silicon FET addressed liquid crystal matrix displays provide an attractive approach to high contrast, flat panel television type displays. Ideally, in an FET addressed LCD device, when the FET is turned on, the "liquid crystal capacitor" charges to the data or source line voltage. When the FET is turned off, the data voltage is stored on the liquid crystal capacitor.
Specific attention is now directed to certain problems occurring in LCD display devices which are solved by the practice of the present invention. In particular, in thin film FET driven liquid crystal displays, the horizontal and vertical address lines (that is, the gate lines and data lines) must all be continuous. For example, in a display having a matrix of 400×400 pixel cells with a resolution of 4 lines per millimeter (100 lines per inch), the total length of the address lines is approximately 100,000 mm. The width of the lines should be less than approximately 10 microns in order to maintain a high relative percentage of active cell area in the display. In the fabrication of these devices, defects can occur in many of the processing steps. These defects may occur as a result of dust or dirt interfering with metal deposition or adhesion, flaws in photoresist patterns used to etch the metal lines, scratches, etc. Additionally, defects in these lines can result from unsatisfactory step coverage. This occurs in those situations where metal lines are required to traverse a vertical or near vertical side wall structure, for example, in an etched insulating layer. These steps typically occur at points in the device at which the horizontal and vertical lines cross over one another. In integrated circuit fabrication, typical open line defect probabilities for lines of this width are of the order of 10-5 per mm. It is therefore apparent that methods for reducing the probability of open x and y addressing lines and methods for enhancing the yield of the LCD device are desired.
In accordance with a preferred embodiment of the present invention, a liquid crystal display comprises a pair of flat substrates with at least one of them being transparent. A quantity of liquid crystal material is disposed and contained between the substrates. An array of pixel electrodes is disposed on at least one of the substrates. At least one ground plane electrode is disposed on the other of the substrates so that liquid crystal material is disposed between the pixel electrodes and any ground plane electrodes. Either the array of pixel electrodes comprise transparent material or the ground plane electrode or electrodes comprise transparent material. In a see-through embodiment of the present invention, both substrates, the ground plane electrode, and the array of pixel electrodes comprise transparent conductive material such as indium tin oxide (ITO). An array of semiconductor switch elements is associated with each pixel electrode. A set of electrically conductive data lines and a set of electrically conductive gate lines are provided and configured with the switch elements so that voltages appearing on the data line are applied to select pixel electrodes.
Most relevantly with respect to the present invention, the semiconductor switch elements preferably comprise thin film field effect transistors. Furthermore, the data lines exhibit a multilayer structure extending for at least a portion of their length with at least two of these layers comprising conductive material in electrical contact along a portion of their length. This structure provides redundancy of up to 90% along the data line length. In a preferred embodiment of the present invention, the data lines comprise a three layer structure with the intermediate layer comprising the same insulating material as the gate insulation for the FET. The first layer of data line metal is preferably deposited at the same time as the gate metal. Accordingly, this metal pattern is incorporated in the gate metal mask pattern. The second or upper conductive layer comprises metal deposited at the same time as the source and drain metal for the FET switches. The presence of the insulating layer and its configuration permit the upper data line layer to be applied without steep step crossovers at the gate line intersections. Electrical contact is established between the conductive layers in the data lines on either side of a narrower strip in the insulating layer. While contact is made along a step structure, the length of this step is much longer, thereby insuring contact at least somewhere along its length. In this way, a redundant data line structure is provided. Similarly, in a preferred embodiment of the present invention, redundancy in the gate line layer is also provided. However, in this situation, it is not necessary to employ an intermediary insulating layer. It is also noted that the roles of the data lines and gate lines may be reversed by varying electrical connections with the switch element.
Accordingly, it is an object of the present invention to provide a mechanism and structure for redundant gate and data lines in liquid crystal display devices.
It is also an object of the present invention to provide LCD display devices having greater reliability.
Lastly, but not limited hereto, it is an object of the present invention to provide improved LCD device structure which are readily manufacturable and which provide improved product yield.
FIG. 1 is a cross sectional side elevation view illustrating a thin film FET;
FIG. 2 is a cross sectional end view illustrating a portion of one embodiment of the present invention in which a three layer, partially redundant data line structure is employed;
FIG. 3A is a plan view illustrating a gate metal pattern employed in a preferred embodiment of the present invention;
FIG. 3B is a plan view illustrating a pattern for gate insulation and active silicon as part of a thin film FET;
FIG. 3C is a plan view illustrating a metal pattern for source and drain electrodes and data lines;
FIG. 3D is a plan view illustrating a pattern of pixel electrode material in the neighborhood of a thin film semiconductor switch device;
FIG. 4 is a plan view illustrating a portion of an LCD device made in accordance with the present invention;
FIG. 5 is a plan view showing an enlarged view of a portion of FIG. 5;
FIG. 6 is a schematic diagram illustrating an electrical model for the semiconductor switch devices associated with each pixel electrode.
FIG. 1 illustrates, in cross section, a conventional thin film FET used in LCD devices. In particular, substrate 20 typically comprises a transparent material such as glass. In accordance with conventional photopatterning methods, metal gate electrode 21 is affixed to this substrate. A patterned layer of insulating material 24 such as silicon nitride is then typically deposited so as to cover gate electrode 21 and to extend a certain distance on either side thereof. An active layer of amorphous silicon (α-silicon) is then typically applied and doped with appropriate polarity dopants to produce a channel region wherein current flow is controlled by electrical signals applied to the gate electrode. In a similar fashion, source and drain electrodes 22 and 23, respectively, are deposited using photopatterning methods to complete the formation of a thin film FET device. It is noted, however, that the opacity of gate material 21 is not a significant viewing limitation since the gate electrode may only be approximately 10 microns in width and therefore essentially invisible to the user. In contrast, the pixel electrodes are by far the larger elements in an LCD device cell. The pixel electrodes are typically approximately 0.01 inches square.
FIG. 2 is particularly relevant to understanding the present invention. In particular, FIG. 2 is a cross sectional view of a portion of FIG. 5 which is more particularly described below. The upper portion of FIG. 2 is shown in phantom view since these structures are, strictly speaking, not produced by the mask patterns in FIGS. 3A-3D. These mask patterns are typically employed to generate only one side of the substrates or panels which form major constituents in an LCD device. As above, substrates 20 and 30 may typically comprise transparent material. Also, as above, ground plane 38 and pixel electrodes 39 are disposed on substrates 30 and 20, respectively. These electrodes may comprise transparent conductive material. Most relevant to the present invention, however, is the data line structure which includes data lines 32 and insulating material 34. It is seen that the first, conductive layer and the third, conductive layer, both designated by reference numeral 32 are in electrical contact along either side of narrow insulating strip 34. The first, conductive data line layer is preferably fabricated in the same process stage as the gate electrodes of the FET switching elements. The second, insulating layer 34 is preferably fabricated in the same process stage as the gate insulating material. The third, conductive layer in the data line structure is preferably fabricated in the same process stage as the fabrication of the source and drain metallization. The presence of insulating layer 34 permits the third or upper conductive data line layer to cross gate lines, from which it is insulated, without the formation of step discontinuities which tend to decrease circuit reliability. Furthermore, the first or lowermost conductive line is in contact with the upper conductive line and provides redundant circuit connection along approximately 90% of the length of each data line. Lowermost data line 32 is, however, provided with gaps to accommodate passage of gate line conductors. While it appears that a longer step jump is now required for contact between the conductive layers in the data line, this is in fact not a problem since insulating material strip 34 in FIG. 2 is relatively narrow and since electrical contact is now possible along the entire length of the lower data line conductor.
FIGS. 3A-3D are layout patterns employable in the fabrication of the present invention. FIG. 3A illustrates a pattern for gate metal and associated horizontal gate drive lines 31. A scale is provided for reference. Additionally, FIG. 3A illustrates the presence of redundant data line 32. These lines are redundant in the sense that they do not form a complete electrical circuit in the layer shown but instead partially duplicate data line paths which are completed in whole in another layer as shown in FIG. 3C. Nonetheless, connection is provided to complete the data line circuit, as shown in FIG. 3C. The metallization layer shown in FIG. 3A is preferably opaque so as to prevent light from reaching the channel regions from one side of the display. The channel regions are formed above the large rectangular area shown in FIG. 3A. Metallic pad 36 is also shown in the layer illustrated in FIG. 3A. Pad 36 facilitates electrical connection between the device drain and the pixel electrode.
After the metallization layer of FIG. 3A is formed on an opaque substrate or on a transparent substrate such as glass, the pattern of FIG. 3B is employed in the deposition of insulating and semiconducting layers. In particular, a layer of silicon nitride or other insulating material is deposited in the pattern shown in FIG. 3B. The insulating material pattern shown in FIG. 3B serves several purposes. Firstly, this pattern provides gate insulating material for thin film FET devices. Secondly, this insulating layer is disposed so as to electrically insulate the gate lines from the data lines. Lastly, it is noted that the vertical portions extending upwardly and downwardly from the central patch region of FIG. 3B overlie data lines 32 shown in FIG. 3A. However, it is noted that the insulating layer in FIG. 3B is narrower than data line 32 in FIG. 3A. This permits the formation of a partially redundant data line as shown in FIG. 3C. Because the width of insulating layer 34 in FIG. 3B is narrower, electrical contact is thereby permitted between the data line conductors shown in FIGS. 3A and the complete data line conductors shown in FIG. 4C, both of which are indicated by reference numeral 32. FIG. 2 provides a cross sectional view of the resulting structure.
As pointed out above, the pattern of FIG. 3B is employed to serve an additional function. In particular, it serves as a pattern for the deposition of a layer or layers of semiconductor material. In particular, it is preferable to employ a triple layer having the pattern shown in FIG. 3B. In this case, the lowermost (that is, first) layer comprises silicon nitride, the next layer comprises α-silicon, and the next layer comprises α-silicon doped with material so as to provide the layer with an N+ polarity. These layers are formed using conventional thin film FET processing.
The next layer applied to the substrate is a metallization layer having the configuration illustrated in FIG. 3C. In particular, the finger projections 32a and 32b extend from data line 32. These projections form source electrodes for an FET. Metallization pattern 33 provides a common drain electrode for the FET formed. This drain electrode is ultimately connected to pixel electrode 39 shown in FIGS. 2, 6, and 3D. It is also in electrical contact with pad 36 in FIG. 3A. Data line 32 is connected to source electrodes 32a and 32b and in addition, because of the narrower width of insulating layer of FIG. 3B, data line 32 is in contact with the partially redundant data line having the same reference numeral in the layer of FIG. 3A. This provides a redundant structure for increased display reliability. It is also noted that gate line 31 is provided with enhanced metallization from the layer of FIG. 3C, again to provide enhanced display reliability.
The next layer to be applied is the layer of pixel electrode patterns. The pixel electrodes must necessarily comprise electrically conductive material. However, depending upon the specific nature of the LCD device, the electrically conductive material may or may not be transparent. However, for transparency, indium tin oxide is preferably employed for this purpose. Accordingly, although pixel electrodes 39 comprise electrically conductive material, they are hatched as glass in figures herein to suggest their potentially transparent nature. It is, of course, required that either the ground plane electrodes or the pixel electrodes, or both, comprise transparent material. If they are both opaque, the purpose of the display is defeated. With further reference to the pixel electrodes, it is noted that FIG. 3D illustrates the presence of four such pixel electrodes. However, the semiconductor switch is in fact associated with the pixel electrode 39 in the lower righthand corner of FIG. 3D. This pixel electrode is in electrical contact with metal (drain) pad 33 in FIG. 3C.
FIG. 4 illustrates in an enlarged view, a single pixel cell and portions of the cells which surround it. The gate lines associated with the cells are shown extending in a horizontal direction. The data lines associated with the cells are shown extending in a vertical direction. It is noted, however, that the relative directionality of these lines is not fixed and that alternate configurations may be employed in which the horizontal and vertical roles are reversed. Additionally, each pixel cell is seen to be uniquely associated with a selected data line and gate line. Each pixel cell is seen to include a pixel electrode and its associated semiconductor switching device. The structure seen in FIG. 4 typically comprises one side of a liquid crystal display device. The other side typically comprises a ground plane electrode disposed on a transparent substrate. Liquid crystal material is disposed between the pixel electrodes and the ground plane electrode or electrodes. While the pixel cells shown in FIG. 4 are square, it is also possible to employ cells of differing shapes or varying sizes. Likewise, while the data lines and gate lines are shown extending in horizontal and vertical directions, it is also possible to employ data lines disposed so as to more closely resemble oblique coordinate systems.
FIG. 5 provides a detailed view of the structure that results from the fabrication steps performed using the patterns shown in FIGS. 4A-4D. FIG. 5 provides an overview of the resulting structure and serves to more particularly describe interlayer structural relationships. FIG. 5 is also notable for the presence of section line 2 referring particularly to FIG. 2 which show the cross section of a typical data line.
FIG. 6 provides an electrical schematic diagram for a single pixel cell. In particular, a capacitor symbol with upper plate 39 and lower plate 38 is employed to represent and suggest the capacitor portion of the cell. Lower plate 38 typically comprises the ground plane electrode and upper plate 39 typically comprises the individual pixel electrodes. The pixel electrodes are electrically connected to drains 33 of FET with gate 31 and source electrodes 32a and 32b. The gate lines and data lines are as shown in FIG. 6. It should be noted, however, that references herein to source and drain electrodes are exemplary only. As is well known in the art, FET devices often exhibit symmetries in which source and drain designations exist only for convenience or as a result of external device connections.
It is also possible to fabricate liquid crystal display devices which display color images rather than monochrome ones. In such devices, a mosaic color filter is typically employed. This color filter is preferably disposed over the ground plane electrode. In accordance with the present invention, it is also possible to dispose spacer material on this filter. However, this is a less desirable arrangement for the reason that the color filter layer must be accurately registered and aligned with respect to the thin film transistor array and the associated pixel electrodes.
As indicated above, different forms of liquid crystal material may be employed in the present invention. In the event that twisted nematic materials are employed, a pair of polarizers are also required. These polarizers are typically disposed external to the walls of the LCD device which contain the liquid crystal material. In LCD devices employing dichroic dyes (guest/host systems), polarizer pairs are no longer required. In these embodiments, systems with either a single polarizer or no polarizers at all may be employed.
Accordingly, from the above, it may be appreciated that the liquid crystal display device of the present invention provides improved display performance, manufacturing yield and is compatible with conventionally employed LCD device fabrication methods. It is also seen that the present invention facilitates the formation of complete, high quality, high contrast images, even color images.
While the invention has been described in detail herein in accord with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.
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|Classification aux États-Unis||345/92, 349/54, 345/206, 345/93, 349/46|
|Classification internationale||G02F1/136, G02F1/1368, G09G3/20, G02F1/1335, G02F1/1362|
|Classification coopérative||G02F2202/103, G02F2001/13629, G02F1/1362, G02F1/1368, G02F1/133512|
|Classification européenne||G02F1/1368, G02F1/1362|
|14 août 1992||FPAY||Fee payment|
Year of fee payment: 4
|28 juin 1996||FPAY||Fee payment|
Year of fee payment: 8
|19 juin 2000||FPAY||Fee payment|
Year of fee payment: 12