USRE36180E - Simultaneous read and refresh of different rows in a DRAM - Google Patents

Simultaneous read and refresh of different rows in a DRAM Download PDF

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USRE36180E
USRE36180E US08/613,455 US61345596A USRE36180E US RE36180 E USRE36180 E US RE36180E US 61345596 A US61345596 A US 61345596A US RE36180 E USRE36180 E US RE36180E
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row
column
write
read
line
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Hank H. Lim
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Micron Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 

Definitions

  • This invention relates generally to a memory array configuration and more particularly to a memory array configuration that allows simultaneous read and refresh of the memory cells in the array.
  • DRAM dynamic random access memory
  • data is stored as a logic one or zero by the presence or absence of charge on a capacitor within an individual memory cell. After the data has been stored as charge on the capacitor, the charge gradually leaks off and the data is corrupted. Therefore, a "refresh" cycle must be performed to maintain the integrity of the data.
  • the array is typically placed in a read mode to obtain the present data stored in a row of memory cells. Subsequently, this data is used as new input data that is re-written into the row of memory cells, thus maintaining the stored data.
  • An important aspect of the refresh cycle of prior art DRAMs is that a normal read operation must be performed on the row that is being refreshed. No other operation involving a different row in the array can occur simultaneously during the read operation.
  • FIG. 1 A functional block diagram of a typical DRAM, the MT4C4003 1 megabit ⁇ 4 DRAM manufactured by Micron Technology, Inc. of Boise, Id., is shown in FIG. 1.
  • the DRAM memory contains approximately 4 megabits organized into four 1 megabit memory arrays 10A-10D.
  • Circuit block 50 includes sense amplifiers coupled to each column within the memory array to transform charge on the capacitor in the memory cell into a valid logic one or zero.
  • each bit in one of the four memory arrays is uniquely addressed through twenty address bits that are entered ten bits (A0-A9) at a time.
  • the RAS signal row address strobe
  • the CAS signal column address strobe
  • a read or write cycle is initiated with the WE signal (write enable).
  • the four data inputs/outputs (DQ1-DQ4) are routed through four pins using a common input/output bus controlled by the WE signal and an OE signal (output enable).
  • a third, "hidden" refresh cycle automatically and internally refreshes the data sequentially in the memory arrays.
  • the hidden refresh cycle is initiated by an appropriate combination of the RAS and CAS signals without specifying an address.
  • none of the three refresh cycles allows the user of the DRAM to accomplish any other functions involving different rows within the array while the combination read/refresh cycles are being performed.
  • a need remains for a memory array configuration that allows a simultaneous read cycle of the memory cells in one row of the memory array and a refresh cycle of the memory cells in another row of the memory array to decrease access time to the stored data.
  • Another object of the invention is to provide a memory array configuration capable of a read operation on one row of the array while performing a simultaneous refresh operation on a different row within the array.
  • a memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells includes M rows and N columns of memory cells arranged in a folded architecture. Each row is arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column. Each memory cell in the top half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective first write row line, and a read row node coupled to a respective read row line.
  • Each memory cell in the bottom half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective second write row line, and a read row node coupled to a respective read row line.
  • a row of N/2 charge sensing amplifiers each has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column.
  • a row of N current/voltage sensing amplifiers each has an input coupled to one of the read column lines and an output for providing a digital signal.
  • one of the entire rows of memory cells is read-selected, which transfers charge in the memory cells to the respective read column node and read column line.
  • the current/voltage sensing amplifiers respectively coupled to the read column node of each of the memory cells transforms the charge into a valid logic signal to complete a normal read operation.
  • each of the write column lines is normalized to a reference level that is halfway between the logic one and zero charge levels.
  • a second half-row of memory cells is write-selected, which transfers charge in the memory cells to the respective write column node and write column line.
  • a pair of write column lines contains a charge from the memory cell, and the other write column line in the pair retains the reference level.
  • the charge amplifiers force complementary valid logic levels on each successive pair of write column lines responsive to the charge difference in the write column lines to simultaneously refresh the second half-row while the first half-row is being read.
  • the first and second half-rows are entirely separate and need not be adjacent in the array.
  • FIG. 1 is a functional block diagram of a typical DRAM
  • FIG. 2 is a block diagram of a memory array configuration of the present invention
  • FIG. 3 is a more detailed block/schematic diagram of the memory array of FIG. 2;
  • FIG. 4 is a schematic diagram of a prior art charge sensing amplifier suitable for use in the present invention.
  • FIG. 5 is a schematic diagram of a prior art current/voltage sensing amplifier suitable for use in the present invention.
  • a memory array 10 configuration of memory cells 20 that allows simultaneous read and refresh of the memory cells includes M rows R1-RM (only the first three rows are depicted) and N columns of memory cells C1-CN (only the first six columns are depicted).
  • the numbers M and N are integers greater than 1, according to the size of the memory array 10 required. For example, in the 4 megabit DRAM of FIG. 1, M and N are both equal to 1024.
  • the array contains a write column line, designated WC, corresponding to each column and a read column line, designated RC, corresponding to each column.
  • the array contains a read row line, designated RR, corresponding to each row.
  • each row contains two write row lines, designated WRA and WRB, corresponding to each row.
  • Each row R1-RM is arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column C1, C3, . . . CN-1, and a bottom half-row of N/2 memory cells corresponding to each even-numbered column C2, C4, . . . CN in a folded architecture.
  • each of the memory cells 20 comprises a non-destructive read two-port type memory cell.
  • Each memory cell in the top half-row has a write column node coupled to the respective write column line WC, a read column node coupled to the respective read column line RC, a write row node coupled to the respective first write row line WRA, and a read row node coupled to the respective read row line RR.
  • Each memory cell in the bottom half-row has a write column node coupled to the respective write column line WC, a read column node coupled to the respective read column line RC, a write row node coupled to the respective second write row line WRB, and a read row node coupled to the respective read row line RR.
  • a row of N/2 charge sensing amplifiers 22 has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column.
  • a row of N current/voltage sensing amplifiers 24 in circuit block 50 has an input coupled to one of the read column lines and an output 28 for transforming the charge on the read column line into a valid digital signal.
  • the row of N current/voltage sensing amplifiers 24 sense the voltage drop across (or the current flow through) a row of N P-channel pull-up transistors 26.
  • a charge sensing amplifier 22 suitable for use in the present invention includes a differential strobe input for selectively enabling and disabling charge amplification. Taking the STROBE signal to a logic one enables the amplification of the charge sensing amplifier 22.
  • Amplifier 22 includes first and second P-channel transistors 42 and 43. The sources of transistors 42 and 43 are coupled together and to the positive supply voltage, VCC, typically equal to five volts, through the P-channel strobe transistor 41. The P-channel strobe transistor 41 is energized with an inverted STROBE signal.
  • Amplifier 22 further includes third and fourth N-channel transistors 44 and 45.
  • the sources of transistors 44 and 45 are coupled together and to a negative supply voltage or ground (GND), through the N-channel strobe transistor 46.
  • the N-channel strobe transistor 46 is energized with a non-inverted STROBE signal.
  • the drains of the first and third transistors 42 and 44 and the gates of the second and fourth transistors 43 and 45 are coupled together to form the first input, WC1.
  • the drains of the second and fourth transistors 43 and 45 and the gates of the first and third transistors 42 and 44 are coupled together to form the second input, WC2.
  • small changes in charge on the word column lines establish a small positive or negative voltage differential across the inputs to the charge sensing amplifier 22.
  • the small change is amplified by the positive feedback configuration of the amplifier, which ultimately establishes a full, valid logic level at the inputs.
  • a logic one appears at the input that was originally slightly more positive than the other input, and, conversely, a logic zero appears at the input that was originally slightly more negative than the other input.
  • a current/voltage sensing amplifier 24 suitable for use in the present invention includes a differential load formed by P-channel transistors 31 and 32.
  • the gate and drain of transistor 31 are coupled together to form a first node and the drain of transistor 32 forms a second nodes.
  • First and second N-channel transistors 33 and 34 form a differential voltage amplifier wherein the sources are coupled together and receive a bias current provided by N-channel transistor 35.
  • the drains of the first and second transistors 33 and 34 are respectively coupled to the first and second nodes of the differential load 31, 32 to provide gain for the amplifier 24.
  • the gate of the first transistor 33 forms the input, RC
  • the drain of the second transistor 34 forms the output 28
  • the gate of the second transistor 34 is coupled to a reference voltage source, VREF, which can be between VCC-VT and VCC/2.
  • VREF reference voltage source
  • a read operation is conventionally performed by read-selecting an entire row and reading data out at the output 28 of the voltage sensing amplifiers 24.
  • Read-selection of one of the entire row of memory cells is typically accomplished by coupling the read row line RR of the entire row to a logic low to couple charge from the memory cell 20 to the respective read column line RC.
  • the respective write row lines WRA or WRB are coupled to a logic low to prevent new data from being read into the memory cells and corrupting the data during the read operation.
  • the polarity of the read and write row lines is typically taken low for enabling the reading of data and preventing the writing of data. However, these polarities may be different in some types of dual-port memory cells.
  • each of the write column lines is normalized to a reference level, usually VCC/2, or 2.5 volts.
  • a second half-row of memory cells is write-selected in order to share stored charge in the memory cell with a corresponding write column line.
  • Write-selection of one of the half-rows of memory cells is typically accomplished by coupling the write row line WRA or WRB to a logic high. Thus, a small incremental voltage is produced on a pair of write column lines.
  • One of the pair of write column lines remains at the reference level, while the other of the pair is slightly more negative or positive depending upon the polarity of the data in the memory cell 20.
  • the charge sensing amplifiers 22 coupled between the pair of write column lines force complementary valid logic levels on successive pairs of write column lines responsive to the charge difference in the write column lines.
  • the charge sensing amplifiers are enabled through the STROBE signal during the simultaneous read and refresh operation. Once a valid logic level is established, this level restores the data in the memory cell through the write column node of the memory cell 20.
  • the present invention allows the user to read an entire row while selecting another half-row to refresh, it is apparent that the same row can be read and refreshed.
  • each of the write column lines are normalized to the reference level during the read operation.
  • the current half-row of memory cells cannot be refreshed until the current/voltage sense amplifiers 24 settle. Therefore, the refresh cycle is delayed for a time to permit the current/voltage sense amplifiers to settle.
  • the same half-row of memory cells is write-selected to share stored charge with the write column line.
  • the charge sensing amplifiers 22 are enabled which forces complementary valid logic levels on the successive pairs of write column lines responsive to the charge difference in the write column lines. The same half-row is therefore refreshed after completing a read operation.

Abstract

A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells includes M rows and N columns of memory cells, each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column. Each memory cell in the top half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective first write row line, and a read row node coupled to a respective read row line. Each memory cell in the bottom half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective second write row line, and a read row node coupled to a respective read row line. A row of N/2 charge sensing amplifiers each has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column. A row of N current/voltage sensing amplifiers each has an input coupled to one of the read column lines and an output for providing a digital signal.

Description

BACKGROUND OF THE INVENTION
This invention relates generally to a memory array configuration and more particularly to a memory array configuration that allows simultaneous read and refresh of the memory cells in the array.
In a dynamic random access memory ("DRAM"), data is stored as a logic one or zero by the presence or absence of charge on a capacitor within an individual memory cell. After the data has been stored as charge on the capacitor, the charge gradually leaks off and the data is corrupted. Therefore, a "refresh" cycle must be performed to maintain the integrity of the data. To refresh data in a memory array, the array is typically placed in a read mode to obtain the present data stored in a row of memory cells. Subsequently, this data is used as new input data that is re-written into the row of memory cells, thus maintaining the stored data. An important aspect of the refresh cycle of prior art DRAMs is that a normal read operation must be performed on the row that is being refreshed. No other operation involving a different row in the array can occur simultaneously during the read operation.
A functional block diagram of a typical DRAM, the MT4C4003 1 megabit×4 DRAM manufactured by Micron Technology, Inc. of Boise, Id., is shown in FIG. 1. The DRAM memory contains approximately 4 megabits organized into four 1 megabit memory arrays 10A-10D. Circuit block 50 includes sense amplifiers coupled to each column within the memory array to transform charge on the capacitor in the memory cell into a valid logic one or zero. During read and write cycles, each bit in one of the four memory arrays is uniquely addressed through twenty address bits that are entered ten bits (A0-A9) at a time. The RAS signal (row address strobe) latches the first ten bits and the CAS signal (column address strobe) latches the latter ten bits. A read or write cycle is initiated with the WE signal (write enable). The four data inputs/outputs (DQ1-DQ4) are routed through four pins using a common input/output bus controlled by the WE signal and an OE signal (output enable).
In the DRAM of FIG. 1, three types of refresh cycles are available. Two of the cycles involve a specific address provided by the user, along with appropriate RAS and/or CAS signals. A third, "hidden" refresh cycle automatically and internally refreshes the data sequentially in the memory arrays. The hidden refresh cycle is initiated by an appropriate combination of the RAS and CAS signals without specifying an address. However, none of the three refresh cycles allows the user of the DRAM to accomplish any other functions involving different rows within the array while the combination read/refresh cycles are being performed.
Accordingly, a need remains for a memory array configuration that allows a simultaneous read cycle of the memory cells in one row of the memory array and a refresh cycle of the memory cells in another row of the memory array to decrease access time to the stored data.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to improve access time to stored data within a memory array.
Another object of the invention is to provide a memory array configuration capable of a read operation on one row of the array while performing a simultaneous refresh operation on a different row within the array.
According to the present invention, a memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells includes M rows and N columns of memory cells arranged in a folded architecture. Each row is arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column. Each memory cell in the top half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective first write row line, and a read row node coupled to a respective read row line. Each memory cell in the bottom half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective second write row line, and a read row node coupled to a respective read row line. A row of N/2 charge sensing amplifiers each has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column. A row of N current/voltage sensing amplifiers each has an input coupled to one of the read column lines and an output for providing a digital signal.
In operation, one of the entire rows of memory cells is read-selected, which transfers charge in the memory cells to the respective read column node and read column line. The current/voltage sensing amplifiers respectively coupled to the read column node of each of the memory cells transforms the charge into a valid logic signal to complete a normal read operation. Simultaneously during the read operation, each of the write column lines is normalized to a reference level that is halfway between the logic one and zero charge levels. A second half-row of memory cells is write-selected, which transfers charge in the memory cells to the respective write column node and write column line. In the present memory array configuration, a pair of write column lines contains a charge from the memory cell, and the other write column line in the pair retains the reference level. Therefore, the charge amplifiers force complementary valid logic levels on each successive pair of write column lines responsive to the charge difference in the write column lines to simultaneously refresh the second half-row while the first half-row is being read. The first and second half-rows are entirely separate and need not be adjacent in the array.
The foregoing and other objects, features and advantages of the invention are more readily apparent from the following detailed description of a preferred embodiment of the invention that proceeds with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a functional block diagram of a typical DRAM;
FIG. 2 is a block diagram of a memory array configuration of the present invention;
FIG. 3 is a more detailed block/schematic diagram of the memory array of FIG. 2;
FIG. 4 is a schematic diagram of a prior art charge sensing amplifier suitable for use in the present invention; and
FIG. 5 is a schematic diagram of a prior art current/voltage sensing amplifier suitable for use in the present invention.
DETAILED DESCRIPTION
Referring now to FIG. 2, a memory array 10 configuration of memory cells 20 that allows simultaneous read and refresh of the memory cells includes M rows R1-RM (only the first three rows are depicted) and N columns of memory cells C1-CN (only the first six columns are depicted). The numbers M and N are integers greater than 1, according to the size of the memory array 10 required. For example, in the 4 megabit DRAM of FIG. 1, M and N are both equal to 1024. As in most dual-port memory cell arrays, the array contains a write column line, designated WC, corresponding to each column and a read column line, designated RC, corresponding to each column. Similarly, the array contains a read row line, designated RR, corresponding to each row. However, unlike most dual-port memory cell arrays, each row contains two write row lines, designated WRA and WRB, corresponding to each row.
Each row R1-RM is arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column C1, C3, . . . CN-1, and a bottom half-row of N/2 memory cells corresponding to each even-numbered column C2, C4, . . . CN in a folded architecture. In the present invention, it is desirable that each of the memory cells 20 comprises a non-destructive read two-port type memory cell. Each memory cell in the top half-row has a write column node coupled to the respective write column line WC, a read column node coupled to the respective read column line RC, a write row node coupled to the respective first write row line WRA, and a read row node coupled to the respective read row line RR. Each memory cell in the bottom half-row has a write column node coupled to the respective write column line WC, a read column node coupled to the respective read column line RC, a write row node coupled to the respective second write row line WRB, and a read row node coupled to the respective read row line RR.
Referring now to FIG. 3, the first four columns C1-C4 of the array 10 are depicted and the first two rows of the array are depicted. Each half-row is labeled. For example, the first row is labeled R1A and R1B designating the top and bottom half-rows. A row of N/2 charge sensing amplifiers 22 has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column. A row of N current/voltage sensing amplifiers 24 in circuit block 50 has an input coupled to one of the read column lines and an output 28 for transforming the charge on the read column line into a valid digital signal. The row of N current/voltage sensing amplifiers 24 sense the voltage drop across (or the current flow through) a row of N P-channel pull-up transistors 26.
Referring now to FIG. 4, a charge sensing amplifier 22 suitable for use in the present invention includes a differential strobe input for selectively enabling and disabling charge amplification. Taking the STROBE signal to a logic one enables the amplification of the charge sensing amplifier 22. Amplifier 22 includes first and second P- channel transistors 42 and 43. The sources of transistors 42 and 43 are coupled together and to the positive supply voltage, VCC, typically equal to five volts, through the P-channel strobe transistor 41. The P-channel strobe transistor 41 is energized with an inverted STROBE signal. Amplifier 22 further includes third and fourth N- channel transistors 44 and 45. The sources of transistors 44 and 45 are coupled together and to a negative supply voltage or ground (GND), through the N-channel strobe transistor 46. The N-channel strobe transistor 46 is energized with a non-inverted STROBE signal. The drains of the first and third transistors 42 and 44 and the gates of the second and fourth transistors 43 and 45 are coupled together to form the first input, WC1. The drains of the second and fourth transistors 43 and 45 and the gates of the first and third transistors 42 and 44 are coupled together to form the second input, WC2.
In operation, small changes in charge on the word column lines establish a small positive or negative voltage differential across the inputs to the charge sensing amplifier 22. The small change is amplified by the positive feedback configuration of the amplifier, which ultimately establishes a full, valid logic level at the inputs. A logic one appears at the input that was originally slightly more positive than the other input, and, conversely, a logic zero appears at the input that was originally slightly more negative than the other input.
Referring now to FIG. 5, a current/voltage sensing amplifier 24 suitable for use in the present invention includes a differential load formed by P- channel transistors 31 and 32. The gate and drain of transistor 31 are coupled together to form a first node and the drain of transistor 32 forms a second nodes. First and second N- channel transistors 33 and 34 form a differential voltage amplifier wherein the sources are coupled together and receive a bias current provided by N-channel transistor 35. The drains of the first and second transistors 33 and 34 are respectively coupled to the first and second nodes of the differential load 31, 32 to provide gain for the amplifier 24. The gate of the first transistor 33 forms the input, RC, the drain of the second transistor 34 forms the output 28, and the gate of the second transistor 34 is coupled to a reference voltage source, VREF, which can be between VCC-VT and VCC/2. The gates of transistors 33 and 34 are interchangeable, but the polarity of the output 28 is then inverted.
Referring back to FIG. 3, a read operation is conventionally performed by read-selecting an entire row and reading data out at the output 28 of the voltage sensing amplifiers 24. Read-selection of one of the entire row of memory cells is typically accomplished by coupling the read row line RR of the entire row to a logic low to couple charge from the memory cell 20 to the respective read column line RC. The respective write row lines WRA or WRB are coupled to a logic low to prevent new data from being read into the memory cells and corrupting the data during the read operation. The polarity of the read and write row lines is typically taken low for enabling the reading of data and preventing the writing of data. However, these polarities may be different in some types of dual-port memory cells.
Simultaneously, during the reading operation of the first half-row of memory cells, another half-row is write-selected in order to refresh the data in the memory cells. During a read operation, each of the write column lines is normalized to a reference level, usually VCC/2, or 2.5 volts. A second half-row of memory cells is write-selected in order to share stored charge in the memory cell with a corresponding write column line. Write-selection of one of the half-rows of memory cells is typically accomplished by coupling the write row line WRA or WRB to a logic high. Thus, a small incremental voltage is produced on a pair of write column lines. One of the pair of write column lines remains at the reference level, while the other of the pair is slightly more negative or positive depending upon the polarity of the data in the memory cell 20. The charge sensing amplifiers 22 coupled between the pair of write column lines force complementary valid logic levels on successive pairs of write column lines responsive to the charge difference in the write column lines. The charge sensing amplifiers are enabled through the STROBE signal during the simultaneous read and refresh operation. Once a valid logic level is established, this level restores the data in the memory cell through the write column node of the memory cell 20.
Although the present invention allows the user to read an entire row while selecting another half-row to refresh, it is apparent that the same row can be read and refreshed. As before, each of the write column lines are normalized to the reference level during the read operation. However, the current half-row of memory cells cannot be refreshed until the current/voltage sense amplifiers 24 settle. Therefore, the refresh cycle is delayed for a time to permit the current/voltage sense amplifiers to settle. After the current/voltage sensing amplifiers 24 have settled, the same half-row of memory cells is write-selected to share stored charge with the write column line. The charge sensing amplifiers 22 are enabled which forces complementary valid logic levels on the successive pairs of write column lines responsive to the charge difference in the write column lines. The same half-row is therefore refreshed after completing a read operation.
Having described and illustrated the principles of the invention in a preferred embodiment thereof, it is apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. For example, many other memory array architectures such as folded, non-folded, and segmented architectures can be adapted to contain the simultaneous refresh feature of the present invention. I therefore claim all modifications and variations coming within the spirit and scope of the following claims.

Claims (21)

I claim:
1. A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells comprising:
two or more rows and two or more columns of memory cells;
a write column line corresponding to each column of memory cells;
a read column line corresponding to each column of memory cells;
first and second write row lines corresponding to each row of memory cells;
a read row line corresponding to each row of memory cells;
each memory cell in the array being coupled to the respective write column line, read column line, and read a row line;
each row of memory cells being arranged into a top half-row of memory cells corresponding to each odd-numbered column of memory cells, and a bottom half-row of memory cells corresponding to each even-numbered column of memory cells;
each memory cell in the top half-row being coupled to the respective first write row line;
each memory cell in the bottom half-row being coupled to the respective second write row line;
charge sensing means coupled to each successive pair of write column lines; and
current/voltage sensing means coupled to each read column line.
2. A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells comprising:
M rows and N columns of memory cells, wherein M and N are integers greater than 1;
a write column line corresponding to each column;
a read column line corresponding to each column;
first and second write row lines corresponding to each row;
a read row line corresponding to each row;
each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column;
each memory cell in the top half-row having a write column node coupled to the respective write column line, a read column node coupled to the respective read column line, a write row node coupled to the respective first write row line, and a read row node coupled to the respective read row line;
each memory cell in the bottom half-row having a write column node coupled to the respective write column line, a read column node coupled to the respective read column line, a write row node coupled to the respective second write row line, and a read row node coupled to the respective read row line;
a row of N/2 charge sensing amplifiers having a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column; and
a row of N current/voltage sensing amplifiers having an input coupled to one of the read column lines and an output for providing a digital signal.
3. A memory array configuration as in claim 2 in which each of the memory cells comprises a non-destructive read memory cell.
4. A memory array configuration as in claim 2 in which at least one of the charge sensing amplifier comprises means coupled to a strobe input for selectively enabling and disabling the amplification of the charge sensing amplifier.
5. A memory array configuration as in claim 2 in which at least one of the charge sensing amplifiers comprises:
first and second transistors of a first type each having a source, a drain, and a gate, the sources being coupled together and to a first source of supply voltage; and
third and fourth transistors of a second type each having a source, a drain, and a gate, the sources being coupled together and to a second source of supply voltage,
wherein the drains of the first and third transistors and the gates of the second and fourth transistors are coupled together to form the first input, and
the drains of the second and fourth transistors and the gates of the first and third transistors are coupled together to form the second input.
6. A memory array configuration as in claim 5 comprising:
means for selectively coupling the coupled sources of the first and second transistors to the first source of supply voltage responsive to an inverted strobe signal; and
means for selectively coupling the coupled sources of the third and fourth transistors to the second source of supply voltage responsive to a strobe signal.
7. A memory array configuration as in claim 2 in which at least one of the current/voltage amplifiers comprises:
a differential load having first and second nodes; and
first and second transistors each having a source, a drain, and a gate, the sources being coupled together and to a source of bias current,
wherein the drains of the first and second transistors are respectively coupled to the first and second nodes of the differential load, and
the gate of the first transistor forms the input, the drain of the second transistor forms the output, and the gate of the second transistor is coupled to a reference voltage source.
8. In a memory array including two or more rows and two or more columns of memory cells, a write column line corresponding to each column, a read column line corresponding to each column, and a read row line corresponding to each row, wherein each memory cell in the array is coupled to the respective write column line, read column line, and read row line, a method for allowing simultaneous read and refresh of different rows in the array, the method comprising the steps of:
providing first and second write row lines;
arranging each row into a top half-row of memory cells corresponding to each odd-numbered column and a bottom half-row of memory cells corresponding to each even-numbered column;
coupling each memory cell in the top half-row to the respective first write row line;
coupling each memory cell in the bottom half-row to the respective second write row line;
charge sensing each successive pair of write column lines; and
current/voltage sensing each read column line;
read-selecting an entire row of memory cells;
reading data out of the memory cells in the read-selected row;
normalizing each of the write column lines to a reference level;
write-selecting, simultaneously with the step of read-selecting, another of the half-rows of memory cells from a row different than the read-selected row in order to refresh the write-selected half-row; and
forcing complementary valid logic on successive pairs of write column lines responsive to the charge difference in the write column lines.
9. In a memory array having M rows and N columns of memory cells, wherein M and N are integers greater than 1, a write column line corresponding to each column, a read column line corresponding to each column, a write row line corresponding to each row, a read row line corresponding to each row, a method for allowing simultaneous read and refresh of the memory cells, the method comprising;
providing a second write row line for each row of memory cells;
arranging each row into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column;
coupling a write row node of each memory cell in the top half-row to a respective first write row line;
coupling a write row node of each memory cell in the bottom half-row to the respective second write row line;
coupling a write column line, a read column line, and a read row line of each memory cell in each row to the respective column and row line;
providing a row of N/2 charge sensing amplifiers having first and second inputs;
coupling the first input of each of the charge sensing amplifiers to an odd-numbered write column line and the second input of each of the charge sensing amplifiers coupled to a next even-numbered write column;
providing a row of N current/voltage sensing amplifiers having an input and an output;
coupling the input of each of the current/voltage sensing amplifiers to one of the read column lines;
providing a digital signal at the output of each of the current/voltage sensing amplifiers;
read-selecting one of the entire rows of memory cells;
reading data out at the output of the current/voltage sensing amplifiers respectively coupled to a read column node of each of the memory cells;
normalizing each of the write column lines to a reference level;
write-selecting, simultaneously with the step of read-selecting, another of the half-rows of memory cells from a row different than the read-selected row to share stored charge in the memory cell with a corresponding write column line to refresh the write-selected half-row; and
forcing complementary valid levels on successive pairs of write column lines responsive to the charge difference in the write column lines.
10. A method for allowing simultaneous reading and refresh of memory cells in a memory array as in claim 9 in which the step of read-selecting one of the half-rows of memory cells comprises the steps of:
coupling the read row line to a logic low; and
simultaneously maintaining the write row line at a logic low.
11. A method for allowing simultaneous reading and refresh of memory cells in a memory array as in claim 9 in which the step of write-selecting another of the half-rows of memory cells comprises the step of coupling the write row line to a logic high.
12. A method for allowing simultaneous reading and refresh of memory cells in a memory as in claim 9 in which the step of forcing complementary valid logic levels on successive pairs of write column lines comprises the step of enabling amplification in the charge sensing amplifiers with a strobe signal. .Iadd.
13. A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells comprising:
at least two rows and at least two columns of memory cells;
a write column line for each column of memory cells;
a read column line for each column of memory cells;
first and second write row lines for each row of memory cells;
a read row line for each row of memory cells;
each memory cell in the array being coupled to an associated write column line, read column line, and read row line;
each row of memory cells being arranged into a first set of memory cells corresponding to a first set of columns of memory cells, and a second set of memory cells corresponding to a second set of columns of memory cells;
the first write row line of each row being coupled to each memory cell in the first set of memory cells of the row;
the second write row line of each row being coupled to each memory cell in the second set of memory cells of the row;
at least one charge sensing device coupled to a write column line of the first column set and a write column line of the second column set; and
a current/voltage sensing device coupled to each read column line..Iaddend..Iadd.14. A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells comprising:
M rows and N columns of memory cells, wherein M and N are integers greater than 1;
a write column line for each memory cell column;
a read column line for each memory cell column;
first and second write row lines for each memory cell row;
a read row line for each memory cell row;
each row being arranged into a first set of N/2 memory cells corresponding to a first set of columns and a second set of N/2 memory cells corresponding to a second set of columns;
each memory cell in a first set of cells having a write column node coupled to an associated write column line, a read column node coupled to an associated read column line, a write row node coupled to an associated first write row line, and a read row node coupled to an associated read row line;
each memory cell in a second set of cells having a write column node coupled to an associated write column line, a read column node coupled to an associated read column line, a write row node coupled to an associated second write row line, and a read row node coupled to an associated read row line;
a group of N/2 charge sensing amplifiers each having a first input coupled to a write column line of the first column set and second input coupled to a write column line of the second column set; and
a group of N current/voltage sensing amplifiers each having an input coupled to a read column line and an output for providing a digital signal..Iaddend..Iadd.15. A memory array configuration as in claim 14 in which each of the memory cells comprises a non-destructive read memory
cell..Iaddend..Iadd.16. A memory array configuration as in claim 14 in which at least one of the charge sensing amplifiers is coupled to a strobe input for selectively enabling and disabling the amplification of that charge sensing amplifier..Iaddend..Iadd.17. A memory array configuration as in claim 14 in which at least one of the charge sensing amplifiers comprises:
first and second transistors of a first type each having a source, a drain, and a gate, the sources being coupled together and to a first source of supply voltage; and
third and fourth transistors of a second type each having a source, a drain, and a gate, the sources being coupled together and to a second source of supply voltage,
wherein the drains of the first and third transistors and the gates of the second and fourth transistors are coupled together to form the first input, and
the drains of the second and fourth transistors and the gates of the first and third transistors are coupled together to form the second input..Iaddend..Iadd.18. A memory array configuration as in claim 17 comprising:
means for selectively coupling the coupled sources of the first and second transistors to the first source of supply voltage responsive to an inverted strobe signal; and
means for selectively coupling the coupled sources of the third and fourth transistors to the second source of supply voltage responsive to a strobe
signal..Iaddend..Iadd.19. A memory array configuration as in claim 14 in which at least one of the current/voltage amplifiers comprises:
a differential load having first and second nodes; and
first and second transistors each having a source, a drain, and a gate, the sources being coupled together and to a source of bias current,
wherein the drains of the first and second transistors are respectively coupled to the first and second nodes of the differential load, and
the gate of the first transistor forms the input, the drain of the second transistor forms the output, and the gate of the second transistor is
coupled to a reference voltage source..Iaddend..Iadd.20. In a memory array including at least two rows and at least two columns of memory cells, a write column line corresponding to each column, a read column line corresponding to each column, and a read row line corresponding to each row, wherein each memory cell in the array is coupled to its respective write column line, read column line, and read row line, a method for allowing simultaneous read and refresh of cells of different rows in the array, the method comprising the steps of:
providing first and second write row lines for each row;
arranging each row into a first set of memory cells corresponding to a first set of columns and a second set of memory cells corresponding to a second set of columns;
coupling the first write row line for each row to each memory cell in the first set of memory cells for the row;
coupling the second write row line for each row to each memory cell in the second set of memory cells for the row;
charge sensing paired write column lines, one from each of the first and second sets of columns;
current/voltage sensing each read column line;
read-selecting an entire row of memory cells;
reading data out of the memory cells in the read-selected row;
normalizing each of the write column lines to a reference level;
write-selecting, substantially simultaneously with the step of read-selecting, the first or second set of memory cells from a row different than the read-selected row in order to refresh the write-selected set of memory cells; and
forcing complementary valid logic on the paired write column lines responsive to the charge difference in the write column lines of the pair..Iaddend..Iadd.21. In a memory array having M rows and N columns of memory cells, wherein M and N are integers greater than 1, a write column line corresponding to each column, a read column line corresponding to each column, a write row line corresponding to each row, a read row line corresponding to each row, a method for allowing simultaneous read and refresh of first and second groups of memory cells, the method comprising:
providing a second write row line for each row of memory cells;
arranging each cell row into a first set of N/2 memory cells corresponding to a first set of columns and a second set of N/2 memory cells corresponding to a second set of columns;
coupling a write row node of each memory cell in a first set of cells to a first write row line for that row;
coupling a write row node of each memory cell in a second set of cells to a second write row line for that row;
coupling a write column node, a read column node, and a read row node of each memory cell in each row to its associated respective write column line, read column line and read row line;
providing a group of N/2 charge sensing amplifiers having first and second inputs;
coupling the first input of each of the charge sensing amplifiers to a write column line of the first column set and the second input of each of the charge sensing amplifiers to a write column line of the second column set;
providing a group of N current/voltage sensing amplifiers having an input and an output;
coupling the input of each of the current/voltage sensing amplifiers to one of the read column lines;
read-selecting one of the entire rows of memory cells;
reading data out at the output of the current/voltage sensing amplifiers;
normalizing each of the write column lines to a reference level;
write-selecting, simultaneously with the step of read-selecting, a first set or a second set of memory cells from a row different than the read-selected row to share stored charge in the memory cell with a corresponding write column line to refresh the write-selected set; and
forcing complementary valid levels on the paired write column lines responsive to the charge difference in the write column
lines..Iaddend..Iadd.22. A method for allowing simultaneous reading and refresh of memory cells in a memory array as in claim 21 in which read-selecting one of the sets of memory cells comprises the steps of:
coupling the read row line to a logic low; and
simultaneously maintaining the write row line at a logic low..Iaddend..Iadd.23. A method for allowing simultaneous reading and refresh of memory cells in a memory array as in claim 21 in which write-selecting another of the sets of memory cells comprises coupling the write row line to a logic high..Iaddend..Iadd.24. A method for allowing simultaneous reading and refresh of memory cells in a memory as in claim 21 in which forcing complementary valid logic levels on paired write column lines comprises the step of enabling amplification in the charge
sensing amplifiers with a strobe signal..Iaddend..Iadd.25. A memory cell array configuration providing the capability for simultaneous respective read and refresh of a first group and a second group of memory cells in the array, comprising:
at least two rows and at least two columns of cells, each row comprising a first set and a second set of cells;
a read column line for each column of cells;
a write column line for each column of cells;
a read row line for each row of cells; and
a first write row line for a first cell set of each row and a second write row line for a second cell set of each row..Iaddend..Iadd.26. A memory cell array configuration providing the capability of simultaneous, respective read and refresh of first and second groups of memory cells in the array located on respective first and second selected rows of the array, the configuration comprising:
at least two rows and at least two columns of memory cells;
a charge sensing circuit associated with each column of memory cells for sensing charge stored in the memory cells of the associated column;
a current source associated with each column of memory cells; and
a current/voltage sensing circuit associated with each column of memory cells for sensing any current flow through the current source associated with the column indicative of charge stored in the memory cells of the
column..Iaddend..Iadd.27. The memory cell array configuration of claim 26, wherein each charge sensing circuit is coupled to two different columns of memory cells..Iaddend..Iadd.28. The memory cell array configuration of claim 26, including one current/voltage sensing circuit for each column of memory cells in the array..Iaddend..Iadd.29. A memory cell array configuration for cell refresh, comprising:
at least one row of memory cells having a write row line associated therewith;
at least two columns of memory cells, each column having a write column line and a read column line associated therewith; and
a charge sensing circuit communicable with write column lines of first and second columns of said at least two columns for sensing charge stored in memory cells of the first and second columns..Iaddend..Iadd.30. A multi-row, multi-column memory array configured for simultaneous access to two memory cells in the same column, comprising:
at least two rows and at least two columns of dual-port memory cells;
a write column line and a read column line for each cell column;
at least one write row line and a read row line for each cell row;
each cell being coupled to a write column line, a read column line, a write row line and a read row line;
charge sensing devices, each coupled to paired write column lines for sensing charge stored in memory cells coupled to the paired write column lines; and
a current/voltage sensing device coupled to each read column line for sensing current along the read column line indicative of charge stored in
memory cells coupled to the read column line..Iaddend..Iadd.31. A multi-row, multi-column memory array configured for simultaneous reading of two memory cells in the same column, comprising:
at least two rows and at least two columns of dual-port memory cells;
a write column line and a read column line for each cell column;
at least one write row line and a read row line for each cell row;
each cell being coupled to a write column line, a read column line, a write row line and a read row line;
charge sensing devices, each coupled to paired write column lines for sensing charge stored in memory cells coupled to the paired write column lines; and
a current/voltage sensing device coupled to each read column line for sensing current along the read column line indicative of charge stored in memory cells coupled to the read column line..Iaddend..Iadd.32. A multi-row, multi-column memory array of dual-port memory cells configured for reading of cells through either port, comprising:
at least two rows and at least two columns of dual-port memory cells;
a write column line and a read column line for each cell column;
at least one write row line and a read row line for each cell row;
each cell being coupled to a write column line, a read column line, a write row line and a read row line;
charge sensing devices, each coupled to paired write column lines for sensing charge stored in memory cells coupled to the paired write column lines; and
a current/voltage sensing device coupled to each read column line for sensing current along the read column line indicative of charge stored in
memory cells coupled to the read column line..Iaddend..Iadd.33. A multi-row, multi-column memory array of dual-port memory cells configured for reading of each cell, comprising:
at least two rows and at least two columns of dual-port memory cells;
a write column line and a read column line for each cell column;
at least one write row line and a read row line for each cell row;
each cell being coupled to a write column line, a read column line, a write row line and a read row line;
charge sensing devices, each coupled to paired write column lines for sensing charge stored in memory cells coupled to the paired write column lines; and
a current/voltage sensing device coupled to each read column line for sensing current along the read column line indicative of charge stored in memory cells coupled to the read column line..Iaddend.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6185132B1 (en) 1998-12-30 2001-02-06 Hyundai Electronics Industries Co., Ltd. Sensing current reduction device for semiconductor memory device and method therefor
US6430098B1 (en) * 2000-05-16 2002-08-06 Broadcom Corporation Transparent continuous refresh RAM cell architecture
US20040037143A1 (en) * 2002-08-22 2004-02-26 Lovett Simon J. High-speed transparent refresh dram-based memory cell
US6859407B1 (en) 2004-01-14 2005-02-22 Infineon Technologies Ag Memory with auto refresh to designated banks
US6941415B1 (en) 2000-08-21 2005-09-06 Micron Technology, Inc. DRAM with hidden refresh
US20110093763A1 (en) * 2008-06-17 2011-04-21 Nxp B.V. Electrical circuit comprising a dynamic random access memory (dram) with concurrent refresh and read or write, and method to perform concurent

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5519655A (en) * 1994-09-29 1996-05-21 Texas Instruments Incorporated Memory architecture using new power saving row decode implementation
US5627791A (en) * 1996-02-16 1997-05-06 Micron Technology, Inc. Multiple bank memory with auto refresh to specified bank
US6104658A (en) * 1996-08-08 2000-08-15 Neomagic Corporation Distributed DRAM refreshing
US6947100B1 (en) * 1996-08-09 2005-09-20 Robert J. Proebsting High speed video frame buffer
US5691951A (en) * 1996-11-04 1997-11-25 Micron Technology, Inc. Staggered row line firing in single ras cycle
US5781483A (en) * 1996-12-31 1998-07-14 Micron Technology, Inc. Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
US5894238A (en) * 1997-01-28 1999-04-13 Chien; Pien Output buffer with static and transient pull-up and pull-down drivers
US5883849A (en) * 1997-06-30 1999-03-16 Micron Technology, Inc. Method and apparatus for simultaneous memory subarray testing
FR2773635B1 (en) * 1998-01-15 2003-01-10 St Microelectronics Sa DEVICE AND METHOD FOR READING REWRITE OF A DYNAMIC LIVE MEMORY CELL
US6242942B1 (en) 1998-11-13 2001-06-05 Integrated Device Technology, Inc. Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics
US6091260A (en) * 1998-11-13 2000-07-18 Integrated Device Technology, Inc. Integrated circuit output buffers having low propagation delay and improved noise characteristics
US6356102B1 (en) 1998-11-13 2002-03-12 Integrated Device Technology, Inc. Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals
US6201729B1 (en) 1999-02-01 2001-03-13 Cisco Technology Inc. DRAM hidden row access method and apparatus
US6256249B1 (en) * 1999-12-30 2001-07-03 Cypress Semiconductor Corp. Method for hidden DRAM refresh
US6587936B1 (en) 2001-02-21 2003-07-01 Cisco Technology, Inc. Multi-bank memory access method and apparatus
US6549476B2 (en) 2001-04-09 2003-04-15 Micron Technology, Inc. Device and method for using complementary bits in a memory array
US7320100B2 (en) * 2003-05-20 2008-01-15 Cray Inc. Apparatus and method for memory with bit swapping on the fly and testing
JP3788804B2 (en) * 2003-05-23 2006-06-21 日本電信電話株式会社 Parallel processing apparatus and parallel processing method
US8245087B2 (en) * 2007-03-26 2012-08-14 Cray Inc. Multi-bit memory error management
JP2009087485A (en) * 2007-10-01 2009-04-23 Elpida Memory Inc Semiconductor device
US9928895B2 (en) * 2016-02-03 2018-03-27 Samsung Electronics Co., Ltd. Volatile memory device and electronic device comprising refresh information generator, information providing method thereof, and refresh control method thereof
US11023171B2 (en) * 2019-07-17 2021-06-01 Micron Technology, Inc. Performing a refresh operation based on a write to read time difference

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3846765A (en) * 1973-02-14 1974-11-05 Monolithic Syst Corp Dynamic cell semiconductor memory with interlace refresh
US4106108A (en) * 1975-08-20 1978-08-08 Honeywell Information Systems Italia Semiconductor dynamic memory and related refreshing system
US4506351A (en) * 1982-06-23 1985-03-19 International Business Machines Corporation One-device random access memory having enhanced sense signal
US4581720A (en) * 1982-09-28 1986-04-08 Fujitsu Limited Semiconductor memory device
US4847809A (en) * 1985-07-10 1989-07-11 Kabushiki Kaisha Toshiba Image memory having standard dynamic RAM chips
US5007002A (en) * 1989-07-11 1991-04-09 Brother Kogyo Kabushiki Kaisha Serial or line printer adapted for use with page describing language
US5093808A (en) * 1987-11-10 1992-03-03 Mosaid, Inc. Folded bitline dynamic ram with reduced shared supply voltages
US5122986A (en) * 1990-11-21 1992-06-16 Micron Technology, Inc. Two transistor dram cell
US5177706A (en) * 1990-03-13 1993-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a plurality of ports
US5253197A (en) * 1989-09-14 1993-10-12 Hitachi, Ltd. Semiconductor associative memory device with current sensing
US5260908A (en) * 1991-04-24 1993-11-09 Kabushiki Kaisha Toshiba Multiport memory device
US5260899A (en) * 1986-11-14 1993-11-09 Seiko Epson Corporation Sense amplifier for semiconductor memory device
US5574729A (en) * 1990-09-29 1996-11-12 Mitsubishi Denki Kabushiki Kaisha Redundancy circuit for repairing defective bits in semiconductor memory device

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3846765A (en) * 1973-02-14 1974-11-05 Monolithic Syst Corp Dynamic cell semiconductor memory with interlace refresh
US4106108A (en) * 1975-08-20 1978-08-08 Honeywell Information Systems Italia Semiconductor dynamic memory and related refreshing system
US4506351A (en) * 1982-06-23 1985-03-19 International Business Machines Corporation One-device random access memory having enhanced sense signal
US4581720A (en) * 1982-09-28 1986-04-08 Fujitsu Limited Semiconductor memory device
US4847809A (en) * 1985-07-10 1989-07-11 Kabushiki Kaisha Toshiba Image memory having standard dynamic RAM chips
US5260899A (en) * 1986-11-14 1993-11-09 Seiko Epson Corporation Sense amplifier for semiconductor memory device
US5093808A (en) * 1987-11-10 1992-03-03 Mosaid, Inc. Folded bitline dynamic ram with reduced shared supply voltages
US5007002A (en) * 1989-07-11 1991-04-09 Brother Kogyo Kabushiki Kaisha Serial or line printer adapted for use with page describing language
US5253197A (en) * 1989-09-14 1993-10-12 Hitachi, Ltd. Semiconductor associative memory device with current sensing
US5177706A (en) * 1990-03-13 1993-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a plurality of ports
US5574729A (en) * 1990-09-29 1996-11-12 Mitsubishi Denki Kabushiki Kaisha Redundancy circuit for repairing defective bits in semiconductor memory device
US5122986A (en) * 1990-11-21 1992-06-16 Micron Technology, Inc. Two transistor dram cell
US5260908A (en) * 1991-04-24 1993-11-09 Kabushiki Kaisha Toshiba Multiport memory device

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6185132B1 (en) 1998-12-30 2001-02-06 Hyundai Electronics Industries Co., Ltd. Sensing current reduction device for semiconductor memory device and method therefor
US6888761B2 (en) 2000-05-16 2005-05-03 Broadcom Corporation Memory device having simultaneous read/write and refresh operations with coincident phases
US6430098B1 (en) * 2000-05-16 2002-08-06 Broadcom Corporation Transparent continuous refresh RAM cell architecture
US6600677B2 (en) 2000-05-16 2003-07-29 Broadcom Corporation Memory circuit capable of simultaneous writing and refreshing on the same column and a memory cell for application in the same
US6717863B2 (en) 2000-05-16 2004-04-06 Broadcom Corporation Transparent continuous refresh RAM cell architecture
US7117299B2 (en) 2000-08-21 2006-10-03 Micron Technology, Inc. DRAM with hidden refresh
US6941415B1 (en) 2000-08-21 2005-09-06 Micron Technology, Inc. DRAM with hidden refresh
US20060013054A1 (en) * 2000-08-21 2006-01-19 Ryan Kevin J DRAM with hidden refresh
US20070011397A1 (en) * 2000-08-21 2007-01-11 Ryan Kevin J Dram with hidden refresh
US6839297B2 (en) 2002-08-22 2005-01-04 Micron Technology, Inc. Method of operating a dynamic random access memory cell
US20050083754A1 (en) * 2002-08-22 2005-04-21 Lovett Simon J. Method of operating a memory cell
US6750497B2 (en) 2002-08-22 2004-06-15 Micron Technology, Inc. High-speed transparent refresh DRAM-based memory cell
US20040037143A1 (en) * 2002-08-22 2004-02-26 Lovett Simon J. High-speed transparent refresh dram-based memory cell
US20060262612A1 (en) * 2002-08-22 2006-11-23 Lovett Simon J Method of operating a memory cell
US7206243B2 (en) 2002-08-22 2007-04-17 Micron Technology, Inc. Method of rewriting a logic state of a memory cell
US7319629B2 (en) 2002-08-22 2008-01-15 Micron Technology, Inc. Method of operating a dynamic random access memory cell
US6859407B1 (en) 2004-01-14 2005-02-22 Infineon Technologies Ag Memory with auto refresh to designated banks
US20110093763A1 (en) * 2008-06-17 2011-04-21 Nxp B.V. Electrical circuit comprising a dynamic random access memory (dram) with concurrent refresh and read or write, and method to perform concurent

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