USRE36311E - Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process - Google Patents

Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process Download PDF

Info

Publication number
USRE36311E
USRE36311E US08/253,151 US25315194A USRE36311E US RE36311 E USRE36311 E US RE36311E US 25315194 A US25315194 A US 25315194A US RE36311 E USRE36311 E US RE36311E
Authority
US
United States
Prior art keywords
iaddend
iadd
region
power transistor
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/253,151
Inventor
Ferruccio Frisina
Giuseppe Ferla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Priority to US08/253,151 priority Critical patent/USRE36311E/en
Application granted granted Critical
Publication of USRE36311E publication Critical patent/USRE36311E/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS

Definitions

  • This invention relates to an integrated high-voltage bipolar power transistor and low-voltage MOS power transistor structure in an emitter switching configuration and to a manufacturing process therefore.
  • Emitter switching is a circuit configuration in which a low-voltage power transistor (typically an MOS transistor) cuts off the emitter current of a high-voltage power transistor (typically a bipolar transistor) in order to switch it off.
  • a low-voltage power transistor typically an MOS transistor
  • a high-voltage power transistor typically a bipolar transistor
  • the object of this invention is to provide a high-voltage bipolar power transistor and a low-voltage MOS power transistor, connected together in the emitter switching configuration, and integrated in a single chip of semiconductor material.
  • the integrated high-voltage bipolar power transistor and vertical low-voltage MOS power transistor structure, in the emitter switching configuration of the invention comprises:
  • the semiconductor layer consists of a first N-type epitaxial layer and a second N-type epitaxial layer grown on it, the first region is located in the first epitaxial layer, in the vicintity of the surface adjacent to the second epitaxial layer, and the second region is located in the second epitaxial layer.
  • the third region can consist of a completely buried layer located astride between the boundary of the first and second epitaxial layer, the body and source regions of the MOS can be located in the second epitaxial layer, in the vicinity of its surface and above the third region.
  • the drain region of the MOS consists substantially of the region between the third region and the aforesaid body regions.
  • an integrated high-voltage bipolar power transistor and horizontal low-voltage MOS power transistor structure in the emitter switching configuration comprises:
  • a first P+ type region constituting the base of the bipolar transistor, located in the layer in the vicinity of its surface, and
  • a second N+ type region constituting the emitter of the bipolar transistor, adjoining the aforesaid first region from below and from the side and adjoining the surface of the layer from above.
  • a third P+ conductivity region in the N- type epitaxial layer and in the vicinity of its surface there is a third P+ conductivity region as well as a fourth and a fifth N+ type region. These latter regions constutute the MOS source and gate regions respectively and being adjacent from below and from the side to the aforesaid third region.
  • the metal coatings of the MOS transistor drain and of the bipolar transistor emitter are interconnected by means of tracks of conductor material.
  • a process for manufacturing an integrated high-voltage bipolar power transistor and vertical low-voltage MOS power transistor structure, in the emitter switching configuration is characterized by the fact that:
  • a second N conductivity epitaxial layer designed to constitute the drain region of the MOS transistor and at the same time automatically form the connection between the drain of the MOS transistor and the emitter of the bipolar transistor, is grown on the first epitaxial layer,
  • the body, the source and the gate of the MOS transistor are then created in the second epitaxial layer, by means of the known processes, in correspondence with the aforesaid buried emitter zone of the bipolar transistor, and
  • a P+ type region which enables the base region of the bipolar transistor to be electrically connected on the surface, is also created at the side of said MOS transistor, by means of the known techniques of oxidation, photomasking, implantation and diffusion.
  • a second P+ type region separated from the first by a region of the epitaxial layer, is created in the epitaxial layer simultaneously to said first region,
  • a fourth and a fifth N+ type region designed to constitute the MOS source and drain region respectively, are created within the second region, and
  • the deposition of tracks of conductor material designed to electrically interconnect the emitter and drain metal coatings is carried out simultaneously to the deposition of the films of conductor material designed to form the gate terminals and the metal coating which ensure the ohmic contact with the MOS source and drain regions and with the base and emitter regions of the bipolar transistor.
  • FIG. 1 is a circuit diagram which shows the equivalent electrical circuit of the 4-terminals integrated structures, which the invention intends to realize;
  • FIGS. 2-7 are diagrammatic sections which show a structure according to the invention, in the vertical MOS power transistor version, during the various stages of the manufacturing process;
  • FIG. 8 is a section which shows the structure obtained at the end of the process referred to in the previous FIGS. 2-7;
  • FIG. 9 is a diagram of the concentrations of the various types of doping agent along a section of the structure of FIG. 7;
  • FIGS. 10-11 are sections which show a structure according to the invention, in the horizontal MOS power transistor version, during the various stages of the manfacturing process.
  • FIG. 12 is a section which shows a schematic representation of the structure obtained at the end of the process referred to in FIGS. 10-11.
  • FIG. 1 shows the equivalent electrical circuit of the 4-terminal integrated structures that the invention intends to provide.
  • This circuit consists of a high-voltage bipolar power transistor T connected by means of its emitter to the drain of a low-voltage MOS power transistor P.
  • a first high resistivity N- conductivity epitaxial layer 2 is grown on an N+ type substrate 1 (FIG. 2).
  • a P+ type region 3 is then obtained, by deposition or implantation and subsequent diffusion, on said layer 2 (FIG. 3).
  • An N+ type region 4 is then obtained by means of the same process (FIG. 4).
  • This is followed by the growth of a second N type epitaxial layer 5 (FIG. 5) and, by the known procedures of oxidation, photomasking, implantation and diffusion, the creation of the P+ type regions 8, which enable the region 3 constituting the base of the bipolar transistor to be connected on the surface (FIG. 6).
  • a low-voltage vertical MOS power transistor and in particular the relative P conductivity body regions 6, N+ type source regions 7 (FIG. 7), the gate 9 and the metal coatings 10, 11 and 14 for ensuring the ohmic contact with the regions 6, 7, 8 and the substrate 1 (FIG. 8) are then created in the area between the two regions 8, according to known procedures.
  • FIG. 8 shows the final structure, as it appears after addition of the terminals C (collector).
  • B base
  • S source
  • G gate
  • the insulating layer 12 of the gate 9 (said gate being connected to the relative terminal by means of the insulated conductor 13).
  • Regions 1, 2, 3 and 4 of the figure constitute, respectively, the collector, the base and the emitter of a bipolar transistor, while region 5 constitutes the drain of the MOS. Said drain is consequently connected directly to the emitter of the bipolar transistor thus forming a structure having as its equivalent circuit the circuit of FIG. 1.
  • the emitter 4 represents a completely buried N+ type active region; by growing a second N type epitaxial layer 5 it is thus possible to connect the drain of the MOS to the emitter 4 of the bipolar transistor,
  • FIG. 9 The profile of the concentration (Co) of the various types of doping agent in the different regions of the structure, along section A--A of FIG. 7, is shown in FIG. 9, where axis x refers to the distance from the upper surface of the structure.
  • the manufacturing process of the integrated structure, in the horizontal MOS power transistor version, includes the following stages.
  • Two P+ type regions 23 and 24 are then created simultaneously on said layer, by the known processes of deposition or implantation and subsequent diffusion, the first of which being destined to act as a base for the bipolar transistor and the second to receive the MOS.
  • an N+ type region 25 which is destined to act as the emitter of the bipolar transistor is created within the region 23, while two N+ type regions 26 and 27 which are destined to act as the source and the drain of the MOS are created within the region 24 (FIG. 11).
  • the aforesaid metal coatings also include the formation of a track 35 for connecting the drain D to the emitter E, so as to achieve the connection of the two transistors in the configuration of FIG. 1.
  • the final structure obtained is provided with 4 terminals, 3 of said terminals being located on one face of the chip and the 4th on the other face.
  • the described process can obviously be used to simultaneously obtain, on the same chip, several pairs of bipolar and MOS transistors having a collector terminal in common and their base contacts, sources and gates connected to three respective common terminals by means of a metal coating carried out on the front of the chip at the end of the process.

Abstract

A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N- epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

Description

This is a divisional of co-pending application Ser. No. 07/288,405 filed on Dec. 21, 1988, now U.S. Pat. No. 5,065,213.
FIELD OF THE INVENTION
This invention relates to an integrated high-voltage bipolar power transistor and low-voltage MOS power transistor structure in an emitter switching configuration and to a manufacturing process therefore.
BACKGROUND OF THE INVENTION
Emitter switching is a circuit configuration in which a low-voltage power transistor (typically an MOS transistor) cuts off the emitter current of a high-voltage power transistor (typically a bipolar transistor) in order to switch it off. This configuration, which up until now was obtained by means of discrete components, offers the following advantages:
it increases the strength of bipolar transistor as far as the possibility of inverted secondary ruptures (ESB) occurring are concerned;
it combines the current and voltage carrying capacity of a piloted transistor and the high speed of a low-voltage transistor;
it enables the system to be piloted directly with linear logic circuits, through the MOS gate.
OBJECT OF THE INVENTION
In view of the advantages that an integrated circuit generally offers, as compared to an analog circuit obtained by means of discrete components, the object of this invention is to provide a high-voltage bipolar power transistor and a low-voltage MOS power transistor, connected together in the emitter switching configuration, and integrated in a single chip of semiconductor material.
SUMMARY OF THE INVENTION
The integrated high-voltage bipolar power transistor and vertical low-voltage MOS power transistor structure, in the emitter switching configuration of the invention comprises:
an N+ type semiconductor substrate,
an overlying semiconductor layer,
a first P type region buried in the aforesaid layer,
a second P type region connecting the first aforesaid region on the surface, the first and second region constituting the base region of the bipolar transistor, and
a third N+ type region adjoining the aforesaid first region from below and constituting the emitter region of the bipolar transistor.
According to the invention, the semiconductor layer consists of a first N-type epitaxial layer and a second N-type epitaxial layer grown on it, the first region is located in the first epitaxial layer, in the vicintity of the surface adjacent to the second epitaxial layer, and the second region is located in the second epitaxial layer. The third region can consist of a completely buried layer located astride between the boundary of the first and second epitaxial layer, the body and source regions of the MOS can be located in the second epitaxial layer, in the vicinity of its surface and above the third region. The drain region of the MOS consists substantially of the region between the third region and the aforesaid body regions. Alternatively an integrated high-voltage bipolar power transistor and horizontal low-voltage MOS power transistor structure, in the emitter switching configuration comprises:
an N+ type semiconductor substrate,
an N- type epitaxial layer grown on the substrate,
a first P+ type region, constituting the base of the bipolar transistor, located in the layer in the vicinity of its surface, and
a second N+ type region, constituting the emitter of the bipolar transistor, adjoining the aforesaid first region from below and from the side and adjoining the surface of the layer from above. According to the invention in the N- type epitaxial layer and in the vicinity of its surface there is a third P+ conductivity region as well as a fourth and a fifth N+ type region. These latter regions constutute the MOS source and gate regions respectively and being adjacent from below and from the side to the aforesaid third region. The metal coatings of the MOS transistor drain and of the bipolar transistor emitter are interconnected by means of tracks of conductor material.
A process for manufacturing an integrated high-voltage bipolar power transistor and vertical low-voltage MOS power transistor structure, in the emitter switching configuration is characterized by the fact that:
a second N conductivity epitaxial layer, designed to constitute the drain region of the MOS transistor and at the same time automatically form the connection between the drain of the MOS transistor and the emitter of the bipolar transistor, is grown on the first epitaxial layer,
the body, the source and the gate of the MOS transistor are then created in the second epitaxial layer, by means of the known processes, in correspondence with the aforesaid buried emitter zone of the bipolar transistor, and
a P+ type region, which enables the base region of the bipolar transistor to be electrically connected on the surface, is also created at the side of said MOS transistor, by means of the known techniques of oxidation, photomasking, implantation and diffusion.
Alternatively, the process is characterized in that:
a second P+ type region, separated from the first by a region of the epitaxial layer, is created in the epitaxial layer simultaneously to said first region,
a fourth and a fifth N+ type region, designed to constitute the MOS source and drain region respectively, are created within the second region, and
the deposition of tracks of conductor material designed to electrically interconnect the emitter and drain metal coatings is carried out simultaneously to the deposition of the films of conductor material designed to form the gate terminals and the metal coating which ensure the ohmic contact with the MOS source and drain regions and with the base and emitter regions of the bipolar transistor.
BRIEF DESCRIPTION OF THE DRAWING
The above and other objects, features and advantages of our invention will become more readily apparent from the following description, reference being made to the accompanying highly diagrammatic drawing in which:
FIG. 1 is a circuit diagram which shows the equivalent electrical circuit of the 4-terminals integrated structures, which the invention intends to realize;
FIGS. 2-7 are diagrammatic sections which show a structure according to the invention, in the vertical MOS power transistor version, during the various stages of the manufacturing process;
FIG. 8 is a section which shows the structure obtained at the end of the process referred to in the previous FIGS. 2-7;
FIG. 9 is a diagram of the concentrations of the various types of doping agent along a section of the structure of FIG. 7;
FIGS. 10-11 are sections which show a structure according to the invention, in the horizontal MOS power transistor version, during the various stages of the manfacturing process; and
FIG. 12 is a section which shows a schematic representation of the structure obtained at the end of the process referred to in FIGS. 10-11.
SPECIFIC DESCRIPTION
FIG. 1 shows the equivalent electrical circuit of the 4-terminal integrated structures that the invention intends to provide.
This circuit consists of a high-voltage bipolar power transistor T connected by means of its emitter to the drain of a low-voltage MOS power transistor P.
The various stages of the manufacturing process of the integrated structure, in the vertical MOS version, are described hereunder.
A first high resistivity N- conductivity epitaxial layer 2 is grown on an N+ type substrate 1 (FIG. 2). A P+ type region 3 is then obtained, by deposition or implantation and subsequent diffusion, on said layer 2 (FIG. 3). An N+ type region 4 is then obtained by means of the same process (FIG. 4). This is followed by the growth of a second N type epitaxial layer 5 (FIG. 5) and, by the known procedures of oxidation, photomasking, implantation and diffusion, the creation of the P+ type regions 8, which enable the region 3 constituting the base of the bipolar transistor to be connected on the surface (FIG. 6). A low-voltage vertical MOS power transistor and in particular the relative P conductivity body regions 6, N+ type source regions 7 (FIG. 7), the gate 9 and the metal coatings 10, 11 and 14 for ensuring the ohmic contact with the regions 6, 7, 8 and the substrate 1 (FIG. 8) are then created in the area between the two regions 8, according to known procedures.
FIG. 8 shows the final structure, as it appears after addition of the terminals C (collector). B (base), S (source) and G (gate) and the insulating layer 12 of the gate 9 (said gate being connected to the relative terminal by means of the insulated conductor 13). Regions 1, 2, 3 and 4 of the figure constitute, respectively, the collector, the base and the emitter of a bipolar transistor, while region 5 constitutes the drain of the MOS. Said drain is consequently connected directly to the emitter of the bipolar transistor thus forming a structure having as its equivalent circuit the circuit of FIG. 1.
The emitter 4 represents a completely buried N+ type active region; by growing a second N type epitaxial layer 5 it is thus possible to connect the drain of the MOS to the emitter 4 of the bipolar transistor,
The profile of the concentration (Co) of the various types of doping agent in the different regions of the structure, along section A--A of FIG. 7, is shown in FIG. 9, where axis x refers to the distance from the upper surface of the structure.
The manufacturing process of the integrated structure, in the horizontal MOS power transistor version, includes the following stages.
A high resistivity N- type epitaxial layer 22, which is designed to constitute the collector of the bipolar transistor, is grown on a N+ type substrate 21 (FIG. 10). Two P+ type regions 23 and 24 are then created simultaneously on said layer, by the known processes of deposition or implantation and subsequent diffusion, the first of which being destined to act as a base for the bipolar transistor and the second to receive the MOS.
By means of the known processes of oxidation, photomasking, deposition or implantation and subsequent diffusion, an N+ type region 25 which is destined to act as the emitter of the bipolar transistor is created within the region 23, while two N+ type regions 26 and 27 which are destined to act as the source and the drain of the MOS are created within the region 24 (FIG. 11). This is followed by the formation of the MOS gate 28, the gate insulating layer 29, the metal coatings 30, 31, 32, 33 and 34, which are designed to ensure the ohmic contact with the underlying regions, and lastly the connections to the terminals S, G, B and C (FIG. 12).
The aforesaid metal coatings also include the formation of a track 35 for connecting the drain D to the emitter E, so as to achieve the connection of the two transistors in the configuration of FIG. 1.
In both the vertical MOS and horizontal versions, the final structure obtained is provided with 4 terminals, 3 of said terminals being located on one face of the chip and the 4th on the other face.
The described process can obviously be used to simultaneously obtain, on the same chip, several pairs of bipolar and MOS transistors having a collector terminal in common and their base contacts, sources and gates connected to three respective common terminals by means of a metal coating carried out on the front of the chip at the end of the process.

Claims (5)

We claim:
1. Process for manufacturing an integrated .Iadd.structure comprising a .Iaddend.high-voltage bipolar power transistor and .Iadd.a .Iaddend.vertical low-voltage MOS power transistor . .structure.!., in . .the.!. .Iadd.an .Iaddend.emitter switching configuration, . .of the type in which: a.!. .Iadd.having an N- type .Iaddend.first . .high resistivity N- type.!. epitaxial layer, designed to form . .the.!. .Iadd.a .Iaddend.collector of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, . .is.!. grown on . .a.!. .Iadd.an .Iaddend.N+ type substrate, a P+ conductivity region, designed to serve as . .the.!. .Iadd.a .Iaddend.base of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, and . .then.!. an N+ type region, designed to serve as . .the.!. .Iadd.a .Iaddend.buried emitter . .zone.!. of . .the same.!. .Iadd.said bipolar power .Iaddend.transistor, . .are subsequently.!. created on said first .Iadd.epitaxial .Iaddend.layer, by deposition or . .implanation.!. .Iadd.implantation .Iaddend.and . .subsequent.!. diffusion,
. .characterized by the fact that.!. .Iadd.said process comprising.Iaddend.:
a second N conductivity epitaxial layer, designed to constitute . .the.!. .Iadd.a .Iaddend.drain . .region.!. of . .the.!. .Iadd.said .Iaddend.MOS .Iadd.power .Iaddend.transistor and . .at the same time automaticaly.!. .Iadd.automatically .Iaddend.form . .the.!. .Iadd.a .Iaddend.connection between . .the.!. .Iadd.said .Iaddend.drain of . .the.!. .Iadd.said .Iaddend.MOS .Iadd.power .Iaddend.transistor and . .the.!. .Iadd.said buried .Iaddend.emitter of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, is grown on . .the.!. .Iadd.said .Iaddend.first epitaxial layer, . .the.!. .Iadd.a .Iaddend.body, . .the.!. .Iadd.a .Iaddend.source and . .the.!. .Iadd.a .Iaddend.gate of . .the.!. .Iadd.said .Iaddend.MOS .Iadd.power .Iaddend.transistor are . .then.!. created in . .the.!. .Iadd.said .Iaddend.second epitaxial layer, in correspondence with . .the aforesaid.!. .Iadd.said .Iaddend.buried emitter . .zone.!. of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor,
a P+ type region, which enables . .the.!. .Iadd.electrical connection to be made to said .Iaddend.base . .region.!. of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor . .to be electrically connected on the surface.!., is . .also.!. created at the side of . .the.!. said MOS .Iadd.power .Iaddend.transistor.
2. Process for manufacturing an integrated .Iadd.structure comprising a .Iaddend.high-voltage bipolar power transistor and .Iadd.a .Iaddend.horizontal low-voltage MOS power transistor . .structure.!., in . .the.!. .Iadd.an .Iaddend.emitter switching configuration, . .of the type in which: a high resistivity.!. .Iadd.having an .Iaddend.N- type epitaxial layer, designed to form . .the.!. .Iadd.a .Iaddend.collector of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, . .is.!. grown on an N+ type substrate, a first P+ type region . .is then created.!. in said epitaxial layer, a third N+ type region, designed to constitute . .the.!. .Iadd.an .Iaddend.emitter . .region.!. of . .the same.!. .Iadd.said bipolar power .Iaddend.transistor, . .is then created.!. .Iadd.and .Iaddend.within . .the aforesaid.!. .Iadd.said .Iaddend.first .Iadd.P+ type .Iaddend.region, .Iadd.said first P+ type region being .Iaddend.designed to constitute . .the.!. .Iadd.a .Iaddend.base of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor,
.Iadd.said process being .Iaddend.characterized by the fact that:
a second P+ type region, separated from . .the.!. .Iadd.said .Iaddend.first .Iadd.P+ type region .Iaddend.by a region of . .the.!. .Iadd.said .Iaddend.epitaxial layer, is created in . .the.!. .Iadd.said .Iaddend.epitaxial layer simultaneously . .to.!. .Iadd.with .Iaddend.said first region,
a fourth .Iadd.N+ type region .Iaddend.and a fifth N+ type region, designed to constitute . .the MOS.!. .Iadd.a .Iaddend.source and .Iadd.a .Iaddend.drain . .region.!. respectively .Iadd.of said MOS power transistor.Iaddend., are created within . .the.!. .Iadd.said .Iaddend.second .Iadd.P+ type .Iaddend.region, the deposition of tracks of conductor material designed to electrically interconnect . .the.!. .Iadd.said .Iaddend.emitter and .Iadd.said .Iaddend.drain . .metal coatings.!. .Iadd.to each other .Iaddend.is carried out simultaneously . .to.!. .Iadd.with .Iaddend.the deposition of . .the.!. films of conductor material designed to form . .the.!. gate terminals and . .the meatal.!. .Iadd.metal .Iaddend.coatings which ensure the ohmic contact with . .the MOS.!. .Iadd.said .Iaddend.source and .Iadd.said .Iaddend.drain . .regions.!. .Iadd.of said MOS power transistor .Iaddend.and with . .the.!. .Iadd.said .Iaddend.base and emitter . .regions.!. of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor.Iadd.;
wherein said MOS power transistor controllably cuts off current to said emitter of said bipolar power transistor, to provide high-voltage switching in a switched-emitter configuration having a primary current path between said fourth N+ type region and said N+ type substrate.Iaddend.. .Iadd.3. The method of claim 1, wherein said body of said MOS power transistor is formed before said source of said MOS power transistor. .Iaddend..Iadd.4. The method of claim 1, wherein said body and said source of said MOS power transistor are both formed by implantation. .Iaddend..Iadd.5. A process for manufacturing an integrated high-voltage bipolar power transistor and a vertical low-voltage MOS power transistor structure, comprising the steps of:
a) growing an N- type first epitaxial layer on an N+ type substrate, said first epitaxial layer providing a collector of said bipolar power transistor;
b) creating on said first epitaxial layer a P+ conductivity region providing a base of said bipolar power transistor, and an N+ the region providing a buried emitter zone, by deposition or implantation and diffusion;
c) growing an N conductivity second epitaxial layer on said first epitaxial layer, and forming a body region therein;
d) creating, at an upper surface of said second epitaxial layer, a source region and a gate of said MOS power transistor structure, in vertical correspondence with said buried emitter zone of said bipolar power transistor,
e) creating a P+ type region at the side of said MOS power transistor structure, which enables said base of said bipolar power transistor to be
electrically connected on said upper surface. .Iaddend..Iadd.6. The method of claim 5, wherein said second epitaxial layer is grown directly on said first epitaxial layer. .Iaddend..Iadd.7. The method of claim 5, wherein said base is formed before said buried emitter zone. .Iaddend..Iadd.8. The method of claim 5, wherein said body region is formed before said source. .Iaddend..Iadd.9. The method of claim 5, wherein said body region and said source region are both formed by implantation. .Iaddend..Iadd.10. The method of claim 5, wherein said gate is insulated on the underside thereof. .Iaddend..Iadd.11. A process for manufacturing a structure having an integrated high-voltage bipolar power transistor and horizontal low-voltage MOS power transistor in an emitter switching configuration said process comprising the steps of:
growing an N- type epitaxial layer, designed to form a collector of said bipolar power transistor, on an N+ type substrate,
creating in said epitaxial layer,
a first P+ type region, to constitute a base of said bipolar power transistor, and
a second P+ type region separated from said first P+ type region by a region of said epitaxial layer;
creating a third N+ type region, to constitute an emitter region of said bipolar power transistor, within said first P+ type region;
creating a fourth and a fifth N+ type region, to constitute a source region and a drain region respectively, of said MOS power transistor within said second P+ type region,
forming a thin film of conductor material which is positioned and operatively connected to provide a field-effect-transistor-gate which controls conduction between said source region and said drain region of said MOS power transistor, and
forming a strip of thin film conductor material which is positioned and operatively connected to electrically interconnect said emitter region of said bipolar power transistor and said drain region of said MOS power transistor;
wherein said MOS power transistor controllably cuts off current to said emitter of said bipolar power transistor, to provide high-voltage switching in a switched-emitter configuration having a primary current path between said source region of said MOS power transistor and said
collector of said bipolar power transistor. .Iaddend..Iadd.12. The method of claim 11, wherein said field-effect-transistor-gate is insulated on the underside thereof. .Iaddend..Iadd.13. A process for manufacturing a microelectronic structure which includes a vertical high-voltage bipolar power transistor, and which also includes a vertical low-voltage MOS power transistor structure extending to a front surface thereof, comprising the steps of:
a) on an N+ type substrate, growing an N- type first epitaxial layer, to provide the collector of the bipolar power transistor;
b) creating, near the front surface of said first epitaxial layer, a P+ region to provide a base of said bipolar power transistor, and an N+ type region, which is shallower than said P+ region, to provide an emitter of said bipolar power transistor;
c) growing an N+ type additional epitaxial layer above said first epitaxial layer;
d) forming, in said additional epitaxial layer, a P- type body region, and an N- type source region which is shallower than said body region, and a P+ sinker region which provides ohmic contact to said base; and
e) creating, atop said additional epitaxial layer, an insulated gate electrode which is capacitively coupled to at least some potions of said body which are laterally adjacent to said source region. .Iaddend..Iadd.14. The method of claim 13, wherein said additional epitaxial layer is grown directly on said first epitaxial layer. .Iaddend..Iadd.15. The method of claim 13, wherein said base is formed before said emitter. .Iaddend..Iadd.16. The method of claim 13, wherein said body region is formed before said source region. .Iaddend..Iadd.17. The method of claim 13, wherein said body and source regions are both
formed by implantation. .Iaddend..Iadd.18. The method of claim 13, wherein said gate electrode is insulated on the underside thereof. .Iaddend..Iadd.19. A process for manufacturing a solid-state structure which includes an integrated high-voltage bipolar power transistor, and which also includes a vertical low-voltage MOS power transistor, comprising the steps of:
a) providing a monolithic semiconductor structure which includes a first region which is doped with a dopant of a first conductivity type and a second region of said first conductivity type and is more lightly doped than said first region, and providing a metallic backside contact to said first region;
b) creating, in an upper surface of said monolithic semiconductor structure, a third region which is doped with a second conductivity type that is opposite to said first conductivity type, and a fourth region which is doped with said first conductivity type;
c) epitaxially growing an additional layer of semiconductor material of said first conductivity type above said monolithic semiconductor structure;
d) forming, in proximity to said front surface,
a body diffusion of said second conductivity type, and
a source diffusion of said first conductivity type that is completely separated by said body diffusion from other portions of said additional layer of semiconductor material, and
a diffusion region of said second conductivity type which extends upward from said third region;
e) creating, atop said additional layer of semiconductor material, an insulated gate electrode which is capacitively coupled to portions of said body diffusion which are laterally adjacent to said source diffusion. .Iaddend..Iadd.20. The method of claim 19, wherein said body diffusion is formed before said source diffusion. .Iaddend..Iadd.21. The method of claim 19, wherein said body and source diffusions are both formed by implantation. .Iaddend..Iadd.22. The method of claim 19, wherein said gate electrode is insulated on the underside thereof. .Iaddend..Iadd.23. The method of claim 19, wherein said additional layer is grown directly on said monolithic semiconductor structure. .Iaddend..Iadd.24. The method of claim 19, wherein said first region of said monolithic semiconductor structure is a substrate, and said second region is an epitaxial layer grown on said substrate. .Iaddend..Iadd.25. The method of claim 19, wherein said first conductivity type is N- type. .Iaddend.
US08/253,151 1987-12-22 1994-06-02 Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process Expired - Lifetime USRE36311E (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/253,151 USRE36311E (en) 1987-12-22 1994-06-02 Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
IT06631/87A IT1217323B (en) 1987-12-22 1987-12-22 INTEGRATED STRUCTURE OF HIGH VOLTAGE BIPOLAR POWER TRANSISTOR AND LOW VOLTAGE POWER MOS TRANSISTOR IN THE "EMITTER SWITCHING" CONFIGURATION AND RELATED MANUFACTURING PROCESS
IT6631/87 1987-12-28
US07/288,405 US5065213A (en) 1987-12-22 1988-12-21 Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process
US07/749,251 US5118635A (en) 1987-12-22 1991-08-23 Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process
US08/253,151 USRE36311E (en) 1987-12-22 1994-06-02 Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US07/288,405 Division US5065213A (en) 1987-12-22 1988-12-21 Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process
US07/749,251 Reissue US5118635A (en) 1987-12-22 1991-08-23 Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process

Publications (1)

Publication Number Publication Date
USRE36311E true USRE36311E (en) 1999-09-21

Family

ID=11121617

Family Applications (3)

Application Number Title Priority Date Filing Date
US07/288,405 Ceased US5065213A (en) 1987-12-22 1988-12-21 Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process
US07/749,251 Ceased US5118635A (en) 1987-12-22 1991-08-23 Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process
US08/253,151 Expired - Lifetime USRE36311E (en) 1987-12-22 1994-06-02 Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US07/288,405 Ceased US5065213A (en) 1987-12-22 1988-12-21 Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process
US07/749,251 Ceased US5118635A (en) 1987-12-22 1991-08-23 Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process

Country Status (6)

Country Link
US (3) US5065213A (en)
EP (1) EP0322041B1 (en)
JP (1) JP2798401B2 (en)
KR (1) KR0130774B1 (en)
DE (1) DE3855603T2 (en)
IT (1) IT1217323B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6395593B1 (en) * 1999-05-06 2002-05-28 Texas Instruments Incorporated Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration
US6759730B2 (en) * 2001-09-18 2004-07-06 Agere Systems Inc. Bipolar junction transistor compatible with vertical replacement gate transistor

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1217323B (en) * 1987-12-22 1990-03-22 Sgs Microelettronica Spa INTEGRATED STRUCTURE OF HIGH VOLTAGE BIPOLAR POWER TRANSISTOR AND LOW VOLTAGE POWER MOS TRANSISTOR IN THE "EMITTER SWITCHING" CONFIGURATION AND RELATED MANUFACTURING PROCESS
USRE35642E (en) * 1987-12-22 1997-10-28 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
JPH0810506Y2 (en) * 1990-03-23 1996-03-29 株式会社小松製作所 Turntable fixing device for machine tools
JP2987884B2 (en) * 1990-06-04 1999-12-06 日産自動車株式会社 Semiconductor device
IT1246759B (en) * 1990-12-31 1994-11-26 Sgs Thomson Microelectronics INTEGRATED STRUCTURE OF BIPOLAR POWER TRANSISTOR AND LOW VOLTAGE BIPOLAR TRANSISTOR IN '' EMITTER SWITCHING '' OR '' SEMI-BRIDGE '' CONFIGURATIONS AND RELATED MANUFACTURING PROCESSES.
EP0544048B1 (en) * 1991-11-25 1997-06-18 STMicroelectronics S.r.l. Integrated bridge device optimising conduction power losses
JPH06163907A (en) * 1992-11-20 1994-06-10 Hitachi Ltd Voltage drive semiconductor device
US5329147A (en) * 1993-01-04 1994-07-12 Xerox Corporation High voltage integrated flyback circuit in 2 μm CMOS
DE69320033T2 (en) * 1993-06-10 1998-12-03 Cons Ric Microelettronica Monolithically integrated structure of a vertical bipolar and a vertical MOSFET transistor
DE69322963T2 (en) * 1993-09-17 1999-06-24 Cons Ric Microelettronica An integrated device with a bipolar transistor and a MOSFET transistor in an emitter circuit arrangement
US5591655A (en) * 1995-02-28 1997-01-07 Sgs-Thomson Microelectronics, Inc. Process for manufacturing a vertical switched-emitter structure with improved lateral isolation
US5633180A (en) * 1995-06-01 1997-05-27 Harris Corporation Method of forming P-type islands over P-type buried layer
US5910664A (en) * 1996-11-05 1999-06-08 International Rectifier Corporation Emitter-switched transistor structures
US5925910A (en) * 1997-03-28 1999-07-20 Stmicroelectronics, Inc. DMOS transistors with schottky diode body structure
US6365447B1 (en) 1998-01-12 2002-04-02 National Semiconductor Corporation High-voltage complementary bipolar and BiCMOS technology using double expitaxial growth
DE69834315T2 (en) 1998-02-10 2007-01-18 Stmicroelectronics S.R.L., Agrate Brianza Integrated circuit with a VDMOS transistor, which is protected against overvoltages between source and gate
EP0981163A1 (en) * 1998-08-14 2000-02-23 STMicroelectronics S.r.l. Semiconductor power device with insulated circuit and process for its manufacture
US6441445B1 (en) * 1998-10-06 2002-08-27 Stmicroelectronics S.R.L. Integrated device with bipolar transistor and electronic switch in “emitter switching” configuration
US9184097B2 (en) * 2009-03-12 2015-11-10 System General Corporation Semiconductor devices and formation methods thereof
CN104576365B (en) * 2013-10-25 2017-11-21 无锡华润上华科技有限公司 Cluster IGBT preparation method
JP6299254B2 (en) * 2014-02-10 2018-03-28 富士電機株式会社 Semiconductor device, switching power supply control IC, and switching power supply device
US9871510B1 (en) 2016-08-24 2018-01-16 Power Integrations, Inc. Clamp for a hybrid switch

Citations (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544863A (en) * 1968-10-29 1970-12-01 Motorola Inc Monolithic integrated circuit substructure with epitaxial decoupling capacitance
US3580745A (en) * 1965-06-05 1971-05-25 Philips Corp Semiconductor device
UST892019I4 (en) * 1969-01-27 1971-11-30 Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance
US3880676A (en) * 1973-10-29 1975-04-29 Rca Corp Method of making a semiconductor device
US4032956A (en) * 1972-12-29 1977-06-28 Sony Corporation Transistor circuit
US4120707A (en) * 1977-03-30 1978-10-17 Harris Corporation Process of fabricating junction isolated IGFET and bipolar transistor integrated circuit by diffusion
US4151006A (en) * 1976-04-27 1979-04-24 U.S. Philips Corporation Method of manufacturing a semiconductor device
US4210925A (en) * 1978-02-07 1980-07-01 Harris Corporation I2 L Integrated circuit and process of fabrication
US4239558A (en) * 1978-06-01 1980-12-16 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor devices utilizing epitaxial deposition and triple diffusion
US4277794A (en) * 1976-12-03 1981-07-07 Thomson-Csf Structure for logic circuits
US4311532A (en) * 1979-07-27 1982-01-19 Harris Corporation Method of making junction isolated bipolar device in unisolated IGFET IC
US4315781A (en) * 1980-04-23 1982-02-16 Hughes Aircraft Company Method of controlling MOSFET threshold voltage with self-aligned channel stop
US4344081A (en) * 1980-04-14 1982-08-10 Supertex, Inc. Combined DMOS and a vertical bipolar transistor device and fabrication method therefor
US4425516A (en) * 1981-05-01 1984-01-10 Zytrex Corporation Buffer circuit and integrated semiconductor circuit structure formed of bipolar and CMOS transistor elements
US4458408A (en) * 1981-07-31 1984-07-10 Motorola, Inc. Method for making a light-activated line-operable zero-crossing switch
US4483738A (en) * 1983-02-12 1984-11-20 Itt Industries, Inc. Method for manufacturing bipolar planar transistors
US4523215A (en) * 1980-01-21 1985-06-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4667393A (en) * 1984-08-21 1987-05-26 Sgs Microelettronica S.P.A. Method for the manufacture of semiconductor devices with planar junctions having a variable charge concentration and a very high breakdown voltage
US4721684A (en) * 1984-12-20 1988-01-26 Sgs Microelettronica Spa Method for forming a buried layer and a collector region in a monolithic semiconductor device
US4780430A (en) * 1986-10-01 1988-10-25 Sgs Microelettronica S.P.A Process for the formation of a monolithic high voltage semiconductor device
US4814288A (en) * 1986-07-14 1989-03-21 Hitachi, Ltd. Method of fabricating semiconductor devices which include vertical elements and control elements
EP0322040A2 (en) * 1987-12-22 1989-06-28 STMicroelectronics S.r.l. Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip
EP0322041A2 (en) * 1987-12-22 1989-06-28 STMicroelectronics S.r.l. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
US4879584A (en) * 1987-02-13 1989-11-07 Kabushiki Kaisha Toshiba Semiconductor device with isolation between MOSFET and control circuit
US4881119A (en) * 1986-05-16 1989-11-14 U.S. Philips Corp. Semiconductor devices
EP0347550A2 (en) * 1988-06-21 1989-12-27 Texas Instruments Incorporated Process for fabricating isolated vertical and super beta bipolar transistors
US4892836A (en) * 1986-03-27 1990-01-09 Sgs Microelettronica S.P.A. Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices
US4898836A (en) * 1988-04-28 1990-02-06 Sgs-Thomson Microelectronics S.R.L. Process for forming an integrated circuit on an N type substrate comprising PNP and NPN transistors placed vertically and insulated one from another
US4935799A (en) * 1986-07-14 1990-06-19 Mutsuhiro Mori Composite semiconductor device
US4947231A (en) * 1987-10-30 1990-08-07 Sgs-Thomson Microelectronics S.R.L. Integrated structure with active and passive components enclosed in insulating pockets and operating at higher than the breakdown voltage between each component and the pocket containing it
US4969030A (en) * 1987-03-05 1990-11-06 Sgs-Thomson Microelectronics S.P.A. Integrated structure for a signal transfer network, in particular for a pilot circuit for MOS power transistors
US5119161A (en) * 1989-06-16 1992-06-02 Sgs-Thomson Microelectronics S.R.L. Semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS568874A (en) * 1979-07-04 1981-01-29 Pioneer Electronic Corp Bipolar transistor device
US4441117A (en) * 1981-07-27 1984-04-03 Intersil, Inc. Monolithically merged field effect transistor and bipolar junction transistor
JPS5896762A (en) * 1981-12-03 1983-06-08 Mitsubishi Electric Corp Semiconductor element
GB2164790A (en) * 1984-09-19 1986-03-26 Philips Electronic Associated Merged bipolar and field effect transistors
IT1213231B (en) * 1984-10-25 1989-12-14 Ates Componenti Elettron INTEGRATED ELECTRONIC DEVICE WITH STABILIZED CONSTANT VOLTAGE, PROCEDURE FOR ITS MANUFACTURE.

Patent Citations (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3580745A (en) * 1965-06-05 1971-05-25 Philips Corp Semiconductor device
US3544863A (en) * 1968-10-29 1970-12-01 Motorola Inc Monolithic integrated circuit substructure with epitaxial decoupling capacitance
UST892019I4 (en) * 1969-01-27 1971-11-30 Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance
US4032956A (en) * 1972-12-29 1977-06-28 Sony Corporation Transistor circuit
US3880676A (en) * 1973-10-29 1975-04-29 Rca Corp Method of making a semiconductor device
US4151006A (en) * 1976-04-27 1979-04-24 U.S. Philips Corporation Method of manufacturing a semiconductor device
US4277794A (en) * 1976-12-03 1981-07-07 Thomson-Csf Structure for logic circuits
US4120707A (en) * 1977-03-30 1978-10-17 Harris Corporation Process of fabricating junction isolated IGFET and bipolar transistor integrated circuit by diffusion
US4210925A (en) * 1978-02-07 1980-07-01 Harris Corporation I2 L Integrated circuit and process of fabrication
US4239558A (en) * 1978-06-01 1980-12-16 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor devices utilizing epitaxial deposition and triple diffusion
US4311532A (en) * 1979-07-27 1982-01-19 Harris Corporation Method of making junction isolated bipolar device in unisolated IGFET IC
US4523215A (en) * 1980-01-21 1985-06-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4344081A (en) * 1980-04-14 1982-08-10 Supertex, Inc. Combined DMOS and a vertical bipolar transistor device and fabrication method therefor
US4315781A (en) * 1980-04-23 1982-02-16 Hughes Aircraft Company Method of controlling MOSFET threshold voltage with self-aligned channel stop
US4425516A (en) * 1981-05-01 1984-01-10 Zytrex Corporation Buffer circuit and integrated semiconductor circuit structure formed of bipolar and CMOS transistor elements
US4458408A (en) * 1981-07-31 1984-07-10 Motorola, Inc. Method for making a light-activated line-operable zero-crossing switch
US4483738A (en) * 1983-02-12 1984-11-20 Itt Industries, Inc. Method for manufacturing bipolar planar transistors
US4667393A (en) * 1984-08-21 1987-05-26 Sgs Microelettronica S.P.A. Method for the manufacture of semiconductor devices with planar junctions having a variable charge concentration and a very high breakdown voltage
US4721684A (en) * 1984-12-20 1988-01-26 Sgs Microelettronica Spa Method for forming a buried layer and a collector region in a monolithic semiconductor device
US4892836A (en) * 1986-03-27 1990-01-09 Sgs Microelettronica S.P.A. Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices
US4881119A (en) * 1986-05-16 1989-11-14 U.S. Philips Corp. Semiconductor devices
US4814288A (en) * 1986-07-14 1989-03-21 Hitachi, Ltd. Method of fabricating semiconductor devices which include vertical elements and control elements
US4935799A (en) * 1986-07-14 1990-06-19 Mutsuhiro Mori Composite semiconductor device
US4780430A (en) * 1986-10-01 1988-10-25 Sgs Microelettronica S.P.A Process for the formation of a monolithic high voltage semiconductor device
US4879584A (en) * 1987-02-13 1989-11-07 Kabushiki Kaisha Toshiba Semiconductor device with isolation between MOSFET and control circuit
US4969030A (en) * 1987-03-05 1990-11-06 Sgs-Thomson Microelectronics S.P.A. Integrated structure for a signal transfer network, in particular for a pilot circuit for MOS power transistors
US4947231A (en) * 1987-10-30 1990-08-07 Sgs-Thomson Microelectronics S.R.L. Integrated structure with active and passive components enclosed in insulating pockets and operating at higher than the breakdown voltage between each component and the pocket containing it
EP0322041A2 (en) * 1987-12-22 1989-06-28 STMicroelectronics S.r.l. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
EP0322040A2 (en) * 1987-12-22 1989-06-28 STMicroelectronics S.r.l. Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip
US5065213A (en) * 1987-12-22 1991-11-12 Sgs-Thomson Microelectronics S.R.L. Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process
US5118635A (en) * 1987-12-22 1992-06-02 Sgs-Thomson Microelectronics S.R Integrated high-voltage bipolar power transistor and low voltage mos power transistor structure in the emitter switching configuration and relative manufacturing process
US4898836A (en) * 1988-04-28 1990-02-06 Sgs-Thomson Microelectronics S.R.L. Process for forming an integrated circuit on an N type substrate comprising PNP and NPN transistors placed vertically and insulated one from another
EP0347550A2 (en) * 1988-06-21 1989-12-27 Texas Instruments Incorporated Process for fabricating isolated vertical and super beta bipolar transistors
US5119161A (en) * 1989-06-16 1992-06-02 Sgs-Thomson Microelectronics S.R.L. Semiconductor device comprising a control circuit and a power stage with a vertical current flow, integrated in monolithic form on a single chip

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Blanchard, "A Power Transistor With an Integrated Thermal Feedback Mechanism," Master of Science Dissertation (1970).
Blanchard, A Power Transistor With an Integrated Thermal Feedback Mechanism, Master of Science Dissertation (1970). *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6395593B1 (en) * 1999-05-06 2002-05-28 Texas Instruments Incorporated Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration
US6759730B2 (en) * 2001-09-18 2004-07-06 Agere Systems Inc. Bipolar junction transistor compatible with vertical replacement gate transistor

Also Published As

Publication number Publication date
KR0130774B1 (en) 1998-04-06
US5118635A (en) 1992-06-02
EP0322041B1 (en) 1996-10-09
EP0322041A3 (en) 1993-04-21
EP0322041A2 (en) 1989-06-28
DE3855603D1 (en) 1996-11-14
JP2798401B2 (en) 1998-09-17
DE3855603T2 (en) 1997-03-13
JPH022665A (en) 1990-01-08
US5065213A (en) 1991-11-12
KR890011106A (en) 1989-08-12
IT1217323B (en) 1990-03-22
IT8706631A0 (en) 1987-12-22

Similar Documents

Publication Publication Date Title
USRE36311E (en) Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
US5914522A (en) Power semiconductor structure with lateral transistor driven by vertical transistor
US5591655A (en) Process for manufacturing a vertical switched-emitter structure with improved lateral isolation
US3293087A (en) Method of making isolated epitaxial field-effect device
US6093948A (en) MOS transistors having vertical current flow
US6559505B1 (en) Power integrated circuit with vertical current flow and related manufacturing process
JPH07193154A (en) Semiconductor integrated device
US5430323A (en) Injection control-type Schottky barrier rectifier
US4322738A (en) N-Channel JFET device compatible with existing bipolar integrated circuit processing techniques
US4512075A (en) Method of making an integrated injection logic cell having self-aligned collector and base reduced resistance utilizing selective diffusion from polycrystalline regions
KR910006672B1 (en) Semiconductor integrated circuit device and its manufacturing method
US4780425A (en) Method of making a bipolar transistor with double diffused isolation regions
US5500551A (en) Integrated emitter switching configuration using bipolar transistors
EP0082331B1 (en) Subsurface avalanche breakdown zener diode
US4639757A (en) Power transistor structure having an emitter ballast resistance
US3595714A (en) Method of manufacturing a semiconductor device comprising a field-effect transistor
US6525392B1 (en) Semiconductor power device with insulated circuit
US4260430A (en) Method of manufacturing a semiconductor device
USRE35642E (en) Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
JPH0362028B2 (en)
US4407005A (en) N-Channel JFET device having a buried channel region, and method for making same
US5866461A (en) Method for forming an integrated emitter switching configuration using bipolar transistors
US6030888A (en) Method of fabricating high-voltage junction-isolated semiconductor devices
US4122482A (en) Vertical complementary bipolar transistor device with epitaxial base zones
KR0164526B1 (en) A buried-type lateral bipolar transistor and method of making the same

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 12