USRE36613E - Multi-chip stacked devices - Google Patents

Multi-chip stacked devices Download PDF

Info

Publication number
USRE36613E
USRE36613E US08/610,127 US61012796A USRE36613E US RE36613 E USRE36613 E US RE36613E US 61012796 A US61012796 A US 61012796A US RE36613 E USRE36613 E US RE36613E
Authority
US
United States
Prior art keywords
die
lead
wires
iaddend
iadd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/610,127
Inventor
Michael B. Ball
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Round Rock Research LLC
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US08/610,127 priority Critical patent/USRE36613E/en
Application granted granted Critical
Publication of USRE36613E publication Critical patent/USRE36613E/en
Priority to US10/346,860 priority patent/USRE40061E1/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: MICRON SEMICONDUCTOR, INC.
Assigned to ROUND ROCK RESEARCH, LLC reassignment ROUND ROCK RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06575Auxiliary carrier between devices, the carrier having no electrical connection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01031Gallium [Ga]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Definitions

  • This invention relates to a multiple die module that has a thickness the same or less than a standard package but has two or more stacked die, thereby increasing device density.
  • Semiconductor devices are typically constructed en masse on a silicon or gallium arsenide wafer through a process which comprises a number of deposition, masking, diffusion, etching, and implanting steps. When the devices are sawed into individual rectangular units, each takes the from of an integrated circuit (IC) die. In order to interface a die with other circuitry, it is (using contemporary conventional packaging technology) mounted on a lead frame paddle of a lead-frame strip which consists of a series of interconnected lead frames, typically ten in a row. The die-mounting paddle of a standard lead frame is larger than the die itself, and it is surrounded by multiple lead fingers of individual leads.
  • IC integrated circuit
  • the bonding pads of the die are then connected one by one in a wire-bonding operation to the lead frame's lead finger pads with extremely fine gold or aluminum wire.
  • a protective layer to the face of the die, it, and a portion of the lead frame to which it is attached, is encapsulated in a plastic material, as are all other die/lead-frame assemblies on the lead-frame strip.
  • a trim-and-form operation then separates the resultant interconnected packages and bends the leads of each package into the proper configuration.
  • IC package density is primarily limited by the area available for die mounting and the height of the package. Typical computer-chip heights in the art are about 0.110 inches. A method of increasing density is to stack die or chips vertically.
  • An upper, smaller die is back-bonded to the upper surface of the lead fingers of the lead frame via a first adhesively coated, insulated film layer.
  • the lower, slightly larger die is face-bonded to the lower surface of the lead extensions with the lower lead-frame die-bonding region via a second, adhesively coated, film layer.
  • the wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum wires.
  • the lower die needs to be slightly larger in order that the die pads are accessible from above so that gold wire connections can be made to the lead extensions (fingers).
  • a Japanese Patent No. 56-62351(A) issued to Sano in 1981 discloses three methods of mounting two chips on a lead frame and attaching the pair of semiconductor chips (pellets) to a common lead frame consisting of:
  • method 3 one chip attached above and one chip attached below a common paddle.
  • a controlled, first, thin-adhesive layer affixing a first die above the paddle
  • a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads and a second wire bond to a plurality of adjacent lead-frame frame lead fingers;
  • a second thin-adhesive layer affixing a second die above the first die
  • FIG. 1 is a partial plan view of the stacked die, lead fingers, and bonded wires of the present invention.
  • FIG. 2 is a side elevation taken through 2--2 of FIG. 1 showing a four die stacking.
  • the stacked die device 10 is shown prior to encapsulation disclosing the top die 12 mounted the paddle 14 and other dies 16, 18, and 20 (FIG. 2) which are adhesively connected to each other by a controlled-thickness thermoplastic-adhesive layer at 22. Thermoplastic indicating the adhesive sets at an elevated temperature. The group of four dies are attached to the paddle 14 by a controlled thin-adhesive layer 24.
  • Each of the die bonding pads 26 in double rows are electrically connected to multiple lead fingers 28A, 28B, 28C . . . 28N by thin (0.001 inch) gold or aluminum wires 30A, 30B, 30C . . . 30N; gold being the preferred metal.
  • the critical bonding method used at the die end pad 26 is ultrasonic ball bond as named by the shape of the bond as at 32. This first-installed bond and formed gold wire are low-loop wire bonds as seen at critical dimension 34, as will be described later.
  • the other end of gold wires 30 are attached to the lead fingers by a wedge bond 36, which is also an ultrasonic indicating the use of ultrasonic energy to heat the wire 30 as it is compressed against the lead finger 28.
  • the wedge bond is not used on the die because the bonding machine contacts the bonding surface and could damage this critical surface.
  • the lead fingers may be formed upward as at 38 to permit the use of shorter wires 30.
  • Paddle 14 which supports the stack is attached to the lead frame typically at four corners as at 40 and also typically, in this application, would have a downset from the lead frame and lead fingers 28 as at dimension 42.
  • the stack is finally encapsulated by a plastic or ceramic at 44.
  • FIG. 2 A dimensional analysis is provided by referring to FIG. 2.
  • the encapsulation thickness 48 is between 0.010 and 0.012 inches.
  • the paddle 74 thickness 50 can be between 0.005 and 0.010 inches and is a matter of choice.
  • the controlled adhesive-layer thickness 52 can be from 0.001 to 0.005 inches.
  • the individual dies 20, 18, 16, and 12 each have a thickness 54 of 0.012 inches nd the critical controlled, adhesive-layer thicknesses 56 between each die are between 0.008 and 0.010 inches. These thin layers have to be slightly greater than the low-loop wire dimension 34, which is about 0.006 inches.
  • the top encapsulation 58 is between 0.010 and 0.012 inches so as to cover the top loop.
  • the height at 60 would be between 0.058 and 0.073 inches and for a three-die stack it would be from 0.078 to 0.100 inches.
  • the die pads 26 of each die can be each connected to an individual lead finger 28 or the dies can be wired in parallel.
  • the final packages can be in the form of a small outline J-leaded (SOJ) package, a dual in-line package (DIP), a single in-line package (SIP), a plastic leaded chip carrier (PLCC), and a zig-zag in-line package (ZIP).
  • SOJ small outline J-leaded
  • DIP dual in-line package
  • SIP single in-line package
  • PLCC plastic leaded chip carrier
  • ZIP zig-zag in-line package

Abstract

A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking is made possible by a low-loop-profile wire-bonding operation and thin-adhesive layer between the stacked dies.

Description

FIELD OF THE INVENTION
This invention relates to a multiple die module that has a thickness the same or less than a standard package but has two or more stacked die, thereby increasing device density.
BACKGROUND OF THE INVENTION
Semiconductor devices are typically constructed en masse on a silicon or gallium arsenide wafer through a process which comprises a number of deposition, masking, diffusion, etching, and implanting steps. When the devices are sawed into individual rectangular units, each takes the from of an integrated circuit (IC) die. In order to interface a die with other circuitry, it is (using contemporary conventional packaging technology) mounted on a lead frame paddle of a lead-frame strip which consists of a series of interconnected lead frames, typically ten in a row. The die-mounting paddle of a standard lead frame is larger than the die itself, and it is surrounded by multiple lead fingers of individual leads. The bonding pads of the die are then connected one by one in a wire-bonding operation to the lead frame's lead finger pads with extremely fine gold or aluminum wire. Following the application of a protective layer to the face of the die, it, and a portion of the lead frame to which it is attached, is encapsulated in a plastic material, as are all other die/lead-frame assemblies on the lead-frame strip. A trim-and-form operation then separates the resultant interconnected packages and bends the leads of each package into the proper configuration.
In the interest of higher performance equipment and lower cost, increased miniaturization of components and greater packaging density have long been the goals of the computer industry. IC package density is primarily limited by the area available for die mounting and the height of the package. Typical computer-chip heights in the art are about 0.110 inches. A method of increasing density is to stack die or chips vertically.
U.S. Pat. No. 5,01,323, issued Apr. 30, 1991, having a common assignee with the present application, discloses a pair of rectangular integrated-circuit dice mounted on opposite sides of the lead frame. An upper, smaller die is back-bonded to the upper surface of the lead fingers of the lead frame via a first adhesively coated, insulated film layer. The lower, slightly larger die is face-bonded to the lower surface of the lead extensions with the lower lead-frame die-bonding region via a second, adhesively coated, film layer. The wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum wires. The lower die needs to be slightly larger in order that the die pads are accessible from above so that gold wire connections can be made to the lead extensions (fingers).
U.S. Pat. No. 4,996,587 (referred to hereafter as '587) shows a semiconductor chip package which uses a chip carrier to support the chips within a cavity. The chip carrier a shown in the fingers has as a slot that permits connection by wires to bonding pads which, in turn, connect to the card connector by conductors. An encapsulation material is placed only on the top surface of the chip in order to provide heat dissipation from the bottoms when carriers are stacked.
A Japanese Patent No. 56-62351(A) issued to Sano in 1981 discloses three methods of mounting two chips on a lead frame and attaching the pair of semiconductor chips (pellets) to a common lead frame consisting of:
method 1 two chips ted on two paddles;
method 2 one chip mounted over a paddle and one below not attached to the paddle; and
method 3 one chip attached above and one chip attached below a common paddle.
The chips are apparently wired in parallel as stated in the "PURPOSE" of Sano.
The chip of patent '587 are also apparently wired in parallel by contacts on the "S" chips which contact the connection means.
It is the purpose of this invention to provide multiple stacked dies assembled in a special vertical configuration such that as many as four encapsulated dies will have a height no greater than existing 0.110-inch high dies and also have a separate lead and lead finger for each die pad connection.
SUMMARY OF THE INVENTION
The invention generally stated is a multiple-die low-profile semiconductor device comprising:
a lead-frame paddle supported by a lead frame;
a controlled, first, thin-adhesive layer affixing a first die above the paddle;
a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads and a second wire bond to a plurality of adjacent lead-frame frame lead fingers;
a second thin-adhesive layer affixing a second die above the first die;
a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
additional dies affixed above the second die, by additional subsequent layers of adhesive and having additional thin wires bonded to addition bonding pads and lead fingers; and
an encapsulated layer surrounding all dies, adhesive layers and thin wires.
Other object, advantages, and capabilities of the present invention will become more apparent as the description proceeds.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention may be better understood and further advantages and uses thereof may become more readily apparent when considered in view of the following detailed description of exemplary embodiments, taken with the accompanied drawings, in which
FIG. 1 is a partial plan view of the stacked die, lead fingers, and bonded wires of the present invention; and
FIG. 2 is a side elevation taken through 2--2 of FIG. 1 showing a four die stacking.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, the stacked die device 10 is shown prior to encapsulation disclosing the top die 12 mounted the paddle 14 and other dies 16, 18, and 20 (FIG. 2) which are adhesively connected to each other by a controlled-thickness thermoplastic-adhesive layer at 22. Thermoplastic indicating the adhesive sets at an elevated temperature. The group of four dies are attached to the paddle 14 by a controlled thin-adhesive layer 24.
Each of the die bonding pads 26 in double rows are electrically connected to multiple lead fingers 28A, 28B, 28C . . . 28N by thin (0.001 inch) gold or aluminum wires 30A, 30B, 30C . . . 30N; gold being the preferred metal. For clarity, only part of the 18 bonding pads, wires, and fingers are shown. The critical bonding method used at the die end pad 26 is ultrasonic ball bond as named by the shape of the bond as at 32. This first-installed bond and formed gold wire are low-loop wire bonds as seen at critical dimension 34, as will be described later.
The other end of gold wires 30 are attached to the lead fingers by a wedge bond 36, which is also an ultrasonic indicating the use of ultrasonic energy to heat the wire 30 as it is compressed against the lead finger 28. The wedge bond is not used on the die because the bonding machine contacts the bonding surface and could damage this critical surface. The lead fingers may be formed upward as at 38 to permit the use of shorter wires 30.
Paddle 14 which supports the stack is attached to the lead frame typically at four corners as at 40 and also typically, in this application, would have a downset from the lead frame and lead fingers 28 as at dimension 42. The stack is finally encapsulated by a plastic or ceramic at 44.
A dimensional analysis is provided by referring to FIG. 2.
By careful control of layer thicknesses, it is possible to fabricate a four-stack die device having as overall height 46 of about 0.110 inches which is the same height as a current single die. Starting at the bottom, the encapsulation thickness 48 is between 0.010 and 0.012 inches. The paddle 74 thickness 50 can be between 0.005 and 0.010 inches and is a matter of choice. The controlled adhesive-layer thickness 52 can be from 0.001 to 0.005 inches. The individual dies 20, 18, 16, and 12 each have a thickness 54 of 0.012 inches nd the critical controlled, adhesive-layer thicknesses 56 between each die are between 0.008 and 0.010 inches. These thin layers have to be slightly greater than the low-loop wire dimension 34, which is about 0.006 inches. Finally, the top encapsulation 58 is between 0.010 and 0.012 inches so as to cover the top loop.
Thus it can be seen by carefully controlling and minimizing the adhesive layer thicknesses 56, the top and bottom encapsulation thicknesses 48 nd 58, and the paddle adhesive layer 52 that it is possible to have an overall height between 0.108 and 0.110 inches overall for the four-stack die.
If the looser tolerances were used for a two-stack die, the height at 60 would be between 0.058 and 0.073 inches and for a three-die stack it would be from 0.078 to 0.100 inches.
The fabrication of these two or four-stack die devices, necessarily, has to be from the bottom up, since it is not possible to form the die pad wire ball bond 32 on the lower dies 16, 18, and 30, if the four dies are already stacked. This is due to the overhead space required by the wire bond machine.
The die pads 26 of each die can be each connected to an individual lead finger 28 or the dies can be wired in parallel. The former configuration would, therefore, require (for a four die stack) something less than 4×18=72 leads, while parallel connections would require something on the order of 22 or more pins, depending on the type of devices and system requirements. The final packages can be in the form of a small outline J-leaded (SOJ) package, a dual in-line package (DIP), a single in-line package (SIP), a plastic leaded chip carrier (PLCC), and a zig-zag in-line package (ZIP).
While a preferred embodiment of the invention has been disclosed, various modes of carrying out the principles disclosed herein are contemplated as being within the scope of the following claims. Therefore, it is understood that the scope of the invention is not to be limited except as otherwise set forth in the claims.

Claims (7)

What is claimed is:
1. A multiple-die low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer of about 0.001 inches affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first .[.diebonding.]. .Iadd.die-bonding .Iaddend.pads, said wire bond having a wire height above the bonding pad of about 0.006 inches, and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer of about 0.008 inches affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
f. two additional dies affixed above the second die by additional subsequent layers of adhesive of about 0.008 inches and having additional thin wires bonded to additional bonding pads and lead fingers; and
g. an .[.encapsulated.]. .Iadd.encapsulation .Iaddend.layer surrounding all dies, adhesive layers, and thin wires wherein a total encapsulated package height is about 0.110 inches.
2. A multiple-die low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer of about 0.001 to 0.005 inches affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads, said low-loop wire .[.ball.]. bond having a wire height above the .Iadd.first die.Iaddend.-bonding pads of about 0.006 inches and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer of about 0.008 to 0.010 inches affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
f. an .[.encapsulated.]. .Iadd.encapsulation .Iaddend.layer surrounding all die adhesive layers and thin wires wherein a total encapsulation-layer height is about 0.070 inches. .Iadd.
3. A multiple-die low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
f. two additional dies affixed above the second die by additional subsequent layers of adhesive and having additional thin wires bonded to additional bonding pads and lead fingers; and
g. an encapsulation layer surrounding all dies, adhesive layers, and thin wires and having a height of about 0.110 inches. .Iaddend..Iadd.4. The semiconductor device as recited in claim 3 wherein the paddle is downset from the lead fingers and selected lead fingers are formed up thereby providing for additional space within the device and shorter thin wires, respectively. .Iaddend..Iadd.5. The semiconductor device as recited in claim 4 wherein the thin wire is gold, and the first low-loop bond is a ball bond and the second bond is a wedge bond. .Iaddend..Iadd.6. The semiconductor device as recited in claim 3 wherein a low-loop bond wire height above the bonding pad is about 0.006 inches and the second and subsequent thin-adhesive layers are about 0.008 inches. .Iaddend..Iadd.7. The semiconductor device as recited in claim 6 wherein the first
thin-adhesive layer is about 0.001 inches. .Iaddend..Iadd.8. A multiple-die, low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads, said low-loop wire bond having a wire height above the bonding pads of about 0.006 inches and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer of about 0.008 to 0.010 inches affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers; and
f. an encapsulation layer surrounding all die adhesive layers and thin wires. .Iaddend..Iadd.9. The semiconductor device as recited in claim 8 wherein the first thin-adhesive layer is about 0.001 to 0.005 inches. .Iaddend..Iadd.10. The semiconductor device as recited in claim 9 wherein a total encapsulation layer height is about 0.070 inches. .Iaddend..Iadd.11. A multiple-die, low-profile semiconductor device comprising:
a lead-frame paddle supported by a lead frame;
a first adhesive layer affixing a first die above the paddle;
a plurality of wires having first wire bonds to a respective plurality of first die-bonding pads and second wire bonds to a respective plurality of adjacent lead-frame lead fingers;
a second adhesive layer affixing a second die above the first die;
a second plurality of wires having first wire bonds to a respective plurality of second die-bonding pads and second wire bonds to a respective plurality of lead fingers;
two additional dies affixed above the second die by additional subsequent layers of adhesive and having additional wires bonded to additional respective bonding pads and lead fingers; and
an encapsulation layer surrounding all dies, adhesive layers, and wires and having a height of about 0.110 inches. .Iaddend..Iadd.12. The semiconductor device as recited in claim 11, wherein the paddle is downset from the lead fingers and selected lead fingers are formed up thereby providing for additional space within the device and shorter wires, respectively. .Iaddend..Iadd.13. The semiconductor device as recited in claim 12, wherein the wire is gold, and the first bond is a ball bond and
the second bond is a wedge bonds. .Iaddend..Iadd.14. The semiconductor device as recited in claim 11, wherein a bond wire height above the first and second die-bonding pads for all but the uppermost die is about 0.006 inches and the second and subsequent adhesive layers are about 0.008 inches. .Iaddend..Iadd.15. The semiconductor device as recited in claim 14 wherein the first thin-adhesive layer is about 0.001 inches. .Iaddend..Iadd.16. A multiple-die, low-profile semiconductor device comprising:
a lead-frame paddle supported by a lead frame;
a first adhesive layer affixing a first die above the paddle;
a plurality of respective wires having first low-loop wire bonds to a plurality of first die-bonding pads, said low-loop wire bonds having a wire height above the bonding pads of about 0.006 inches, and second wire bonds to a plurality of adjacent lead-frame lead fingers;
a second adhesive layer of about 0.008 to 0.010 inches affixing a second die above the first die;
a second plurality of respective wires having first wire bonds to a plurality of second die-bonding pads and second wire bonds to a respective plurality of lead fingers; and
an encapsulation layer surrounding all die adhesive layers and wires. .Iaddend..Iadd.17. The semiconductor device as recited in claim 16 wherein the first adhesive layer is about 0.001 to 0.005 inches. .Iaddend..Iadd.18. The semiconductor device as recited in claim 17 wherein a total encapsulation layer height is about 0.070 inches. .Iaddend..Iadd.19. A multiple-die, low-profile semiconductor device comprising:
a lead-frame paddle supported by a lead frame;
a first die affixed above the paddle;
an adhesive layer having a thickness and affixing a second die above the first die; and
a plurality of wires having first wire bonds to a respective plurality of first die-bonding pads and second wire bonds to a respective plurality of lead-frame lead fingers, the first wire bonds having loop heights above the first die of less than the thickness of the adhesive layer. .Iaddend..Iadd.20. The semiconductor device of claim 19, further including a second plurality of wires having first wire bonds to a respective plurality of second die-bonding pads and second wire bonds to a respective
plurality of lead fingers. .Iaddend..Iadd.21. The semiconductor device of claim 20, further including two additional dies affixed above the second die by additional subsequent layers of adhesive and having additional wires bonded to additional respective bonding pads and lead fingers, the wires bonded to at least those affixed die below the uppermost die having loop heights above the die to which those wires are bonded of less than the thickness of the adhesive layer affixing the die above. .Iaddend..Iadd.22. The semiconductor device of claim 19, further including an encapsulation layer surrounding all dies, adhesive layers, and wires. .Iaddend..Iadd.23. A multiple-die, low-profile semiconductor device comprising:
a lead-frame paddle supported by a lead frame;
a first die having bonding pads at the periphery thereof and affixed above the paddle;
an adhesive layer having a thickness and affixing a second die above the first die, said adhesive layer leaving the first die peripheral bonding pads uncovered; and
a plurality of wires having first wire bonds to a respective plurality of first die-bonding pads and second wire bonds to a respective plurality of lead-frame lead fingers, the first wire bonds having loop heights above said first die of less than the thickness of said adhesive layer. .Iaddend..Iadd.24. The semiconductor device of claim 23, further including a second plurality of wires having first wire bonds to a respective plurality of second die-bonding pads and second wire bonds to a respective plurality of lead fingers. .Iaddend..Iadd.25. The semiconductor device of claim 24, further including two additional dies affixed above the second die by additional subsequent layers of adhesive and having additional wires bonded to additional respective bonding pads and lead fingers, at least the dies below the uppermost having peripheral bond pads, the adhesive layers leaving the peripheral bond pads uncovered, and the wires bonded to at least those affixed dies except the uppermost die having loop heights above the die to which the wires are bonded of less than the thickness of the adhesive layer affixing the die above.
.Iaddend..Iadd. The semiconductor device of claim 23, further including an encapsulation layer surrounding all dies, adhesive layers, and wires. .Iaddend.
US08/610,127 1993-04-06 1996-02-29 Multi-chip stacked devices Expired - Lifetime USRE36613E (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US08/610,127 USRE36613E (en) 1993-04-06 1996-02-29 Multi-chip stacked devices
US10/346,860 USRE40061E1 (en) 1993-04-06 2003-01-16 Multi-chip stacked devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/043,503 US5291061A (en) 1993-04-06 1993-04-06 Multi-chip stacked devices
US08/610,127 USRE36613E (en) 1993-04-06 1996-02-29 Multi-chip stacked devices

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/043,503 Reissue US5291061A (en) 1993-04-06 1993-04-06 Multi-chip stacked devices

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US42712399A Continuation 1993-04-06 1999-10-21

Publications (1)

Publication Number Publication Date
USRE36613E true USRE36613E (en) 2000-03-14

Family

ID=21927488

Family Applications (2)

Application Number Title Priority Date Filing Date
US08/043,503 Ceased US5291061A (en) 1993-04-06 1993-04-06 Multi-chip stacked devices
US08/610,127 Expired - Lifetime USRE36613E (en) 1993-04-06 1996-02-29 Multi-chip stacked devices

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US08/043,503 Ceased US5291061A (en) 1993-04-06 1993-04-06 Multi-chip stacked devices

Country Status (1)

Country Link
US (2) US5291061A (en)

Cited By (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229202B1 (en) * 2000-01-10 2001-05-08 Micron Technology, Inc. Semiconductor package having downset leadframe for reducing package bow
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US6384487B1 (en) 1999-12-06 2002-05-07 Micron Technology, Inc. Bow resistant plastic semiconductor package and method of fabrication
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6400007B1 (en) * 2001-04-16 2002-06-04 Kingpak Technology Inc. Stacked structure of semiconductor means and method for manufacturing the same
US6414396B1 (en) 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
US6437449B1 (en) 2001-04-06 2002-08-20 Amkor Technology, Inc. Making semiconductor devices having stacked dies with biased back surfaces
US6441495B1 (en) * 1997-10-06 2002-08-27 Rohm Co., Ltd. Semiconductor device of stacked chips
US20020125556A1 (en) * 2001-03-09 2002-09-12 Oh Kwang Seok Stacking structure of semiconductor chips and semiconductor package using it
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US20030006494A1 (en) * 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US20030038356A1 (en) * 2001-08-24 2003-02-27 Derderian James M Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods
US20030038357A1 (en) * 2001-08-24 2003-02-27 Derderian James M. Spacer for semiconductor devices, semiconductor devices and assemblies including the spacer, and methods
US20030042615A1 (en) * 2001-08-30 2003-03-06 Tongbi Jiang Stacked microelectronic devices and methods of fabricating same
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6538303B1 (en) * 1999-06-02 2003-03-25 Sharp Kabushiki Kaisha Lead frame and semiconductor device using the same
US20030071362A1 (en) * 2001-10-15 2003-04-17 Derderian James M. Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6595404B2 (en) * 2000-01-13 2003-07-22 Hitachi, Ltd. Method of producing electronic part with bumps and method of producing electronic part
US6603072B1 (en) 2001-04-06 2003-08-05 Amkor Technology, Inc. Making leadframe semiconductor packages with stacked dies and interconnecting interposer
US6624005B1 (en) 2000-09-06 2003-09-23 Amkor Technology, Inc. Semiconductor memory cards and method of making same
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6657290B2 (en) 2001-01-24 2003-12-02 Sharp Kabushiki Kaisha Semiconductor device having insulation layer and adhesion layer between chip lamination
US6670217B2 (en) 2000-12-11 2003-12-30 Medtronic, Inc. Methods for forming a die package
US20040007771A1 (en) * 1999-08-24 2004-01-15 Amkor Technology, Inc. Semiconductor package and method for fabricating the smae
US20040036157A1 (en) * 2002-08-23 2004-02-26 Salman Akram Semiconductor component with on board capacitor and method of fabrication
US6700210B1 (en) 1999-12-06 2004-03-02 Micron Technology, Inc. Electronic assemblies containing bow resistant semiconductor packages
US20040061202A1 (en) * 2002-09-27 2004-04-01 St Assembly Test Services Pte Ltd Leadframe for die stacking applications and related die stacking concepts
US6717248B2 (en) 1999-05-07 2004-04-06 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US20040065905A1 (en) * 2001-03-27 2004-04-08 Jong Sik Paek Semiconductor package and method for manufacturing the same
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6759307B1 (en) 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
US6759737B2 (en) 2000-03-25 2004-07-06 Amkor Technology, Inc. Semiconductor package including stacked chips with aligned input/output pads
US20040150086A1 (en) * 1999-10-15 2004-08-05 Lee Tae Heon Semiconductor package having reduced thickness
US6777789B1 (en) 2001-03-20 2004-08-17 Amkor Technology, Inc. Mounting for a package containing a chip
US6784090B2 (en) * 1999-06-28 2004-08-31 Sumitomo Electric Industries, Ltd. Semiconductor device and method for manufacturing the same
US6791166B1 (en) 2001-04-09 2004-09-14 Amkor Technology, Inc. Stackable lead frame package using exposed internal lead traces
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6833609B1 (en) 1999-11-05 2004-12-21 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US20040259289A1 (en) * 2003-06-18 2004-12-23 Medtronic, Inc. Method for forming a high-voltage/high-power die package
US20050026395A1 (en) * 2002-01-16 2005-02-03 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US6873032B1 (en) 2001-04-04 2005-03-29 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US20050082679A1 (en) * 2003-07-24 2005-04-21 Infineon Technologies Ag Semiconductor component and production method suitable therefor
US6927478B2 (en) * 2001-01-15 2005-08-09 Amkor Technology, Inc. Reduced size semiconductor package with stacked dies
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US6982485B1 (en) 2002-02-13 2006-01-03 Amkor Technology, Inc. Stacking structure for semiconductor chips and a semiconductor package using it
US20060022323A1 (en) * 2004-07-29 2006-02-02 Swee Seng Eric T Assemblies including stacked semiconductor dice having centrally located, wire bonded bond pads
US20060046436A1 (en) * 2000-09-11 2006-03-02 Shinji Ohuchi Manufacturing method of stack-type semiconductor device
US20060076655A1 (en) * 2003-05-28 2006-04-13 Fernandez Elstan A Integrated circuit package employing a flexible substrate
US20060202319A1 (en) * 2004-08-19 2006-09-14 Swee Seng Eric T Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
US20060220209A1 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US20060246622A1 (en) * 2005-02-22 2006-11-02 Kim Dalson Y S Stacked die package for peripheral and center device pad layout device
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7183630B1 (en) 2002-04-15 2007-02-27 Amkor Technology, Inc. Lead frame with plated end leads
US20070145548A1 (en) * 2003-12-22 2007-06-28 Amkor Technology, Inc. Stack-type semiconductor package and manufacturing method thereof
US20070158809A1 (en) * 2006-01-04 2007-07-12 Chow Seng G Multi-chip package system
US20070158833A1 (en) * 2006-01-04 2007-07-12 Soo-San Park Integrated circuit package system including stacked die
US20070182018A1 (en) * 2006-02-09 2007-08-09 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
USRE40061E1 (en) 1993-04-06 2008-02-12 Micron Technology, Inc. Multi-chip stacked devices
US20080054433A1 (en) * 2006-09-05 2008-03-06 Samsung Electronics Co., Ltd. Multi-chip package with spacer for blocking interchip heat transfer
US20080142942A1 (en) * 2006-12-19 2008-06-19 Yong Du Method and apparatus for multi-chip packaging
US20080179729A1 (en) * 2005-03-31 2008-07-31 Il Kwon Shim Encapsulant cavity integrated circuit package system
US20080246129A1 (en) * 2007-04-04 2008-10-09 Matsushita Electric Industrial Co., Ltd. Method of manufacturing semiconductor device and semiconductor device
US20090091009A1 (en) * 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US20090174054A1 (en) * 2006-07-18 2009-07-09 Christian Block Module with Flat Construction and Method for Placing Components
US7633144B1 (en) 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
US7645634B2 (en) 2005-06-20 2010-01-12 Stats Chippac Ltd. Method of fabricating module having stacked chip scale semiconductor packages
US7675180B1 (en) 2006-02-17 2010-03-09 Amkor Technology, Inc. Stacked electronic component package having film-on-wire spacer
US7687315B2 (en) 2005-04-29 2010-03-30 Stats Chippac Ltd. Stacked integrated circuit package system and method of manufacture therefor
US7692286B1 (en) 2002-11-08 2010-04-06 Amkor Technology, Inc. Two-sided fan-out wafer escape package
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7977163B1 (en) 2005-12-08 2011-07-12 Amkor Technology, Inc. Embedded electronic component package fabrication method
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US8410585B2 (en) 2000-04-27 2013-04-02 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8853836B1 (en) 1998-06-24 2014-10-07 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9466545B1 (en) 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages

Families Citing this family (109)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993023982A1 (en) * 1992-05-11 1993-11-25 Nchip, Inc. Stacked devices for multichip modules
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US6848173B2 (en) * 1994-07-07 2005-02-01 Tessera, Inc. Microelectric packages having deformed bonded leads and methods therefor
JPH08279591A (en) * 1995-04-07 1996-10-22 Nec Corp Semiconductor device and its manufacture
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US5874781A (en) * 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5721452A (en) * 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6884657B1 (en) 1995-08-16 2005-04-26 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6014586A (en) * 1995-11-20 2000-01-11 Pacesetter, Inc. Vertically integrated semiconductor package for an implantable medical device
US5689135A (en) * 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5952725A (en) 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5696031A (en) * 1996-11-20 1997-12-09 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US5817530A (en) * 1996-05-20 1998-10-06 Micron Technology, Inc. Use of conductive lines on the back side of wafers and dice for semiconductor interconnects
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US6784023B2 (en) * 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6682954B1 (en) 1996-05-29 2004-01-27 Micron Technology, Inc. Method for employing piggyback multiple die #3
US5735030A (en) * 1996-06-04 1998-04-07 Texas Instruments Incorporated Low loop wire bonding
US5677567A (en) 1996-06-17 1997-10-14 Micron Technology, Inc. Leads between chips assembly
US6068174A (en) * 1996-12-13 2000-05-30 Micro)N Technology, Inc. Device and method for clamping and wire-bonding the leads of a lead frame one set at a time
US5907769A (en) * 1996-12-30 1999-05-25 Micron Technology, Inc. Leads under chip in conventional IC package
FR2759527B1 (en) * 1997-02-10 2002-07-19 Alsthom Cge Alkatel MONOBLOCK STRUCTURE OF STACKED COMPONENTS
US5994166A (en) 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
US6208018B1 (en) 1997-05-29 2001-03-27 Micron Technology, Inc. Piggyback multiple dice assembly
US5777705A (en) * 1997-05-30 1998-07-07 International Business Machines Corporation Wire bond attachment of a liquid crystal display tile to a tile carrier
US6147411A (en) 1998-03-31 2000-11-14 Micron Technology, Inc. Vertical surface mount package utilizing a back-to-back semiconductor device module
US6329705B1 (en) 1998-05-20 2001-12-11 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes
KR100277438B1 (en) * 1998-05-28 2001-02-01 윤종용 Multi Chip Package
JP3377748B2 (en) * 1998-06-25 2003-02-17 株式会社新川 Wire bonding method
US6297542B1 (en) 1998-06-25 2001-10-02 Micron Technology, Inc. Connecting a die in an integrated circuit module
US6313522B1 (en) 1998-08-28 2001-11-06 Micron Technology, Inc. Semiconductor structure having stacked semiconductor devices
KR100290784B1 (en) 1998-09-15 2001-07-12 박종섭 Stack Package and Manufacturing Method
US6261865B1 (en) 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6677665B2 (en) 1999-01-18 2004-01-13 Siliconware Precision Industries Co., Ltd. Dual-die integrated circuit package
US6815251B1 (en) 1999-02-01 2004-11-09 Micron Technology, Inc. High density modularity for IC's
KR20000066816A (en) * 1999-04-21 2000-11-15 최완균 Method for manufacturing stacked chip package
USRE40112E1 (en) 1999-05-20 2008-02-26 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6161753A (en) * 1999-11-01 2000-12-19 Advanced Semiconductor Engineering, Inc. Method of making a low-profile wire connection for stacked dies
US6337225B1 (en) 2000-03-30 2002-01-08 Advanced Micro Devices, Inc. Method of making stacked die assemblies and modules
US6333562B1 (en) * 2000-07-13 2001-12-25 Advanced Semiconductor Engineering, Inc. Multichip module having stacked chip arrangement
TW455964B (en) * 2000-07-18 2001-09-21 Siliconware Precision Industries Co Ltd Multi-chip module package structure with stacked chips
AU2001280684A1 (en) * 2000-07-20 2002-02-05 Vertical Circuits, Inc. Vertically integrated chip on chip circuit stack
KR100549311B1 (en) * 2000-08-21 2006-02-02 앰코 테크놀로지 코리아 주식회사 Semiconductor package
SG102591A1 (en) 2000-09-01 2004-03-26 Micron Technology Inc Dual loc semiconductor assembly employing floating lead finger structure
US6674161B1 (en) * 2000-10-03 2004-01-06 Rambus Inc. Semiconductor stacked die devices
US6900549B2 (en) * 2001-01-17 2005-05-31 Micron Technology, Inc. Semiconductor assembly without adhesive fillets
TW480686B (en) * 2001-04-03 2002-03-21 Siliconware Precision Industries Co Ltd Intersecting stacked type dual die package structure and manufacturing process
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
US20030221313A1 (en) * 2001-01-26 2003-12-04 Gann Keith D. Method for making stacked integrated circuits (ICs) using prepackaged parts
US7174627B2 (en) * 2001-01-26 2007-02-13 Irvine Sensors Corporation Method of fabricating known good dies from packaged integrated circuits
JP2002231885A (en) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp Semiconductor device
WO2002082527A1 (en) * 2001-04-05 2002-10-17 Stmicroelectronics Pte Ltd Method of forming electrical connections
SG106054A1 (en) 2001-04-17 2004-09-30 Micron Technology Inc Method and apparatus for package reduction in stacked chip and board assemblies
US6559526B2 (en) 2001-04-26 2003-05-06 Macronix International Co., Ltd. Multiple-step inner lead of leadframe
US6828884B2 (en) * 2001-05-09 2004-12-07 Science Applications International Corporation Phase change control devices and circuits for guiding electromagnetic waves employing phase change control devices
KR100520602B1 (en) * 2001-05-19 2005-10-10 앰코 테크놀로지 코리아 주식회사 Stacking structure of semiconductor chip
JP2002359346A (en) * 2001-05-30 2002-12-13 Sharp Corp Semiconductor device and method of stacking semiconductor chips
US6504746B2 (en) * 2001-05-31 2003-01-07 Hewlett-Packard Company High-density low-cost read-only memory circuit
US6531782B1 (en) 2001-06-19 2003-03-11 Cypress Semiconductor Corp. Method of placing die to minimize die-to-die routing complexity on a substrate
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US20050156322A1 (en) * 2001-08-31 2005-07-21 Smith Lee J. Thin semiconductor package including stacked dies
US6847105B2 (en) 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US7211884B1 (en) 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
SG121705A1 (en) * 2002-02-21 2006-05-26 United Test & Assembly Ct Ltd Semiconductor package
US6955941B2 (en) * 2002-03-07 2005-10-18 Micron Technology, Inc. Methods and apparatus for packaging semiconductor devices
US6700206B2 (en) 2002-08-02 2004-03-02 Micron Technology, Inc. Stacked semiconductor package and method producing same
US20040081860A1 (en) * 2002-10-29 2004-04-29 Stmicroelectronics, Inc. Thin-film battery equipment
JP2004221555A (en) * 2002-12-27 2004-08-05 Sumitomo Bakelite Co Ltd Semiconductor element with film pasted, semiconductor device, and manufacturing method therefor
US6861288B2 (en) 2003-01-23 2005-03-01 St Assembly Test Services, Ltd. Stacked semiconductor packages and method for the fabrication thereof
US7309923B2 (en) * 2003-06-16 2007-12-18 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
US6984881B2 (en) * 2003-06-16 2006-01-10 Sandisk Corporation Stackable integrated circuit package and method therefor
US6930378B1 (en) 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
US7132303B2 (en) * 2003-12-18 2006-11-07 Freescale Semiconductor, Inc. Stacked semiconductor device assembly and method for forming
JP4587676B2 (en) * 2004-01-29 2010-11-24 ルネサスエレクトロニクス株式会社 Three-dimensional semiconductor device having a stacked chip configuration
TWM254027U (en) * 2004-03-05 2004-12-21 Teco Image Sys Co Ltd Optical module
TWI242852B (en) * 2004-05-05 2005-11-01 Orient Semiconductor Elect Ltd Semiconductor package
JP2008504627A (en) * 2004-06-30 2008-02-14 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Chip card for holder insertion
US7166924B2 (en) * 2004-08-17 2007-01-23 Intel Corporation Electronic packages with dice landed on wire bonds
US8105932B2 (en) * 2004-08-19 2012-01-31 Infineon Technologies Ag Mixed wire semiconductor lead frame package
WO2006061673A1 (en) * 2004-12-09 2006-06-15 Infineon Technologies Ag Semiconductor package having at least two semiconductor chips and method of assembling the semiconductor package
US7598606B2 (en) * 2005-02-22 2009-10-06 Stats Chippac Ltd. Integrated circuit package system with die and package combination
US7163839B2 (en) * 2005-04-27 2007-01-16 Spansion Llc Multi-chip module and method of manufacture
US8586413B2 (en) * 2005-05-04 2013-11-19 Spansion Llc Multi-chip module having a support structure and method of manufacture
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US7327592B2 (en) * 2005-08-30 2008-02-05 Micron Technology, Inc. Self-identifying stacked die semiconductor components
US20070052079A1 (en) * 2005-09-07 2007-03-08 Macronix International Co., Ltd. Multi-chip stacking package structure
US7429785B2 (en) * 2005-10-19 2008-09-30 Littelfuse, Inc. Stacked integrated circuit chip assembly
US8285379B2 (en) * 2006-01-30 2012-10-09 Medtronic, Inc. Electrical interconnection structures and method
US20080237824A1 (en) * 2006-02-17 2008-10-02 Amkor Technology, Inc. Stacked electronic component package having single-sided film spacer
SG135066A1 (en) 2006-02-20 2007-09-28 Micron Technology Inc Semiconductor device assemblies including face-to-face semiconductor dice, systems including such assemblies, and methods for fabricating such assemblies
US7663232B2 (en) * 2006-03-07 2010-02-16 Micron Technology, Inc. Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems
US7468556B2 (en) * 2006-06-19 2008-12-23 Lv Sensors, Inc. Packaging of hybrid integrated circuits
TWI297945B (en) * 2006-06-20 2008-06-11 Chipmos Technologies Inc Multi-chip stack package having reduced thickness
US7888185B2 (en) * 2006-08-17 2011-02-15 Micron Technology, Inc. Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
US20080054429A1 (en) * 2006-08-25 2008-03-06 Bolken Todd O Spacers for separating components of semiconductor device assemblies, semiconductor device assemblies and systems including spacers and methods of making spacers
TWI314775B (en) * 2006-11-09 2009-09-11 Orient Semiconductor Elect Ltd A film and chip packaging process using the same
US7683468B2 (en) * 2006-12-21 2010-03-23 Tessera, Inc. Enabling uniformity of stacking process through bumpers
US8847413B2 (en) * 2007-01-15 2014-09-30 Stats Chippac Ltd. Integrated circuit package system with leads having multiple sides exposed
US7911053B2 (en) * 2007-04-19 2011-03-22 Marvell World Trade Ltd. Semiconductor packaging with internal wiring bus
US20100219532A1 (en) * 2007-06-01 2010-09-02 Kenji Yamasaki Semiconductor device
US20090001599A1 (en) * 2007-06-28 2009-01-01 Spansion Llc Die attachment, die stacking, and wire embedding using film
US20090051043A1 (en) * 2007-08-21 2009-02-26 Spansion Llc Die stacking in multi-die stacks using die support mechanisms
US8004080B2 (en) * 2009-09-04 2011-08-23 Freescale Smeiconductor, Inc. Edge mounted integrated circuits with heat sink
MY166609A (en) 2010-09-15 2018-07-17 Semiconductor Components Ind Llc Connector assembly and method of manufacture
US9147600B2 (en) * 2013-01-03 2015-09-29 Infineon Technologies Ag Packages for multiple semiconductor chips
US9929123B2 (en) 2015-06-08 2018-03-27 Analog Devices, Inc. Resonant circuit including bump pads
US9520356B1 (en) 2015-09-09 2016-12-13 Analog Devices, Inc. Circuit with reduced noise and controlled frequency

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662351A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor device for memory
JPS60182731A (en) * 1984-02-29 1985-09-18 Toshiba Corp Semiconductor device
US4567643A (en) * 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
JPS62126661A (en) * 1985-11-27 1987-06-08 Nec Corp Hybrid integrated circuit device
JPS63128736A (en) * 1986-11-19 1988-06-01 Olympus Optical Co Ltd Semiconductor element
US4984059A (en) * 1982-10-08 1991-01-08 Fujitsu Limited Semiconductor device and a method for fabricating the same
US4996587A (en) * 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
US5012323A (en) * 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
JPH03169062A (en) * 1989-11-28 1991-07-22 Nec Kyushu Ltd Semiconductor device
US5049976A (en) * 1989-01-10 1991-09-17 National Semiconductor Corporation Stress reduction package and process
JPH0456262A (en) * 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor integrated circuit device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6428856A (en) * 1987-07-23 1989-01-31 Mitsubishi Electric Corp Multilayered integrated circuit

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662351A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor device for memory
US4984059A (en) * 1982-10-08 1991-01-08 Fujitsu Limited Semiconductor device and a method for fabricating the same
US4567643A (en) * 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
JPS60182731A (en) * 1984-02-29 1985-09-18 Toshiba Corp Semiconductor device
JPS62126661A (en) * 1985-11-27 1987-06-08 Nec Corp Hybrid integrated circuit device
JPS63128736A (en) * 1986-11-19 1988-06-01 Olympus Optical Co Ltd Semiconductor element
US5049976A (en) * 1989-01-10 1991-09-17 National Semiconductor Corporation Stress reduction package and process
US4996587A (en) * 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
US5012323A (en) * 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
JPH03169062A (en) * 1989-11-28 1991-07-22 Nec Kyushu Ltd Semiconductor device
JPH0456262A (en) * 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor integrated circuit device

Cited By (208)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE40061E1 (en) 1993-04-06 2008-02-12 Micron Technology, Inc. Multi-chip stacked devices
US6861760B2 (en) 1997-10-06 2005-03-01 Rohm Co., Ltd. Semiconductor device with stacked-semiconductor chips and support plate
US20050153480A1 (en) * 1997-10-06 2005-07-14 Rohm Co., Ltd. Semiconductor device and method for making the same
US7242100B2 (en) 1997-10-06 2007-07-10 Rohm Co., Ltd. Method for manufacturing semiconductor device with plural semiconductor chips
US6441495B1 (en) * 1997-10-06 2002-08-27 Rohm Co., Ltd. Semiconductor device of stacked chips
US8853836B1 (en) 1998-06-24 2014-10-07 Amkor Technology, Inc. Integrated circuit package and method of making the same
US9224676B1 (en) 1998-06-24 2015-12-29 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8963301B1 (en) 1998-06-24 2015-02-24 Amkor Technology, Inc. Integrated circuit package and method of making the same
US6717248B2 (en) 1999-05-07 2004-04-06 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6762078B2 (en) 1999-05-20 2004-07-13 Amkor Technology, Inc. Semiconductor package having semiconductor chip within central aperture of substrate
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6538303B1 (en) * 1999-06-02 2003-03-25 Sharp Kabushiki Kaisha Lead frame and semiconductor device using the same
US6784090B2 (en) * 1999-06-28 2004-08-31 Sumitomo Electric Industries, Ltd. Semiconductor device and method for manufacturing the same
US6982488B2 (en) 1999-08-24 2006-01-03 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US20040007771A1 (en) * 1999-08-24 2004-01-15 Amkor Technology, Inc. Semiconductor package and method for fabricating the smae
US7211900B2 (en) 1999-08-24 2007-05-01 Amkor Technology, Inc. Thin semiconductor package including stacked dies
US20040150086A1 (en) * 1999-10-15 2004-08-05 Lee Tae Heon Semiconductor package having reduced thickness
US6833609B1 (en) 1999-11-05 2004-12-21 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6700210B1 (en) 1999-12-06 2004-03-02 Micron Technology, Inc. Electronic assemblies containing bow resistant semiconductor packages
US6384487B1 (en) 1999-12-06 2002-05-07 Micron Technology, Inc. Bow resistant plastic semiconductor package and method of fabrication
US6440772B1 (en) 1999-12-06 2002-08-27 Micron Technology, Inc. Bow resistant plastic semiconductor package and method of fabrication
US6943457B2 (en) 1999-12-06 2005-09-13 Micron Technology, Inc. Semiconductor package having polymer members configured to provide selected package characteristics
US20040065945A1 (en) * 1999-12-06 2004-04-08 Smith Steven R. Semiconductor package having polymer members configured to provide selected package characteristics
US6803254B2 (en) 1999-12-20 2004-10-12 Amkor Technology, Inc. Wire bonding method for a semiconductor package
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6258624B1 (en) 2000-01-10 2001-07-10 Micron Technology, Inc. Semiconductor package having downset leadframe for reducing package bow
US6229202B1 (en) * 2000-01-10 2001-05-08 Micron Technology, Inc. Semiconductor package having downset leadframe for reducing package bow
US6595404B2 (en) * 2000-01-13 2003-07-22 Hitachi, Ltd. Method of producing electronic part with bumps and method of producing electronic part
US6695200B2 (en) 2000-01-13 2004-02-24 Hitachi, Ltd. Method of producing electronic part with bumps and method of producing electronic part
US6414396B1 (en) 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
US6759737B2 (en) 2000-03-25 2004-07-06 Amkor Technology, Inc. Semiconductor package including stacked chips with aligned input/output pads
US8410585B2 (en) 2000-04-27 2013-04-02 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US9362210B2 (en) 2000-04-27 2016-06-07 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6984544B2 (en) 2000-07-12 2006-01-10 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6906408B2 (en) 2000-07-12 2005-06-14 Micron Technology, Inc. Assemblies and packages including die-to-die connections
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6650019B2 (en) 2000-07-20 2003-11-18 Amkor Technology, Inc. Method of making a semiconductor package including stacked semiconductor dies
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US8258613B1 (en) 2000-09-06 2012-09-04 Amkor Technology, Inc. Semiconductor memory card
US6624005B1 (en) 2000-09-06 2003-09-23 Amkor Technology, Inc. Semiconductor memory cards and method of making same
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US7405138B2 (en) 2000-09-11 2008-07-29 Oki Electric Industry Co., Ltd. Manufacturing method of stack-type semiconductor device
US7019397B2 (en) * 2000-09-11 2006-03-28 Oki Electric Industry Co., Ltd. Semiconductor device, manufacturing method of semiconductor device, stack type semiconductor device, and manufacturing method of stack type semiconductor device
US20060046436A1 (en) * 2000-09-11 2006-03-02 Shinji Ohuchi Manufacturing method of stack-type semiconductor device
US7224070B2 (en) 2000-09-21 2007-05-29 Micron Technology, Inc. Plurality of semiconductor die in an assembly
US7078264B2 (en) 2000-09-21 2006-07-18 Micron Technology, Inc. Stacked semiconductor die
US6759307B1 (en) 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US7045390B2 (en) 2000-12-11 2006-05-16 Medtronic, Inc. Stacked die package
US6696318B2 (en) 2000-12-11 2004-02-24 Medtronic, Inc. Methods for forming a die package
US6670217B2 (en) 2000-12-11 2003-12-30 Medtronic, Inc. Methods for forming a die package
US6927478B2 (en) * 2001-01-15 2005-08-09 Amkor Technology, Inc. Reduced size semiconductor package with stacked dies
US6657290B2 (en) 2001-01-24 2003-12-02 Sharp Kabushiki Kaisha Semiconductor device having insulation layer and adhesion layer between chip lamination
US20060071315A1 (en) * 2001-03-09 2006-04-06 Oh Kwang S Method of forming a stacked semiconductor package
US8143727B2 (en) 2001-03-09 2012-03-27 Amkor Technology, Inc. Adhesive on wire stacked semiconductor package
US20110089564A1 (en) * 2001-03-09 2011-04-21 Amkor Technology, Inc. Adhesive on wire stacked semiconductor package
US20020125556A1 (en) * 2001-03-09 2002-09-12 Oh Kwang Seok Stacking structure of semiconductor chips and semiconductor package using it
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US7863723B2 (en) 2001-03-09 2011-01-04 Amkor Technology, Inc. Adhesive on wire stacked semiconductor package
US6777789B1 (en) 2001-03-20 2004-08-17 Amkor Technology, Inc. Mounting for a package containing a chip
US20040065905A1 (en) * 2001-03-27 2004-04-08 Jong Sik Paek Semiconductor package and method for manufacturing the same
US6873032B1 (en) 2001-04-04 2005-03-29 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US6603072B1 (en) 2001-04-06 2003-08-05 Amkor Technology, Inc. Making leadframe semiconductor packages with stacked dies and interconnecting interposer
US6437449B1 (en) 2001-04-06 2002-08-20 Amkor Technology, Inc. Making semiconductor devices having stacked dies with biased back surfaces
US6791166B1 (en) 2001-04-09 2004-09-14 Amkor Technology, Inc. Stackable lead frame package using exposed internal lead traces
US6400007B1 (en) * 2001-04-16 2002-06-04 Kingpak Technology Inc. Stacked structure of semiconductor means and method for manufacturing the same
US20030006494A1 (en) * 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US20030038357A1 (en) * 2001-08-24 2003-02-27 Derderian James M. Spacer for semiconductor devices, semiconductor devices and assemblies including the spacer, and methods
US20030038356A1 (en) * 2001-08-24 2003-02-27 Derderian James M Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods
US8101459B2 (en) 2001-08-24 2012-01-24 Micron Technology, Inc. Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween
US20040200885A1 (en) * 2001-08-24 2004-10-14 Derderian James M Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween
US20060035408A1 (en) * 2001-08-24 2006-02-16 Derderian James M Methods for designing spacers for use in stacking semiconductor devices or semiconductor device components
US7518223B2 (en) 2001-08-24 2009-04-14 Micron Technology, Inc. Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
US20030042615A1 (en) * 2001-08-30 2003-03-06 Tongbi Jiang Stacked microelectronic devices and methods of fabricating same
US7037756B1 (en) 2001-08-30 2006-05-02 Micron Technology, Inc. Stacked microelectronic devices and methods of fabricating same
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6870269B2 (en) 2001-10-15 2005-03-22 Micron Technology, Inc. Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
US6569709B2 (en) 2001-10-15 2003-05-27 Micron Technology, Inc. Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
US7332372B2 (en) 2001-10-15 2008-02-19 Micron Technology, Inc. Methods for forming assemblies and packages that include stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween
US7335533B2 (en) 2001-10-15 2008-02-26 Micron Technology, Inc. Methods for assembling semiconductor devices in superimposed relation with adhesive material defining the distance adjacent semiconductor devices are spaced apart from one another
US6869828B2 (en) 2001-10-15 2005-03-22 Micron Technology, Inc. Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
US20040157375A1 (en) * 2001-10-15 2004-08-12 Derderian James M. Methods for forming assemblies and packages that include stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween
US20030071362A1 (en) * 2001-10-15 2003-04-17 Derderian James M. Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6919631B1 (en) 2001-12-07 2005-07-19 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US7022418B2 (en) 2002-01-16 2006-04-04 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US7037751B2 (en) 2002-01-16 2006-05-02 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US20050026395A1 (en) * 2002-01-16 2005-02-03 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US20050026415A1 (en) * 2002-01-16 2005-02-03 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US20060159947A1 (en) * 2002-01-16 2006-07-20 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US20060172510A1 (en) * 2002-01-16 2006-08-03 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US6896760B1 (en) 2002-01-16 2005-05-24 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US6982485B1 (en) 2002-02-13 2006-01-03 Amkor Technology, Inc. Stacking structure for semiconductor chips and a semiconductor package using it
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7183630B1 (en) 2002-04-15 2007-02-27 Amkor Technology, Inc. Lead frame with plated end leads
US7041537B2 (en) 2002-08-23 2006-05-09 Micron Technology, Inc. Method for fabricating semiconductor component with on board capacitor
US20040036157A1 (en) * 2002-08-23 2004-02-26 Salman Akram Semiconductor component with on board capacitor and method of fabrication
US6891248B2 (en) 2002-08-23 2005-05-10 Micron Technology, Inc. Semiconductor component with on board capacitor
US20040115865A1 (en) * 2002-08-23 2004-06-17 Salman Akram Method for fabricating semiconductor component with on board capacitor
US7002248B2 (en) 2002-08-23 2006-02-21 Micron Technology, Inc. Semiconductor components having multiple on board capacitors
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US20040061202A1 (en) * 2002-09-27 2004-04-01 St Assembly Test Services Pte Ltd Leadframe for die stacking applications and related die stacking concepts
US6841858B2 (en) 2002-09-27 2005-01-11 St Assembly Test Services Pte Ltd. Leadframe for die stacking applications and related die stacking concepts
US8501543B1 (en) 2002-11-08 2013-08-06 Amkor Technology, Inc. Direct-write wafer level chip scale package
US8710649B1 (en) 2002-11-08 2014-04-29 Amkor Technology, Inc. Wafer level package and fabrication method
US8486764B1 (en) 2002-11-08 2013-07-16 Amkor Technology, Inc. Wafer level package and fabrication method
US7692286B1 (en) 2002-11-08 2010-04-06 Amkor Technology, Inc. Two-sided fan-out wafer escape package
US8691632B1 (en) 2002-11-08 2014-04-08 Amkor Technology, Inc. Wafer level package and fabrication method
US8298866B1 (en) 2002-11-08 2012-10-30 Amkor Technology, Inc. Wafer level package and fabrication method
US7714431B1 (en) 2002-11-08 2010-05-11 Amkor Technology, Inc. Electronic component package comprising fan-out and fan-in traces
US8188584B1 (en) 2002-11-08 2012-05-29 Amkor Technology, Inc. Direct-write wafer level chip scale package
US10665567B1 (en) 2002-11-08 2020-05-26 Amkor Technology, Inc. Wafer level package and fabrication method
US9406645B1 (en) 2002-11-08 2016-08-02 Amkor Technology, Inc. Wafer level package and fabrication method
US8119455B1 (en) 2002-11-08 2012-02-21 Amkor Technology, Inc. Wafer level package fabrication method
US8952522B1 (en) 2002-11-08 2015-02-10 Amkor Technology, Inc. Wafer level package and fabrication method
US9871015B1 (en) 2002-11-08 2018-01-16 Amkor Technology, Inc. Wafer level package and fabrication method
US7932595B1 (en) 2002-11-08 2011-04-26 Amkor Technology, Inc. Electronic component package comprising fan-out traces
US9054117B1 (en) 2002-11-08 2015-06-09 Amkor Technology, Inc. Wafer level package and fabrication method
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US20060076655A1 (en) * 2003-05-28 2006-04-13 Fernandez Elstan A Integrated circuit package employing a flexible substrate
US7659620B2 (en) 2003-05-28 2010-02-09 Infineon Technologies, Ag Integrated circuit package employing a flexible substrate
US6991961B2 (en) 2003-06-18 2006-01-31 Medtronic, Inc. Method of forming a high-voltage/high-power die package
US20040259289A1 (en) * 2003-06-18 2004-12-23 Medtronic, Inc. Method for forming a high-voltage/high-power die package
US20050082679A1 (en) * 2003-07-24 2005-04-21 Infineon Technologies Ag Semiconductor component and production method suitable therefor
US7161234B2 (en) * 2003-07-24 2007-01-09 Infineon Technologies Ag Semiconductor component and production method suitable therefor
US20070145548A1 (en) * 2003-12-22 2007-06-28 Amkor Technology, Inc. Stack-type semiconductor package and manufacturing method thereof
US8237290B2 (en) 2004-07-29 2012-08-07 Micron Technology, Inc. Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
US9070641B2 (en) 2004-07-29 2015-06-30 Micron Technology, Inc. Methods for forming assemblies and multi-chip modules including stacked semiconductor dice
US20090121338A1 (en) * 2004-07-29 2009-05-14 Micron Technology, Inc. Assemblies and multi chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
US11101245B2 (en) 2004-07-29 2021-08-24 Micron Technology, Inc. Multi-chip modules including stacked semiconductor dice
US20060022323A1 (en) * 2004-07-29 2006-02-02 Swee Seng Eric T Assemblies including stacked semiconductor dice having centrally located, wire bonded bond pads
US7276790B2 (en) 2004-07-29 2007-10-02 Micron Technology, Inc. Methods of forming a multi-chip module having discrete spacers
US7492039B2 (en) * 2004-08-19 2009-02-17 Micron Technology, Inc. Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
US20060202319A1 (en) * 2004-08-19 2006-09-14 Swee Seng Eric T Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
US8269328B2 (en) 2005-02-22 2012-09-18 Micron Technology, Inc. Stacked die package for peripheral and center device pad layout device
US7846768B2 (en) 2005-02-22 2010-12-07 Micron Technology, Inc. Stacked die package for peripheral and center device pad layout device
US7205656B2 (en) 2005-02-22 2007-04-17 Micron Technology, Inc. Stacked device package for peripheral and center device pad layout device
US20110062583A1 (en) * 2005-02-22 2011-03-17 Micron Technology, Inc. Stacked die package for peripheral and center device pad layout device
US20060246622A1 (en) * 2005-02-22 2006-11-02 Kim Dalson Y S Stacked die package for peripheral and center device pad layout device
US20080280396A1 (en) * 2005-02-22 2008-11-13 Micron Technology, Inc. Stacked die package for peripheral and center device pad layout device
US7425463B2 (en) 2005-02-22 2008-09-16 Micron Technology, Inc. Stacked die package for peripheral and center device pad layout device
US8021924B2 (en) 2005-03-31 2011-09-20 Stats Chippac Ltd. Encapsulant cavity integrated circuit package system and method of fabrication thereof
US20080179729A1 (en) * 2005-03-31 2008-07-31 Il Kwon Shim Encapsulant cavity integrated circuit package system
US20110018084A1 (en) * 2005-03-31 2011-01-27 Il Kwon Shim Encapsulant cavity integrated circuit package system and method of fabrication thereof
US7372141B2 (en) * 2005-03-31 2008-05-13 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US7855100B2 (en) 2005-03-31 2010-12-21 Stats Chippac Ltd. Integrated circuit package system with an encapsulant cavity and method of fabrication thereof
US20060220209A1 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US8309397B2 (en) 2005-03-31 2012-11-13 Stats Chippac Ltd. Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof
US7687315B2 (en) 2005-04-29 2010-03-30 Stats Chippac Ltd. Stacked integrated circuit package system and method of manufacture therefor
US7645634B2 (en) 2005-06-20 2010-01-12 Stats Chippac Ltd. Method of fabricating module having stacked chip scale semiconductor packages
US7977163B1 (en) 2005-12-08 2011-07-12 Amkor Technology, Inc. Embedded electronic component package fabrication method
US20070158833A1 (en) * 2006-01-04 2007-07-12 Soo-San Park Integrated circuit package system including stacked die
US20070158809A1 (en) * 2006-01-04 2007-07-12 Chow Seng G Multi-chip package system
US7652376B2 (en) 2006-01-04 2010-01-26 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7768125B2 (en) 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US20070182018A1 (en) * 2006-02-09 2007-08-09 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US7750482B2 (en) 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US7675180B1 (en) 2006-02-17 2010-03-09 Amkor Technology, Inc. Stacked electronic component package having film-on-wire spacer
US8072083B1 (en) 2006-02-17 2011-12-06 Amkor Technology, Inc. Stacked electronic component package having film-on-wire spacer
US7633144B1 (en) 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US8129849B1 (en) 2006-05-24 2012-03-06 Amkor Technology, Inc. Method of making semiconductor package with adhering portion
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US20090174054A1 (en) * 2006-07-18 2009-07-09 Christian Block Module with Flat Construction and Method for Placing Components
US20080054433A1 (en) * 2006-09-05 2008-03-06 Samsung Electronics Co., Ltd. Multi-chip package with spacer for blocking interchip heat transfer
US8698304B2 (en) * 2006-09-05 2014-04-15 Samsung Electronics Co., Ltd. Multi-chip package with spacer for blocking interchip heat transfer
US7691668B2 (en) * 2006-12-19 2010-04-06 Spansion Llc Method and apparatus for multi-chip packaging
US20080142942A1 (en) * 2006-12-19 2008-06-19 Yong Du Method and apparatus for multi-chip packaging
US8324716B2 (en) 2006-12-19 2012-12-04 Spansion Llc Method and apparatus for multi-chip packaging
US20100164124A1 (en) * 2006-12-19 2010-07-01 Yong Du Method and apparatus for multi-chip packaging
US9466545B1 (en) 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US9768124B2 (en) 2007-02-21 2017-09-19 Amkor Technology, Inc. Semiconductor package in package
US20080246129A1 (en) * 2007-04-04 2008-10-09 Matsushita Electric Industrial Co., Ltd. Method of manufacturing semiconductor device and semiconductor device
US20090091009A1 (en) * 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
TWI398938B (en) * 2007-10-03 2013-06-11 Micron Technology Inc Stackable integrated circuit package
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US10546833B2 (en) 2009-12-07 2020-01-28 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9324614B1 (en) 2010-04-06 2016-04-26 Amkor Technology, Inc. Through via nub reveal method and structure
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US9159672B1 (en) 2010-08-02 2015-10-13 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8900995B1 (en) 2010-10-05 2014-12-02 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US9082833B1 (en) 2011-01-06 2015-07-14 Amkor Technology, Inc. Through via recessed reveal structure and method
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9947623B1 (en) 2011-11-29 2018-04-17 Amkor Technology, Inc. Semiconductor device comprising a conductive pad on a protruding-through electrode
US10410967B1 (en) 2011-11-29 2019-09-10 Amkor Technology, Inc. Electronic device comprising a conductive pad on a protruding-through electrode
US8981572B1 (en) 2011-11-29 2015-03-17 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US11043458B2 (en) 2011-11-29 2021-06-22 Amkor Technology Singapore Holding Pte. Ltd. Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode
US9431323B1 (en) 2011-11-29 2016-08-30 Amkor Technology, Inc. Conductive pad on protruding through electrode
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US10014240B1 (en) 2012-03-29 2018-07-03 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method

Also Published As

Publication number Publication date
US5291061A (en) 1994-03-01

Similar Documents

Publication Publication Date Title
USRE36613E (en) Multi-chip stacked devices
US5963794A (en) Angularly offset stacked die multichip device and method of manufacture
US5886412A (en) Angularly offset and recessed stacked die multichip device
US6051886A (en) Angularly offset stacked die multichip device and method of manufacture
US7381593B2 (en) Method and apparatus for stacked die packaging
US6261865B1 (en) Multi chip semiconductor package and method of construction
US6087722A (en) Multi-chip package
KR0179803B1 (en) Lead-exposured semiconductor package
US7199458B2 (en) Stacked offset semiconductor package and method for fabricating
US8049342B2 (en) Semiconductor device and method of fabrication thereof
US7084490B2 (en) Leads under chip IC package
US7015587B1 (en) Stacked die package for semiconductor devices
US7968996B2 (en) Integrated circuit package system with supported stacked die
US20070052079A1 (en) Multi-chip stacking package structure
US6483181B2 (en) Multi-chip package
US8759954B2 (en) Integrated circuit package system with offset stacked die
US7622794B1 (en) COL (Chip-On-Lead) multi-chip package
US6884657B1 (en) Angularly offset stacked die multichip device and method of manufacture
JPH07153904A (en) Manufacture of laminar type semiconductor device, and semiconductor package manufactured thereby
USRE40061E1 (en) Multi-chip stacked devices
KR940008325B1 (en) Laminated type semiconductor device
JPS6370532A (en) Semiconductor device
KR20060076455A (en) Chip stack package
KR20010053953A (en) Multi chip package

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: MERGER;ASSIGNOR:MICRON SEMICONDUCTOR, INC.;REEL/FRAME:013684/0806

Effective date: 19941028

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223