USRE37048E1 - Field programmable digital signal processing array integrated circuit - Google Patents
Field programmable digital signal processing array integrated circuit Download PDFInfo
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- USRE37048E1 USRE37048E1 US08/946,928 US94692897A USRE37048E US RE37048 E1 USRE37048 E1 US RE37048E1 US 94692897 A US94692897 A US 94692897A US RE37048 E USRE37048 E US RE37048E
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- the present invention relates to integrated circuits and, more specifically, to user-programmable integrated circuits. More particularly, the present invention relates to user-programmable mixed analog and digital integrated circuits.
- General purpose linear integrated circuits have limited themselves to specific functions such as operational amplifiers, phase locked loops, comparators, A/D converters, video amplifiers, transistor arrays, etc. These circuits form the building blocks of analog systems. Integrating these circuits into higher functions is difficult due to the need to employ external components (i.e., resistors, capacitors, inductors, etc.) to determine their exact function. Thus once integrated, these circuits become specialized. In order to be practicable for design, manufacture, and sale, such a specialized part must have a large usage base.
- One illustrative example of such a circuit is an audio amplifier which may be used in stereo systems or television sets. Without a large usage base, the design and manufacture of such a circuit is not economical.
- Another common problem in electronics is that various parts of a complex signal need to be kept in phase while utilizing different circuit paths. This For example, this is commonly done in color television sets where the luminance information is routed through a delay line while the chrominance information is processed.
- DSP digital signal processing
- a fundamental limitation of these integrated DSP devices is that the device speed is limited by the Von Neuman architecture of the microprocessor where many processor functions are required for each time slice of the analog signal. This limitation has heretofore limited the speed of such devices to frequencies in the audio spectrum. This is of course due to the fact that the customization of the function is achieved by the coding of the instructions in the microprocessor.
- MIMD multiple instruction multiple data or single instruction multiple data
- SIMD multiple instruction multiple data or single instruction multiple data
- Yet another object of the present invention is to provide a user-programmable digital signal processing integrated circuit which allows the user to control phase shifting of signals being processed therein.
- a field programmable, digital signal processing integrated circuit is formed in a semiconductor die and includes an array of arithmetic logic unit (ALU) circuits.
- a user programmable interconnect architecture is superimposed on the array of ALU circuits.
- One or more interface circuits comprising digital-to-analog (D/A) converters or analog-to-digital (A/D) converters are provided on (or off) the integrated circuit to interface to off-chip analog input signals and provide off-chip analog output signals.
- Other functional circuit blocks such as programmable read only memory (PROM) or Random Access Memory (RAM) circuits may also be disposed on the integrated circuit die.
- Circuitry is provided to program the interconnections between the interface circuits and the ALU circuits and between individual ones of the ALU circuits, as well as to define the specific functions of the individual ALU circuits.
- the architecture of the present invention avoids the Von Neuman bottle neck characteristic of prior art systems by eliminating the need for sequential instructions.
- Each ALU circuit of the present invention may be user customized to act like the mathematical equivalent of an analog circuit element.
- the individual ALU circuits are interconnected to one another and to A/D and D/A interface circuits by user-programmable interconnect elements.
- FIG. 1 is a block diagram of the architecture for an illustrative field programmable digital signal processing integrated circuit according to a preferred embodiment of the present invention.
- FIG. 2 a 2 A is a block diagram of an illustrative ALU circuit suitable for inclusion in the field programmable digital signal processing integrated circuit according to the present invention.
- FIG. 2 b 2 B is a state diagram which discloses in detail the operation of the control circuit portion of the ALU circuit of FIG. 2 a 2 A.
- FIG. 3 is a schematic diagram of an architecture for a bus interchange which can perform a single or multibit shift operation.
- FIG. 4 a 4 A is a schematic diagram of a simple inverting analog amplifier.
- FIG. 4 b 4 B is an equivalent block diagram of the amplifier of FIG. 4 a 4 A implemented according to the present invention.
- FIG. 4 c 4 C is an equivalent block diagram of the amplifier of FIG. 4 a 4 A implemented according to the present invention and including a logarithmic feedback element.
- FIG. 5 is a graph showing the waveforms of the signal input and signal output waveform of the circuit of FIG. 4 b 4 B for a sinusoidal input waveform.
- FIG. 6 is a graph showing the waveforms of the signal input and signal output waveform of the circuit of FIG. 4 b 4 B for a square input waveform.
- FIG. 7 a 7 A is a schematic diagram of a variation of the amplifier circuit of FIG. 4 a 4 A.
- FIG. 7 b 7 B is an equivalent block diagram of the amplifier of FIG. 7 a 7 A implemented according to the present invention in a manner which avoids pipelining distortion in the output.
- FIG. 8 is a graph showing the input and output voltages of the circuit of FIG. 7 b 7 B for 1 MHz sine wave input.
- FIG. 9 is a graph showing the input and output voltages of the circuit of FIG. 7 b 7 B for 1 MHz square wave input.
- FIG. 10 is a block diagram of an illustrative analog shift register configured using the architecture of the present invention.
- FIGS. 11 a 11 A and 11 b 11 B are examples of a series RLC tuned circuit implemented according to the present invention.
- FIG. 1 a block diagram is presented of the architecture for an illustrative field programmable digital signal processing integrated circuit according to a preferred embodiment of the present invention.
- the architecture of the present invention is integrated on a single piece of semiconductor material, and may be fabricated using known semiconductor processing technology, such as CMOS technology, which is presently preferred.
- the field programmable digital signal processing integrated circuit 10 of the present invention is built around an array of arithmetic logic unit (ALU) circuits shown at reference numerals 12 - 1 through 12 - 9 .
- ALU arithmetic logic unit
- arithmetic logic units 12 - 1 through 12 - 9 are shown arranged as a regular array comprising three rows and three columns of ALU circuits.
- FIG. 1 is illustrative only and not limiting, in that such skilled persons will readily recognize that other numbers of ALU circuits and other layout arrangements may be employed.
- At least one analog-to-digital (A/D) converter and at least one digital-to-analog (D/A) converter circuit may be optionally disposed on the integrated circuit along with the ALU circuits.
- A/D circuits 14 - 1 and 14 - 2 and two D/A circuits 16 - 1 and 16 - 2 are shown.
- A/D converters 14 - 1 and 14 - 2 and D/A converters 16 - 1 and 16 - 2 will probably be located near the periphery of the integrated circuit die upon which the architecture 10 of the present invention is disposed, but those of ordinary skill in the art will understand that placement of these devices is largely a matter of design choice. Such elements may even be located off chip in certain applications.
- I/O input/output
- the number of I/O pins provided on any actual embodiment of the architecture of the present invention will be purely a matter of design choice.
- a group of such I/O pins is depicted as a single I/O block 18 , but those of ordinary skill in the art will recognize that I/O block 18 represents a plurality of I/O pins.
- PROM devices 20 - 1 and 20 - 2 are shown disposed in the integrated circuit architecture 10 of the present invention.
- RAM and ROM circuits may be usefully employed in the architecture of the present invention.
- a user-programmable interconnect architecture is superimposed upon the aforementioned circuit elements.
- the user-programmable interconnect architecture is used to connect the aforementioned circuit elements to one another and to the I/O pins.
- User-programmable interconnect architectures include a plurality of interconnect conductors which may be connected to one another, to inputs and outputs of the various circuit elements, and to the I/O pins by user-programmable interconnect elements.
- These user-programmable interconnect elements may take several forms as is known in the art. Examples of such elements include antifuses, of which there are numerous known examples, such as those disclosed in U.S. Pat. Nos. 4,899,205, and 5,070,384, and 5,181,096, and pass transistors, such as disclosed in the architecture described in U.S. Pat. No. 4,870,302. Those of ordinary skill in the art will recognize that these examples are non-exhaustive and merely illustrate the state of the user-programmable interconnect element art.
- user-programmable interconnect element as used herein shall be construed to cover all forms of such interconnect elements.
- the structure, design, and use of such user-programmable interconnect elements is well known in the art and will not be recited herein.
- FIG. 1 the user-programmable interconnect architecture is shown diagrammatically as horizontal interconnect conductors 22 and vertical interconnect conductors 24 which are distributed throughout and among the circuit elements of FIG. 1 .
- FIG. 1 is very general in this respect.
- the lines identified by reference numerals 22 and 24 in the drawing figure are not intended to represent individual interconnect conductors but rather represent groups of conductors. An actual arrangement of interconnect conductors useful for employment in the present invention will be disclosed in subsequent figures and text herein.
- some of the conductors will be segmented and some conductors may run the entire length or width of the array of circuit elements in the architecture.
- Individual user programmable interconnect elements will be connected between selected adjacent segments of the interconnect conductors to selectively lengthen them, and other individual user-programmable interconnect elements will be positioned between intersecting horizontal and vertical segments of the interconnect conductors. Nonexhaustive examples of the segmenting of individual interconnect conductors are seen in U.S. Pat. Nos. 4,870,302, 4,758,745, and 5,073,729.
- the interconnect conductor groups may communicate with the I/O pins, either directly, as shown in FIG. 1 by leftmost and rightmost vertical interconnect conductor groups 24 entering I/O block 18 , or through appropriate input and output buffers as is known in the art.
- This feature of the present invention allows a number of integrated circuits according to the present invention to be connected together to form larger circuits, which may be clocked together as will be described further herein.
- FIG. 2 a 2 A the structure and organization of a presently preferred single ALU circuit 12 suitable for use in the architecture of the present invention is depicted in block diagram form.
- ALU circuit 12 may be configured using standard CMOS building blocks for circuits of this type.
- CMOS building blocks for circuits of this type.
- ALU circuit 12 includes an a first 2:1 multiplexer 26 and a second 2:1 multiplexer 28 . Both the first and second multiplexers 26 and 28 are n-bits wide, where n is the width of the data byte used by the ALU circuit 12 .
- the byte size used in any actual embodiment of the invention could be from 2-64 bits wide and will be dictated by resolution, size, and other design considerations.
- a typical byte size might be, for example, 8 bits.
- Practically a data byte would be the width of the A/D and D/A converters used. This would be for instance 8 or 10 bits in the case of Video D/A converters and 18 bits for Audio D/A converters.
- the voltage in tuned reactive circuits is Q (quality factor) times higher than the input voltage.
- Q quality factor
- a Q may be as high as 100, which would require an extra 8 bits to be added to the ALU circuits 12 to accommodate the voltage, resulting in 16 to 18 bits for Video D/A converters.
- the programmable circuit is optimized for reactive circuits, only the internal nodes of the reactive circuits need be this size.
- the rest of the ALU circuit 12 data paths could be 8 to 10 bits wide.
- ALU circuits 12 Another solution to this problem would be to configure all of the ALU circuits 12 to be 8 to 10 bits wide and to program an AGC circuit consisting of a peak detector, a comparator and gain adjust circuit into the circuit to reduce the input signal amplitude to the reactive circuit module, thereby preventing the ALU circuit 12 from overflowing.
- AGC circuit consisting of a peak detector, a comparator and gain adjust circuit into the circuit to reduce the input signal amplitude to the reactive circuit module, thereby preventing the ALU circuit 12 from overflowing.
- first 2:1 multiplexer 26 are connected to n-wide input busses 34 and 36
- data inputs (C and D) of second 2:1 multiplexer 28 are connected to n-wide input busses 32 and 34 .
- the input busses physically exit the ALU circuit 12 in different directions to maximize the interconnect possibilities.
- one end of input busses 30 , 32 , 34 , and 36 might exit the ALU block horizontally and one end may exit vertically to permit connection to both horizontal and vertical interconnect conductors in the interconnect matrix of the integrated circuit, thus allowing for greater interconnect possibilities. This is shown diagrammatically in FIG.
- ALU circuit 12 - 1 in the region of ALU circuit 12 - 1 at reference numerals 30 a, 32 a, and 34 a. While only one ALU circuit 12 - 1 is shown having such an input structure in FIG. 1, in order to avoid cluttering up the drawing, those of ordinary skill in the art will recognize that it is preferable for all ALU circuits to be similarly configured.
- control inputs 38 and 40 of first and second 2:1 multiplexers 26 and 28 are brought to an interconnect matrix which includes conductor 42 carrying the Vcc potential for the integrated circuit, conductor 44 carrying ground potential, and general interconnect conductors 46 , 48 , and 50 .
- the small circles in the interconnect matrix at the intersections of control inputs 38 and 40 and conductors 42 , 44 , 46 , 48 , and 50 represent user programmable interconnect elements, such as antifuses or pass transistors.
- control inputs 38 and 40 of the multiplexers 26 and 28 can be hardwired to Vcc or ground to preselect the data source or can be hardwired to data sources via one of general interconnect conductors 46 , 48 , or 50 to dynamically alter the signal sources during circuit operation.
- negate circuits 52 and 54 The outputs of first and second 2:1 multiplexers 26 and 28 are directed to negate circuits 52 and 54 .
- the function of negate circuits 52 and 54 is to selectively invert the data state of the input, and the circuits may be configured from exclusive OR gates as is known in the art.
- the control inputs 56 and 58 of negate circuits 52 and 54 are brought into the interconnect matrix, thus allowing maximum flexibility of the negate function.
- the outputs of negate circuits 52 and 54 drive the Latch A latches 60 and 62 .
- the outputs of Latch A latches 60 and 62 form the input terms for adder 64 .
- Adder 64 may be a conventional multibit adder circuit.
- the output of adder 64 drives the input of Latch B latch 66 .
- the output of Latch B latch 66 is connected to output bus 68 .
- control circuit 70 The Latch A latches 60 and 62 and Latch B latch 66 are controlled by a control circuit 70 .
- the purpose of control circuit 70 is to synchronize the operation of the ALU circuit to assure that the operation of the circuit is coordinated with the arrival of the correct data to be processed by the ALU circuit.
- Control circuit 70 has a clock (CLK) input 72 , an enable (EN) input 74 and an input-ready in (INRIN) input 76 . These inputs are incorporated into an interconnect matrix including two clock lines CLKA line 78 , CLKB line 80 , and three general interconnect conductors 82 , 84 , and 86 .
- the input lines 72 , 74 and 76 are connectable to any of lines 78 , 80 , 82 , 84 and 86 by the user programmable interconnect elements shown as small circles at the intersections of the lines 78 , 80 , 82 , 84 and 86 and the input lines 72 , 74 and 76 .
- the connectivity choices shown in FIG. 2 a 2 A are only illustrative, and that the actual choices in an architecture built in accordance with the teachings of the present invention will be dictated largely as a matter of design choice.
- Control circuit 70 has four outputs. Output A (line 88 ) drives the clocks of the Latch A Latches 60 and 62 , and output B (line 90 ) drives the clock of the Latch B latch 66 .
- INROUT line 92 is used for asynchronous connection of modules and is an input-read output signal which would be connected to the input-read (INRIN) input of the module connected upstream so that the upstream module will release data on the next clock.
- DATARDY line 94 is a data ready output used to indicate that data is valid for the next module downstream to read.
- the ALU circuit 12 of FIG. 2 a 2 A may be configured to perform the customary logical functions performed by ALU circuits.
- FIG. 2 b 2 B a state diagram is presented, showing in detail the operation of the control circuit 12 portion of the ALU circuit of FIG. 2 a 2 A.
- synchronous stages will not need to utilize the INRIN and INROUT lines 76 and 92 .
- Asynchronous stages will use the INRIN and INROUT lines 76 and 92 at the interface.
- Occasional bytes may be lost, but this should not affect the overall operation of any circuits configured using the architecture of the present invention. Lost bytes may be averaged out by (A+B)/2 of subsequent data bytes until smoothness level is achieved, so long as the number of data samples per cycle are is adequate.
- the organization of the interconnect architecture of the present invention makes it possible to utilize the interconnect itself to perform mathematical functions such as multiply and divide.
- This feature of the present invention is advantageous in that such operations may be performed in the same clock cycle as the operations performed by the ALU circuit whose output is driving the interconnect conductors.
- the speed will be limited by the rate at which the ALU circuits can perform an addition (subtraction) and a multiplication (division).
- the multiplication and division are the mathematical processes that take the most time. If, however, the application circuit is designed to use circuit elements such as resistors, capacitors, inductors etc. in units of the power of 2, i.e., 2, 4, 8, 16, etc., the multiplication and division may be digitally represented by a shift left or a shift right operation.
- FIG. 3 shows a plurality of horizontal interconnect conductors 22 - 1 through 22 - 6 intersecting a plurality of vertical interconnect conductors 24 - 1 through 24 - 6 .
- a transistor 96 - 1 through 96 - 36 is connected between the horizontal and vertical interconnect conductors.
- the gates of diagonally-situated ones of the transistors are connected together to one of gate lines 98 - 1 through 98 - 11
- bit shifting technique can be implemented by other user-programmable interconnect devices such as antifuses.
- intersecting conductive lines may be connected by antifuses and the bit shifting to the left or right may be accomplished by selective programming of the antifuses.
- a bus interchange like that depicted in FIG. 3 may be placed at the intersection of horizontal and vertical interconnect conductors such as 22 and 24 and may also be employed to connect an input bus or an output bus of an ALU circuit to the horizontal and vertical interconnect busses of the interconnect architecture. It is apparent that the multiplication and division operations implemented by the shift function disclosed herein will take no significant time, and will certainly occur in the same clock cycle used to operate the driving ALU circuit. Hence those of ordinary skill in the art will appreciate that the architecture of the present invention can perform functions with the same approximate speed as high speed analog operational amplifiers.
- the value of R as any power of 2 may be preprogrammed into the ALU circuit by shifting the output bus one or more bit positions. This function could be achieved in one clock cycle and the digital resistor performs the same function on each clock cycle, i.e. subtract two input numbers and divide by a preprogrammed constant.
- the architecture of the present invention eliminates the need for program storage.
- the division operation for calculating capacitances whose values are powers of 2 is automatically performed as a result of a bit shift of one or more places in the opposite direction from that for a multiplication operation. Similar simple functions exist for inductors and transformers and operational amplifiers, comparators, ideal diodes, switches or multiplexers, which are the building blocks of analog electronics.
- the user-programmed interconnect of the digital ALU circuits would be a one-to-one map of the analog equivalent.
- the additional integration of digital signals is simple because the digital gates would be made of the same type of transistors for digital circuits.
- the digital modules may use similar logic as is currently available in Gate arrays, FPGA's FPGAs and PAL's PALs.
- the interconnection of the analog elements may of course be made in the same manner as used in Gate arrays, FPGA's FPGAs and PAL's PALs.
- An integrated circuit according to the present invention is easily customizable, suitable for mixing analog and digital functions, and can be extremely fast, capable of working with analog signals in the RF and Video frequency ranges.
- the limiting frequency will likely be the rate of A/D and D/A conversions at the boundaries of the system. Flash converters currently work in the tens of megahertz.
- the A/D and D/A converters could either be on chip or off chip depending on the desire of the designed/manufacturer.
- FIGS. 4 a 4 A and 4 b 4 B a simple design of an inverting unity gain amplifier is shown as an example of the operation of the architecture of the present invention.
- FIG. 4 a 4 A is a schematic diagram of the analog equivalent circuit including two one ohm resistors, a 40 nF capacitor, and an amplifier having a slew rate of 0.25 V/V IN .
- FIG. 4 b 4 B is a block diagram of the digital equivalent circuit as implemented in the architecture of the present invention.
- An analog input voltage is supplied to A/D converter 100 , which presents its output to ALU 102 , programmed to behave as the resistor R 1 in the circuit of FIG. 4 a 4 A.
- ALU 104 is programmed to behave as capacitor C
- ALU 106 is programmed to behave as resistor R 2
- ALU 108 is programmed to behave as the amplifier element.
- the entire circuit is driven by a 100 MHz clock 110 .
- ALU 102 resistor 1 R 1
- FIG. 5 is a graph showing the waveforms of the signal input and signal output waveform of the circuit for a sinusoidal input waveform. It may be seen from FIG. 5 that the output of the amplifier is somewhat “phase shifted” due to the pipelining time for the data through the ALU system which emulates the analog amplifier.
- FIG. 6 is a graph showing the waveforms of the signal input and signal output waveform of the circuit of FIG. 4 b 4 B for a square input waveform.
- the damped overshoot characteristic which is typical of analog amplifiers may be seen on the output waveform.
- re-arranging the architecture of the emulated amplifier circuit can eliminate the distortion exhibited by the circuit of FIG. 4 b 4 B which is apparent in FIGS. 5 and 6.
- FIGS. 7 a 7 A and 7 b 7 B an alternate configuration can be configured by employing a slower master clock and using the data-valid (INR and OUTR) connections of the ALU circuits.
- the same reference numerals are used in the circuits of FIGS. 4 b 4 B and 7 b 7 B, but the capacitor C has a value of 60 nF and the amplifier has a gain of 2.
- FIGS. 8 and 9 are graphs showing the input and output voltages of the circuit of FIG. 7 b 7 B for 1 MHz sine and square wave inputs, respectively.
- Those of ordinary skill in the art will recognize that, while the phase of the output voltages are lagging the input voltages, the square wave output is completely free of overshoot.
- Such skilled persons will also recognize that, due to the slower clocking speed (i.e., 33 MHz as opposed to 100 MHz for the circuit of FIG. 4 b 4 B), fewer data points are used to define the output function.
- the architecture of the present invention may be used to implement an analog shift register as shown in FIG. 10, thus making possible any length delay without phase alteration.
- three ALU modules 120 , 122 and 124 are shown connected as an analog shift register.
- the ALU modules are configured to compute the function (V 1 +0)/1, by connecting the B input busses of each to ground and the A input busses of each module to the output bus of the preceding ALU module in the chain.
- This technique may be used to configure an analog shift register chain of arbitrary length, although only three stages are shown in FIG. 10 .
- the present invention may also be employed to simulate tuned circuits.
- the actual value of the circuit element is also a function of the frequency at which the circuit is clocked. If the number that is output is the value of a current, then the time period of the ALU clock signal will represent a current multiplied by time. Therefore the circuit output value is an amount of charge or Q.
- a capacitor ALU having a digital value 1 clocked at a clock frequency of 100 MHz will be have a value of C/clock frequency, or 10 nanofarads.
- the actual value of the circuit elements will be set by the clock frequency of the ALU.
- One technique to avoid this problem in the circuits configured according to the present invention is to make a small FIFO of, for example, three signal bytes. This would require the use of three ALU circuits, unless the ALU circuits are optimized to perform this function.
- the load signal is determined by the output of one ALU circuit and the dump signal would be determined by the input ALU running at a different frequency. If the FIFO is full, one byte is erased and the next byte loaded. If the FIFO is empty, then the last byte is kept for the next read cycle. This is, of course, only one of many ways to perform this function.
- Another possible method is to design the ALU circuits with hand shaking such that the waiting module will not perform any function on the next clock cycle if the adjacent module is not ready to send or receive the data.
- MIMD multiple instruction multiple data or single instruction multiple data
- SIMD multiple instruction multiple data or single instruction multiple data
- the MIMD and SIMD machines do not use interconnect to perform operations such as multiplication and division, and instead utilize the processor engines to perform these functions in the traditional manner. Nor do they utilize the concept of varying the processor clock frequency to vary the calculation result, as is employed in the present invention. Nor does any of this prior work disclose or suggest the idea of programming the interconnect to represent an analog function to run in real time. Also the processors in these arrays are very complex and are therefore stuck with subject to the undesirable Von Neuman bottleneck, which is an undesirable characteristic thereof discussed above.
- the architecture of the present invention by its very nature requires each adder/shifter to perform only the one single function so that there is no data bottleneck. This provides constitutes a significant advantage over the prior art.
- Another advantage of modeling an analog circuit with an array of adders and shifters with programmable interconnect is that general integer arithmetic can be easily performed by combining adder/shifters. Hence the end user can design his device to multiply or divide a value by any integer when necessary. Since analog circuits typically move a signal along a circuit path with few feedback terms the additional time required for the integer arithmetic may not slow down the circuit as this architecture will basically pipeline the calculation so long as the calculation is not in a high speed feedback term.
- the architecture of the present invention could be implemented in an FPGA but the modules in these devices are small and designed for logic functions, typically one bit wide. Hence many modules would have to be used to make a 10 bit adder and the interconnect architectures in FPGA devices do not provide a sufficient number of lines to efficiently implement the shift function in the interconnect. Hence the circuit cost per analog function will be high and the speed will be much slower. Additionally, the modules in an FPGA are not designed to accept signals arriving asynchronously with the clock signal.
- Circuits that utilize feedback that is running at the signal frequency represent the limiting frequency of the performance of this invention. This is caused by a phase shift between the signal and the reaction to that signal which represents at best one clock delay. For these applications the circuit will be more stable if the modules are clocked in series rather than in parallel. This of course causes the maximum operating frequency of the circuit to be limited (divided) by a factor of the number of series clock pulse pulses used. Such a clocking scheme is useful for such applications for the Z transform for the specific circuit to be solved and applied to the module array as opposed to the just placing the circuit elements one to each module.
- FIGS. 11 a 11 A and 11 b 11 B Two examples of a simple series RLC tuned circuit implemented using the architecture of the present invention are shown in FIGS. 11 a 11 A and 11 b 11 B.
- FIG. 11 a 11 A the straightforward placement requires four ALU modules 130 , 132 , 134 , and 136 , driven by four sequential clocks CLK 1 , CLK 2 , CLK 3 , and CLK 4 .
- the circuit is envisioned as an input node impressed with a voltage V in in series with an inductance L in series with a resistance R in series with a capacitance C to ground.
- ALU module 130 driven by CLK 1 , computes V in ⁇ V 2prev , where V 2prev is the voltage at the node joining the inductance L and resistance R at the last clock cycle.
- ALU module 132 driven by CLK 2 , computes i prev + ⁇ i, where i prev is the current through the RLC circuit at the previous clock cycle and ⁇ i is the change in current to the current clock cycle. The current is obtained by dividing the output of ALU module 130 by L (as noted in FIG. 11 a 11 A). As taught herein, this may be done by the bit shifting technique disclosed with reference to FIG. 3 and the accompanying disclosure.
- ALU module 134 driven by CLK 3 , computes V 1 prev +i/C, where V 1 prev V 1prev +iC, where V 1prev is the voltage at the node connecting the resistance R to the capacitance C at the previous clock cycle and i/C is simply the current i (output of ALU module 132 divided by the capacitance C (: as noted in FIG. 11 a 11 A) by the bit shifting technique.
- ALU module 136 driven by CLK 4 , computes V 1 +iR V 1 +iR , where V 1 V 1 is the voltage at the node connecting the resistance R to the capacitance C at the current clock cycle and iR is simply the current i (output of ALU module 132 multiplied by the resistance R (as noted in FIG. 11 a 11 A) by the bit shifting technique.
- FIG. 11 b 11 B judicious placement of the Z transform reduces the number of clocks to two and increases the number of ALU modules to five.
- the implementation of FIG. 11 b 11 B doubles the maximum frequency. In this sense the present invention can be imagined as a parallel programmable Z transform.
- ALU module 148 driven by CLK 1 , computes V c , the voltage across the capacitance in the present cycle, as V cprev , the voltage across the capacitance C in the previous cycle, minus the quantity I prev /C.
- IR at one input to ALU module 142 may be obtained by the bit shifting techniques taught herein.
- I prev /C Of of ALU module 148 and I prev /LC at the input to ALU module 144 may be similarly obtained. While this bit shifting multiply and divide technique does allow use of a minimal number of ALU modules, those of ordinary skill in the art will recognize that the values of the multiplicands and divisors are limited to integers which are powers of 2, i.e., 2 . . . 4 . . . 8 . . . 16 2, 4, 8, 16, etc. Such skilled persons will recognize that divider and multiplier circuits may be configured from multiple ALU modules to provide more flexibility of component value choices at the expense of greater circuit complexity and ALU utilization.
- a double balanced mixer configured using the architecture of the present invention requires only one module to perform the function IVC 1 +V 2 I/ 2 where ABS ( X ) is the absolute value of X .
- the module is programmed to add the two numbers and if the most significant bit is negative (signed integer) then perform the two's complement that the module would normally due for a subtract.
- the divide by two is done on the output to the interconnect.
- three coupling transformers, two diodes and an amplifier are modeled by one module.
- Variations in gain for circuits such as AGC circuits can be implemented as powers of two by designing the module interconnect with transistors that can be switched in the circuit, as opposed to hard wired interconnect with antifuses. Another method of varying gain would be to provide a resistor divider programmed into the modules wherein the resistor value is set in SRAM memory in the module that can be changed on the fly.
- Sine wave oscillators are made with this architecture with only two clocks, one representing the L and one the C. Since these devices are mathematical there is no series resistance and therefore no damping of the oscillation. Hence the oscillator, once started, runs forever. By setting its initial conditions, the phase and amplitude are determined for every cycle until reset. Phase looked loops are therefore simple to implement. An excellent application would be synchronizing a 3.58 MHz oscillator to the color burst signal of a NTSC (TV) signal for decoding the color information. The clock frequency will change the oscillator frequency and the amplitude can be loaded at any time to synchronize with the input signal.
- NTSC NTSC
- Another feature of this architecture is that once the signal is digitized a more complex system can be built by merely adding more chips. These would be designed such that all the digital outputs for a signal are adjacent and would match up to the inputs of another chip, allowing communicating pins from chips to be placed side by side. Lead lengths and capacitance loading are therefore minimized, allowing communication of the signal from one chip to the next at the maximum possible frequency.
- the signal need not be converted back to analog until necessary to return the signal to the real world (i.e. speaker or video monitor). Of course if the information goes to a computer then the signal need never be converted back to analog.
- the modules may be designed with gated inputs to control the time a signal is loaded as is the case in synchronizing a signal or to steer the input as is the case with multiplexers.
- this architecture could integrate integer divide and multiply in the modules to perform the calculations thereby eliminating the requirement of using component values of a power of two. Clock frequencies would not therefore need to be fractionally different. This of course would lower the speed and density of the chip but it will still be considerably faster the than conventional DSP chips as there still would be no Von Neuman bottleneck.
- Some chips could be specialized by designing more specialized modules, optimized for special applications.
- a module could be optimized for the series RLC circuit example disclosed herein and could speed up the maximum chip operating frequency by about a factor of two.
Abstract
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US7024653B1 (en) * | 2000-10-30 | 2006-04-04 | Cypress Semiconductor Corporation | Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD) |
US6970509B2 (en) | 2001-07-31 | 2005-11-29 | Wis Technologies, Inc. | Cell array and method of multiresolution motion estimation and compensation |
US7184101B2 (en) | 2001-07-31 | 2007-02-27 | Micronas Usa, Inc. | Address generation for video processing |
US6996702B2 (en) * | 2001-07-31 | 2006-02-07 | Wis Technologies, Inc. | Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention |
US20050207663A1 (en) * | 2001-07-31 | 2005-09-22 | Weimin Zeng | Searching method and system for best matching motion vector |
US20050206784A1 (en) * | 2001-07-31 | 2005-09-22 | Sha Li | Video input processor in multi-format video compression system |
US20050213661A1 (en) * | 2001-07-31 | 2005-09-29 | Shuhua Xiang | Cell array and method of multiresolution motion estimation and compensation |
US20050216608A1 (en) * | 2001-07-31 | 2005-09-29 | Xu Wang | Multiple channel data bus control for video processing |
US20050223410A1 (en) * | 2001-07-31 | 2005-10-06 | Sha Li | Video processing control and scheduling |
US6981073B2 (en) | 2001-07-31 | 2005-12-27 | Wis Technologies, Inc. | Multiple channel data bus control for video processing |
US20030025839A1 (en) * | 2001-07-31 | 2003-02-06 | Shuhua Xiang | Address generation for video processing |
US7219173B2 (en) | 2001-07-31 | 2007-05-15 | Micronas Usa, Inc. | System for video processing control and scheduling wherein commands are unaffected by signal interrupts and schedule commands are transmitted at precise time |
US7142251B2 (en) | 2001-07-31 | 2006-11-28 | Micronas Usa, Inc. | Video input processor in multi-format video compression system |
US20050228970A1 (en) * | 2001-07-31 | 2005-10-13 | Shuhua Xiang | Processing unit with cross-coupled alus/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention |
US7035332B2 (en) | 2001-07-31 | 2006-04-25 | Wis Technologies, Inc. | DCT/IDCT with minimum multiplication |
US7085320B2 (en) | 2001-07-31 | 2006-08-01 | Wis Technologies, Inc. | Multiple format video compression |
US20040036500A1 (en) * | 2002-08-08 | 2004-02-26 | Bratt Adrian Harvey | Semiconductor devices |
US20040242261A1 (en) * | 2003-05-29 | 2004-12-02 | General Dynamics Decision Systems, Inc. | Software-defined radio |
US20050094677A1 (en) * | 2003-10-30 | 2005-05-05 | Lsi Logic Corporation | Optimized interleaver and/or deinterleaver design |
US7502390B2 (en) * | 2003-10-30 | 2009-03-10 | Lsi Corporation | Optimized interleaver and/or deinterleaver design |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US20120117357A1 (en) * | 2010-11-08 | 2012-05-10 | Electronics And Telecommunications Research Institute | Energy tile processor |
Also Published As
Publication number | Publication date |
---|---|
JPH0786921A (en) | 1995-03-31 |
US5457644A (en) | 1995-10-10 |
EP0639816A2 (en) | 1995-02-22 |
EP0639816A3 (en) | 1995-11-29 |
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