USRE38487E1 - Synchronous-rectified DC to DC converter with improved current sensing - Google Patents
Synchronous-rectified DC to DC converter with improved current sensing Download PDFInfo
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- USRE38487E1 USRE38487E1 US10/044,506 US4450602A USRE38487E US RE38487 E1 USRE38487 E1 US RE38487E1 US 4450602 A US4450602 A US 4450602A US RE38487 E USRE38487 E US RE38487E
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- a synchronous buck DC to DC converter typically employs a pair of switches arranged to connect one end of an inductor to either an input supply voltage or to ground. The second end of the inductor is attached to a load. It is well known to use field effect transistors (FET's) as these switches. Load current flows from the supply through the upper FET and the inductor while that FET is on, and from ground through the lower FET and the inductor while that FET is on.
- FET's field effect transistors
- the load current can be sensed through determining the DC resistance of the inductor and sensing the voltage drop across that DC resistance, or by sensing the voltage drop across an added series sense resistor.
- the load current can also be detected by sensing the voltage drop caused by the load current flowing through the upper FET switch.
- Sensing the load current by using the DC resistance of the inductor requires adding an R-C filter across the inductor to remove the AC component of the current. Thus, additional components are required and extra cost incurred. Adding a series sense resistor also requires an extra component, increases cost, and reduces system efficiency. Furthermore, sensing the voltage drop across the drain-to-source resistance of the upper FET when it is conducting has often proven to be impractical, since the “on” time of that switch is typically very short.
- the present invention provides a power supply with improved current sensing.
- the invention comprises, in one form thereof, a DC to DC buck pulse width modulator converter circuit having an input, a high side output and a low side output.
- a high side switch is electrically connected between a common output node and a voltage supply, and controls a flow of current therethrough dependent upon the high side output.
- a low side switch is electrically connected between the common output node and ground, and controls a flow of current therethrough dependent upon the low side output.
- a virtual ground amplifier includes a second input electrically connected to ground.
- a current feedback resistor is electrically connected intermediate the common output node and a first input of the virtual ground amplifier.
- a variable impedance component is electrically connected to an output of the virtual ground amplifier and to the first input of the virtual ground amplifier.
- the impedance of the variable impedance component is varied dependent upon the output of the virtual ground amplifier.
- a sample and hold circuit is electrically connected intermediate the input of the pulse width modulator converter circuit and the variable impedance component. The sample and hold circuit sources a virtual ground current through the variable impedance component, and samples the virtual ground current.
- An advantage of the DC/DC converter or the present invention is that it provides an improved method and apparatus to measure the voltage drop across the drain-to-source resistance of a FET having a very brief “on” time.
- Another advantage of the DC/DC converter of the present invention is that the amount of droop in the output voltage in response to a change in load current is easily manipulated and scaled by selecting an appropriate value for the voltage feedback resistor.
- Yet another advantage of the DC/DC converter of the present invention is that the sensitivity or magnitude of the current limiting or trip is easily manipulated or scaled by selecting an appropriate value for the voltage feedback resistor.
- a still further advantage of the DC/DC converter of the present invention is that a broad range of load current and component values is accommodated by selecting an appropriate value for the current feedback resistor.
- FIG. 1 is a high-level schematic and functional diagram of one embodiment of the DC/DC converter of the present invention
- FIG. 2 is a detailed schematic and functional diagram of the DC/DC converter of FIG. 1;
- FIGS. 3a and 3b are timing diagrams illustrating the operation of the DC/DC converter of FIG. 2;
- FIG. 4 is a diagram of a node voltage versus load current of the DC/DC converter of FIG. 2;
- FIG. 5 is a schematic of a negative current source for use with the DC/DC converter of FIG. 2;
- FIG. 6 is a detailed schematic of a second embodiment of a DC/DC converter of the present invention.
- DC/DC converter 10 includes low side field effect transistor (FET) 12 and high side FET 14 .
- the drain of low side FET 12 is electrically connected to the source of high side FET 14 at common output node 16 .
- the drain of high side FET 14 is connected to power supply 18 .
- the source of low side FET 12 is electrically connected to ground.
- Each gate terminal of low side FET 12 and high side FET 14 is electrically connected to a respective output (not referenced) of buck converter circuit 20 .
- Inductor 24 and current feedback resistor 26 are each electrically connected to common output node 16 , and thus to the drain of FET 12 and source of FET 14 .
- inductor 24 is electrically connected between common output node 16 and load reservoir capacitor 28
- current feedback resistor 26 is electrically interconnected between common output node 16 and virtual ground circuit node 30
- a load 32 schematically represented as a resistor, is electrically connected in parallel with load reservoir capacitor 28 .
- Virtual ground amplifier 34 has its inverting input 34 a electrically connected to virtual ground circuit node 30 and its non-inverting input 34 b connected to ground. Output 34 c of virtual ground amplifier 34 is electrically connected to and drives the gate of FET 36 .
- the source of FET 36 is electrically connected to virtual ground circuit node 30 .
- the drain of FET 36 is electrically connected to sample and hold circuit 38 .
- virtual ground amplifier 34 and FET 36 are configured to continuously drive virtual ground circuit node 30 toward ground potential. With virtual ground circuit node 30 being continuously driven towards ground potential, the end of current feedback resistor 26 that is connected to circuit node 30 will be at ground potential and the end connected to common output node 16 will have a negative voltage.
- This negative voltage at the end of current feedback resistor 26 that is connected to common output node 16 will be equal to the product of output current I OUT and the on-state resistance that exists between the drain and source (RDS ON ) of low side FET 12 .
- Current I SENSE flows through current feedback resistor 26 and has a magnitude determined by the ratio of RDS ON of low side FET 12 to the value of current feedback resistor 26 .
- I SENSE is the product of output current I OUT and the ratio of RDS ON of low side FET 12 to current feedback resistor 26 , and as such is representative of output current I OUT .
- Load current I L is the current flowing through inductor 24 and is substantially equal to output current I OUT minus I SENSE .
- I SENSE is substantially smaller than output current I OUT . Therefore, output current I OUT and load current I L will be of substantially similar magnitudes and thus I SENSE will also be representative of load current I L .
- the value of current feedback resistor 26 is selected to provide a convenient value of current flow for the values of load current I L and/or the value of RDS ON of low side FET 12 .
- the sensitivity or magnitude of, for example, the voltage droop, current limiting or trip, and current balancing incorporated into DC/DC converter 10 is scaled by selecting the value of current feedback resistor 26 relative to the value of RDS ON of low side FET 12 .
- the voltage drop across RDS ON of low side FET 12 which is usually negative, is accommodated in DC/DC converter 10 without the need for a negative voltage supply.
- a system control circuit 40 is electrically connected to sample and hold circuit 38 .
- the drain of FET 36 connects to sample and hold circuit 38 .
- the current supplied by the source of FET 36 flows from sample and hold circuit 38 into the drain of FET 36 , out the source of FET 36 , and into virtual ground circuit node 30 .
- I SENSE Also flowing into virtual ground circuit node 30 , from the opposite direction, is I SENSE which, as stated above, is representative of load current I L .
- virtual ground amplifier 34 via output 34 c, adjusts the current flowing through FET 36 and into virtual ground circuit node 30 to be substantially equal to I L SENSE .
- I SENSE is representative of the load current I L
- the current flowing through FET 36 and into virtual ground circuit node 30 , as controlled by virtual ground amplifier 34 and FET 36 is also representative of load current I L .
- System control circuit 40 periodically issues control signal 40 a to sample and hold circuit 38 .
- Control signal 40 a is issued when FET 36 is in the on or conducting condition.
- sample and hold circuit 38 samples the current flowing through FET 36 when FET 36 is in the on condition and holds the sampled value.
- the sampled value acquired by sample and hold circuit 38 is also representative of load current I L .
- Sample and hold circuit 38 issues sample signal 38 a which is representative of the sampled value of current flowing through FET 36 .
- DC/DC converter 10 monitors the voltage V OUT across load 32 through voltage feedback resistor 44 .
- Voltage feedback resistor 44 is connected at one end to load 32 and at the other end to inverting input 46 a of error amplifier 46 .
- V FB is the voltage across voltage feedback resistor 44 .
- the non-inverting input 46 b of error amplifier 46 is electrically connected to reference voltage supply 48 , which provides a predetermined voltage that is substantially equal to the desired output voltage of DC/DC converter 10 .
- Error amplifier 46 regulates the voltage at inverting input 46 a to be substantially equal to the voltage from reference voltage supply 48 .
- error amplifier 46 acts to regulate the sum of V OUT and V FB to be substantially equal to the voltage from reference voltage supply 48 .
- Output 46 c of error amplifier 46 is electrically connected to compensation circuit node 50 .
- a feedback path between output 46 c and inverting input 46 a of error amplifier 46 includes compensation resistor 52 and compensation capacitor 54 . More particularly, connected to compensation circuit node 50 is one end of compensation capacitor 54 which, in turn, is connected at its other end to compensation resistor 52 . Compensation resistor 52 , at the end thereof opposite to compensation capacitor 54 , is connected to summing node 56 . Compensation resistor 52 and capacitor 54 in the voltage feedback path provide system stability and control system response.
- Sample signal 38 a which is issued by sample and hold circuit 38 and is representative of load current I L , is also connected to the inverting input of error amplifier 46 . There is no other path for direct current at inverting input 46 a of error amplifier 46 except through voltage feedback resistor 44 . Thus, the voltage across voltage feedback resistor 44 , i.e., V FB , is modified by sampling signal 38 a. As stated above, error amplifier 46 regulates the voltage at its inverting input 46 a, which is equal to the sum of V OUT and V FB , to be substantially equal to the reference voltage supply 48 .
- V FB increases proportionally and error amplifier 46 reduces V OUT to maintain the voltage at inverting input 46 a to be equal to reference voltage supply 48 .
- sampling signal 38 a is representative of load current I L
- V OUT is in effect modulated in an inversely proportional manner relative to load current I L .
- V OUT is varied or droops dependent at least in part upon load current I L .
- Inverting input 58 a of comparator 58 is electrically connected to sawtooth generator 60 , and receives therefrom a sawtooth waveform having predetermined characteristics.
- Output 58 c of comparator 58 is electrically connected to set-reset (SR) latch 62 .
- Output 62 a of SR latch 62 is electrically connected to and buffered by driver 64 which, in turn, drives low side FET 12 and high side FET 14 .
- DC/DC converter 10 is configured, for example, such that a high-level signal at output 62 a of SR latch 62 turns low side FET 12 off and turns on high side FET 14 .
- Sawtooth generator 60 receives sync pulse 66 from system control circuit 40 .
- SR latch 62 also receives sync pulse 66 .
- Error amplifier 46 produces at output 46 c a signal that is representative of the actual output voltage V OUT relative to, such as, for example, subtracted from or added to, the voltage of reference voltage supply 48 , which represents the desired output voltage of DC/DC converter 10 .
- output 46 c of error amplifier 46 produces a signal that is more negative, or increases in a negative direction, as V OUT increases above the voltage of reference voltage supply 48 .
- error amplifier 46 produces at output 46 c a signal having a decreasingly negative magnitude (i.e., a more positive magnitude) as V OUT decreases below the voltage of reference voltage supply 48 .
- Output 46 c of error amplifier 46 is electrically connected to the non-inverting input of comparator 58 .
- Comparator 58 compares the sawtooth waveform electrically connected to its inverting input 58 a with output 46 c of error amplifier 46 which is electrically connected to its noninverting input 58 b.
- Output 58 c of comparator 58 is active, such as, for example, high during the time that the sawtooth waveform generated by sawtooth generator 60 is less positive than output 46 c of error amplifier 46 .
- output 46 c of error amplifier 46 is relatively high, thereby placing a relatively high signal at noninverting input 58 b of comparator 58 . At least a substantial portion of the period of the sawtooth waveform will be less positive than the relatively high-level signal present at noninverting input 58 b.
- Output 58 c of comparator 58 is active, such as, for example, high, during that substantial portion of the period for which the sawtooth waveform has a value that is less positive than the relatively high signal present at noninverting input 58 b.
- the pulse width of output 58 c will be relatively wide, or alternatively the active period of output 58 c will be relatively long in duration, when V OUT is less than the voltage of reference voltage supply 48 .
- output 46 c of error amplifier 46 is relatively low when V OUT is greater than the voltage of reference voltage supply 48 .
- This condition places a relatively low-level signal at noninverting input 58 a of comparator 58 .
- a relatively small portion of the period of the sawtooth waveform will be less positive than the relatively low-level signal present at noninverting input 58 b.
- Output 58 c of comparator 58 will be active during only that relatively small portion, if any, of the period of the sawtooth waveform (e.g., the lowest points or bottom peaks) which is less positive than the relatively low signal at noninverting input 58 b.
- the pulse width of output 58 c will be relatively narrow, or alternatively the active period of output 58 c will be relatively short in duration, when V OUT is greater than the voltage of reference voltage supply 48 .
- output 62 a of SR latch 62 When output 58 c is active, output 62 a of SR latch 62 is set, such as, for example, high. Conversely, when output 58 c is not active, output 62 a of SR latch 62 is reset, such as, for example, low. Thus, when the sawtooth waveform is more positive than the voltage level of reference voltage supply 48 , output 62 a of SR latch 62 is reset, i.e., low. Output 62 a of SR latch 62 is set, i.e., high, when the sawtooth waveform drops below the predetermined voltage. Output 62 a of SR latch 62 is electrically connected to and buffered by driver 64 which, in turn, drives low side FET 12 and high side FET 14 .
- DC/DC converter 10 is configured such that, for example, a high or set condition on output 62 a of SR latch 62 results in driver 64 turning off low side FET 12 and turning on high side FET 14
- Overcurrent detection circuit 70 compares the sample signal 38 a to a reference current (not shown) and issues overcurrent signal 70 a to system control circuit 40 when sample signal 38 a exceeds the reference current.
- System control 40 responds to overcurrent signal 70 a by shutting down DC/DC converter 10 .
- System control 40 is configured, for example, to restart the operation of DC/DC converter 10 after a predetermined amount of time.
- Negative current source 72 is electrically connected intermediate system control 40 and virtual ground circuit node 30 .
- Load current I L becomes negative under certain operating conditions, such as, for example, when load current I L has a low average value and the sawtooth waveform created due to the switching of voltage across inductor 24 dips to a negative value.
- the voltage at the drain of low side FET 12 is positive.
- the positive voltage on the drain of low side FET 12 results in the sourcing of current through resistor 26 and into virtual ground circuit node 30 , thereby driving virtual ground circuit node 30 to a positive potential.
- Negative current source 72 sources I PULL DOWN into virtual ground circuit node 30 in response to signal 40 N , and thereby maintains virtual ground node 30 at ground potential under the conditions when I L is negative.
- virtual ground amplifier 46 , variable impedance component 36 and sample and hold circuit 38 are not required to operate in a bi-directional manner (i.e., they source current in one direction only) and the need to include a negative voltage supply in DC/DC converter 10 is eliminated.
- a negative current source 72 includes switches 80 , 82 and 84 .
- switches 80 , 82 and 84 are, for example, MOS transistors.
- Current source 86 is a pull down current source, such as, for example, an NMOS mirror, and is electrically connected intermediate ground and node 90 .
- Switch 80 is electrically connected intermediate node 90 and voltage supply 88 , and selectively connects node 90 to voltage supply 88 .
- Capacitor 92 is electrically interconnected between node 90 and node 94 .
- Each of switch 82 and 84 have a first side electrically connected to node 94 .
- switch 82 is electrically connected to ground, while the other side of switch 84 is electrically connected to virtual ground circuit node 30 .
- Switches 80 and 82 are closed and switch 84 is open when the reverse current sourced by current source 86 is not required to maintain virtual ground circuit node 30 at ground potential, such as, for example, when low side FET 12 is off.
- the supply voltage of voltage supply 88 is thus stored across capacitor 92 , with node 90 having a positive potential and node 94 having a negative potential.
- switches 80 and 82 are each opened and switch 84 is closed.
- I PULL DOWN flows into virtual ground node 30 in the same direction as normal forward current induced by the voltage drop on low side FET 12 .
- the addition of current I PULL DOWN maintains virtual ground circuit node 30 at ground potential, and is optionally subtracted out later so as not to affect subsequent circuit operation, such as, for example, the current limit trip point.
- the sequence of operation of DC/DC converter 10 is as follows.
- Sawtooth generator 60 receives sync pulse 66 from system control circuit 40 .
- SR latch 62 also receives sync pulse 66 .
- Sync pulse resets both the sawtooth waveform and output 62 a of SR latch 62 to low levels.
- SR latch 62 is configured to reset output 62 a based upon sync pulse 66 , regardless of the condition or state of the output of comparator 58 .
- output 62 a of SR latch 62 will be low during a high level of sync pulse 66 .
- sync pulse 66 resets the sawtooth waveform generated by sawtooth generator 60 to a low level, and resets output 62 a of SR latch 62 .
- DC/DC converter 10 is configured such that, for example, when output 62 a of SR latch 62 is low, high side FET 14 is off and low side FET 12 is on. Thus, the resetting of output 62 a of SR latch 62 by sync pulse 66 turns on low side FET 12 . During this time period, i.e., when low side FET 12 is on, RDS ON of low side FET 12 is measured.
- the sawtooth waveform begins to slope downward (i.e. has a negative slope).
- FIG. 3a the condition of DC/DC converter 10 having an output voltage V OUT that is lower than the desired or target level is illustrated.
- the voltage across load 32 is lower than desired.
- This condition results in output 46 c of error amplifier 46 having a high level relative to the sawtooth waveform.
- the leading, or positively sloped, edge of the sawtooth waveform crosses above the output level of output 46 c of error amplifier 46 , thereby sending output 58 c of comparator 58 low.
- This particular transition in output 58 c does not affect output 62 a of SR latch 62 since sync pulse 66 is still active, and thus output 62 a remains reset or low.
- the trailing, or negatively sloped, edge of the sawtooth waveform crosses below the output level of output 46 c of error amplifier 46 , thereby sending output 58 c of comparator 58 high.
- This transition in output 58 c to a high level sets output 62 a of SR latch 62 high thereby turning high side FET 14 on and turning off low side FET 12 .
- the high level of output 46 c relative to the sawtooth waveform results in the sawtooth waveform dropping below the level of output 46 c (at point 310 a) relatively early in the period of the sawtooth waveform.
- points 300 a and 310 a are relatively close in time, and, therefore, the period of time during which low side FET 12 is off is correspondingly brief. Conversely, the period of time during which high side FET 14 is on and sourcing current is relatively long. Thus, high side FET 14 is on for a relatively long period of time and sources a greater amount of current to load 32 when V OUT is less than the desired output voltage.
- the trailing, or negatively sloped, edge of the sawtooth waveform crosses below the output level of output 46 c of error amplifier 46 , thereby sending output 58 c of comparator 58 high.
- This transition in output 58 c to a high level sets output 62 a of SR latch 62 high thereby turning high side FET 14 on and turning off low side FET 12 .
- the low level of output 46 c relative to the sawtooth waveform results in the sawtooth waveform dropping below the level of output 46 c (at point 310 b) relatively late in the period of the sawtooth waveform.
- points 300 a and 310 a are separated by a substantially greater amount of time relative to the situation illustrated in FIG.
- the period of time during which low side FET 12 is on is of a correspondingly longer duration.
- the period of time during which high side FET 14 is on and sourcing current is relatively brief. Therefore high side FET 14 sources a lesser amount of current to load 32 when V OUT is greater than the desired output voltage.
- output 62 a of SR latch 62 goes low based upon sync pulse 66 rather than dependent upon the relative value of the voltage across load 32 .
- Output 62 a of SR latch 62 remains low at least during the duration of sync pulse 66 .
- load current I L flows from ground through the source to the drain of low side FET 12 when low side FET 12 is in the on condition.
- This direction of current flow through low side FET 12 develops a negative voltage on the drain of low side FET 12 .
- the magnitude of this negative voltage is the product of I L and the RDS ON of low side FET 12 .
- the source of low side FET 12 is electrically connected to ground.
- low side FET 12 can be alternately configured, such as, for example, having its source tied through a resistor to ground, and electrically connecting sensing resistor 26 to the source of low side FET 12 .
- the net effect is the same, and the virtual ground amplifier continues to drive virtual ground node 30 to virtual ground.
- current from Sample and Hold circuit 38 is still representative of load current I L except the load-current-induced voltage drop across the added sense resistor is measured rather than the voltage drop across RDS ON of low side FET 12 .
- This alternative embodiment is best shown in FIG. 6 .
- reference voltage supply 48 is described as a fixed voltage supply. However, it is to be understood that reference voltage supply 48 can be alternatively configured, such as, for example, as a bandgap or other fixed voltage source, or may be configured as a Digital to Analog converter or other variable voltage source.
- FET 36 is configured as an FET. However, it is to be understood that FET 36 can be alternately configured, such as, for example, an NPN transistor, with Base substituted for Gate, Emitter for Source, and Collector of Drain.
- virtual ground amplifier 34 is configured for continuous operation. However, it is to be understood that virtual ground amplifier 34 can be alternately configured, such as, for example, an auto-zeroed amplifier or other non-continuously operating amplifier, as it is needed only when low side FET 12 is in the on state.
- DC/DC converter 10 is configured such that a high-level signal at output 62 a of SR latch 62 turns low side FET 12 off and turns on high side FET 14 .
- DC/DC converter 10 can be alternately configured such that the operational polarity of FET 12 and FET 14 is reversed.
- system control circuit 40 is configured to restart the operation of DC/DC converter 10 after a predetermined amount of time following the detection of an overcurrent condition.
- system control circuit 40 may be alternately configured, such as, for example, to issue a visual or audible warning signal or to completely shut down DC/DC converter 10 .
- DC/DC converter 10 is configured with inductor 24 , load capacitor 28 and load 32 connected to node 16 .
- DC/DC converter 10 can be alternately configured, such as, for example, without inductor 24 , load capacitor 28 and load 32 such that a user, designer, or manufacturer can choose and customize circuitry attached to node 16 of DC/DC converter 10 .
Abstract
Description
Claims (42)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/044,506 USRE38487E1 (en) | 1999-09-01 | 2002-01-11 | Synchronous-rectified DC to DC converter with improved current sensing |
US11/337,925 USRE42532E1 (en) | 1999-09-01 | 2006-01-23 | Synchronous-rectified DC to DC converter with improved current sensing |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US15182699P | 1999-09-01 | 1999-09-01 | |
US09/633,316 US6246220B1 (en) | 1999-09-01 | 2000-08-07 | Synchronous-rectified DC to DC converter with improved current sensing |
US10/044,506 USRE38487E1 (en) | 1999-09-01 | 2002-01-11 | Synchronous-rectified DC to DC converter with improved current sensing |
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US09/633,316 Reissue US6246220B1 (en) | 1999-09-01 | 2000-08-07 | Synchronous-rectified DC to DC converter with improved current sensing |
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USRE38487E1 true USRE38487E1 (en) | 2004-04-06 |
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US09/633,316 Ceased US6246220B1 (en) | 1999-09-01 | 2000-08-07 | Synchronous-rectified DC to DC converter with improved current sensing |
US10/044,506 Expired - Lifetime USRE38487E1 (en) | 1999-09-01 | 2002-01-11 | Synchronous-rectified DC to DC converter with improved current sensing |
US10/282,753 Expired - Lifetime USRE38940E1 (en) | 1999-09-01 | 2002-10-29 | Synchronous-rectified DC to DC converter with improved current sensing |
US11/337,925 Expired - Lifetime USRE42532E1 (en) | 1999-09-01 | 2006-01-23 | Synchronous-rectified DC to DC converter with improved current sensing |
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US09/633,316 Ceased US6246220B1 (en) | 1999-09-01 | 2000-08-07 | Synchronous-rectified DC to DC converter with improved current sensing |
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US10/282,753 Expired - Lifetime USRE38940E1 (en) | 1999-09-01 | 2002-10-29 | Synchronous-rectified DC to DC converter with improved current sensing |
US11/337,925 Expired - Lifetime USRE42532E1 (en) | 1999-09-01 | 2006-01-23 | Synchronous-rectified DC to DC converter with improved current sensing |
Country Status (4)
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US (4) | US6246220B1 (en) |
KR (1) | KR100573520B1 (en) |
CN (1) | CN1201470C (en) |
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Also Published As
Publication number | Publication date |
---|---|
USRE38940E1 (en) | 2006-01-24 |
KR100573520B1 (en) | 2006-04-26 |
USRE42532E1 (en) | 2011-07-12 |
TW517441B (en) | 2003-01-11 |
US6246220B1 (en) | 2001-06-12 |
CN1286520A (en) | 2001-03-07 |
KR20010030203A (en) | 2001-04-16 |
CN1201470C (en) | 2005-05-11 |
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