USRE38956E1 - Data compression circuit and method for testing memory devices - Google Patents

Data compression circuit and method for testing memory devices Download PDF

Info

Publication number
USRE38956E1
USRE38956E1 US10/139,131 US13913102A USRE38956E US RE38956 E1 USRE38956 E1 US RE38956E1 US 13913102 A US13913102 A US 13913102A US RE38956 E USRE38956 E US RE38956E
Authority
US
United States
Prior art keywords
data
coupled
error detection
detection circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/139,131
Inventor
Ray Beffa
Leland R. Nevill
Neil L. Hansen
Eugene H. Cloud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Bank NA
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US10/139,131 priority Critical patent/USRE38956E1/en
Application granted granted Critical
Publication of USRE38956E1 publication Critical patent/USRE38956E1/en
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT reassignment MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: MICRON TECHNOLOGY, INC.
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: MICRON TECHNOLOGY, INC.
Anticipated expiration legal-status Critical
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques

Definitions

  • the present invention relates generally to the testing of semiconductor memories, and more specifically to a method and circuit for performing on-chip data compression to reduce the time for testing memory cells in a semiconductor memory.
  • SDRAMs synchronous dynamic random access memories
  • a typical SDRAM includes a number of arrays, each array including a number of memory cells arranged in rows and columns. During testing of the SDRAM, each memory cell must be tested to ensure it is operating properly.
  • data having a first binary value e.g., a “1”
  • data having a second binary value e.g., a “0”
  • a memory cell is determined to be defective when the data written to the memory cell does not equal that read from the memory cell.
  • other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern 101010 . . . written to the memory cells in each row of the arrays.
  • an automated memory tester is coupled to address, data, and control buses of the SDRAM, and develops signals on these buses to perform the desired tests.
  • the tester applies data transfer commands on the control bus, addresses on the address bus, and either provides or receives data on the data bus depending on whether the data transfer command is a read or write.
  • the tester develops a clock signal which drives circuitry in the SDRAM to synchronously perform each of the steps involved in a particular data transfer operation, as understood by one skilled in the art.
  • the signals developed by the tester must satisfy particular timing parameters of the SDRAM that are established relative to particular edges of the clock signal.
  • the tester may need to develop a clock signal having a frequency of 100 megahertz or greater, and must also develop the associated address, data, and control signals at increasingly faster rates due to the shorter interval between rising edges of the clock signal.
  • the design and layout of circuitry associated with a particular application typically become more complex and, as a result, typically more expensive. This is due in part to the potential for coupling electromagnetic energy at high frequencies between circuit lines, the critical nature of the physical line lengths at high frequencies, and the potential for small delays to result in inoperability of the circuit.
  • the tester could supply a lower frequency clock signal to the SDRAM, but this would increase the time and thus the cost of testing the SDRAM.
  • test would then not be performed at the more stringent high speeds at which the SDRAM may operate during use.
  • the tester must supply very high frequency clock signals to modem SDRAMs. Testers capable of operating at these higher frequencies are typically more expensive than lower frequency testers. In fact, the cost of such testers typically increases exponentially with increases in the frequency of operation. For example, a tester operating at 50 megahertz may cost approximately $1 million while a tester operating at 100 megahertz can cost up to $5 million.
  • the tester In addition to the frequency of operation of the tester, the number of data transfer operations the tester must perform in writing data to and reading data from the memory cells affects the time and thus the cost of testing the SDRAM. As the storage capacity of SDRAM increases, the number of data transfers performed in testing every memory cell increases accordingly. For example, in a memory array having n rows and m columns of memory cells, the tester performs n ⁇ m cell accesses in writing the first binary data values to all the memory cells in the array, and thereafter performs n ⁇ m cell accesses in reading the same data. The tester must once again perform n ⁇ m access in writing data having a second binary value to each memory cell, and the same number of accesses in reading this data.
  • the tester thus performs a total of four times n ⁇ m cell accessories, each of which requires a bus cycle to perform, in testing each memory cell in the array.
  • n ⁇ m cell accessories each of which requires a bus cycle to perform, in testing each memory cell in the array.
  • 67,108,864 bus cycles are required to perform a complete test of every memory cell.
  • test circuit that reduces the time it takes a low frequency memory tester to test the memory cells in a high frequency SDRAM.
  • a test circuit detects defective memory cells in a plurality of memory cells in a memory device.
  • the test circuit includes a test mode terminal adapted to receive a test mode signal.
  • An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. The error detection circuit develops an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data.
  • a control circuit is coupled to the test mode terminal, the error detection circuit, and the memory cells.
  • the control circuit is operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.
  • FIG. 1 is a functional block diagram of a test system including a memory device having a test circuit according to one embodiment of the present invention.
  • FIG. 2 is a functional block diagram of one embodiment of the error detection circuit of FIG. 1 .
  • FIG. 3 is a schematic of one embodiment of the data compression circuits of FIG. 2 .
  • FIG. 4 is a functional block diagram of a computer system including the memory device of FIG. 1 .
  • FIG. 1 is a functional block diagram of a test system 8 comprising a memory tester 9 coupled to a memory device 10 including a test circuit 12 according to one embodiment of the present invention.
  • the memory tester 9 places the memory device 10 in a test mode during which the test circuit 12 detects the defective memory cells in the memory device 10 and provides a signal to the tester 9 indicating the presence of any such detected defective cells as will be explained in more detail below.
  • the memory device 10 includes an address decoder 20 receiving address signals on an address bus ADDR.
  • the address decoder 20 decodes the address signals and outputs a decoded address to a number of memory-cell arrays 22 - 28 .
  • the memory-cell arrays 22 - 28 each include a number of memory cells (not shown in FIG. 1 ) arranged in rows and columns, each memory cell operable to store a bit of data as known in the art.
  • a read/write circuit 30 is coupled between a data bus DATA and the arrays 22 - 28 , and transfers data to and from the data bus DATA during read and write data transfer operations, respectively.
  • a control circuit 16 controls the address decoder 20 , arrays 22 - 28 , and read/write circuit 30 responsive to a clock signal CLK received on a terminal 34 .
  • the address decoder 20 , read/write circuit 30 , and control circuit 16 are shown coupled only to the array 22 , one skilled in the art will realize that these circuits are coupled to all of the arrays 22 - 28 to perform their desired functions.
  • the test circuit 12 includes a conventional frequency multiplier circuit 32 receiving the clock signal CLK through a transfer gate 36 .
  • the frequency multiplier circuit 32 develops a test clock signal TSTCLK having a frequency greater than the frequency of the clock signal CLK.
  • the test clock signal TSTCLK is applied through a transfer gate 38 to the control circuit 16 .
  • the clock circuit 14 further includes a transfer gate 44 coupled between the clock terminal 34 and the control circuit 16 and receiving the test mode signal TM on its control input.
  • the test circuit 12 further includes an error detection circuit 18 receiving data signals D 1 -D 4 from the arrays 22 - 28 , respectively, and receiving control signals TEST, CLEAR, and ⁇ overscore (ENABLE) ⁇ from the control circuit 16 .
  • the error detection circuit 18 compares the binary values of the data signals D 1 -D 4 , and develops an error signal ERROR on a terminal 46 indicating the result of this comparison, as will be explained in more detail below.
  • the error detection circuit 18 can compare the binary values of the data signals D 1 -D 4 to each other or to predetermined binary values, as understood by one skilled in the art.
  • FIG. 2 is a more detailed schematic block diagram of one embodiment of the error detection circuit 18 of FIG. 1 .
  • the error detection circuit 18 includes three data compression circuits 100 - 104 that collectively compress the data signals D 1 -D 4 received from the arrays 22 - 28 , as will be explained in more detail below.
  • the data signals D 1 -D 4 each include a complementary signal portion designated by the overbar in FIG. 2 , with these complementary portions being omitted in FIG. 1 for the sake of brevity.
  • a detailed schematic of one embodiment of the data compression circuit 100 is shown in FIG. 3 .
  • the data compression circuits 102 and 104 are identical to the data compression circuit 100 and thus, for the sake of brevity, only the circuit 100 will be described in more detail with reference to FIG. 3 .
  • the data compression circuit 100 includes a NAND gate 200 receiving the data signals D 1 and D 2 on its inputs, and a NAND gate 202 receiving the data signals ⁇ overscore (D 1 ) ⁇ and ⁇ overscore (D 2 ) ⁇ on its inputs.
  • the output of the NAND gate 200 is applied to a gate of an NMOS drive transistor 204 and to a gate of a PMOS drive transistor 208 .
  • the transistors 204 and 208 operate in a complementary manner to develop an output signal D[ 1 - 2 ] on a node 222 .
  • a first enable transistor 220 couples the source of the transistor 208 to a supply voltage source V CC in response to the test signal TEST applied to its gate through an inverter 206 .
  • a second enable transistor 216 couples the source of the transistor 204 to ground in response to the test signal TEST.
  • the output of the NAND gate 202 is similarly coupled to a gate of an NMOS drive transistor 210 and to a gate of a PMOS drive transistor 214 .
  • the transistor 210 and 214 operate in a complementary manner to develop an output signal ⁇ overscore (D) ⁇ [ 1 - 2 ] on an output node 224 .
  • the source of the transistor 210 is coupled through a third enable transistor 218 to ground in response to the test signal TEST, and the source of the transistor 214 coupled to the supply voltage source V CC through the enable transistor 220 .
  • the data compression circuit 100 operates in an active 20 mode and an inactive mode in response to the test signal TEST.
  • the enable transistors 216 , 218 and 220 turn OFF isolating the drive transistors 204 , 208 , 210 , and 214 from the supply voltage V CC and the ground.
  • high impedances are presented, respectively, on the output nodes 222 and 224 independent of the outputs of the NAND gates 200 and 202 .
  • the enable transistors 216 and 218 turn ON coupling the sources of the output transistors 204 and 210 , respectively, to ground, and the enable transistor 220 turns ON coupling the sources of the output transistors 208 and 214 to the supply voltage source V CC .
  • the state of the output signals D[ 1 - 2 ] and ⁇ overscore (D) ⁇ [ 1 - 2 ] is determined by the binary values of the data signals D 1 , ⁇ overscore (D 1 ) ⁇ and D 2 , ⁇ overscore (D 2 ) ⁇ . For example, assume the data signals D 1 and D 2 are both high.
  • the NAND gate 200 drives its output low turning OFF the transistor 204 and turning ON the transistor 208 which drives the voltage on the output node 222 high to approximately the supply voltage V CC through the transistors 208 and 220 .
  • the data signals D 1 and D 2 are high, the data signals ⁇ overscore (D 1 ) ⁇ and ⁇ overscore (D 2 ) ⁇ are accordingly low.
  • the NAND gate 202 drives its output high, turning OFF the transistor 214 and turning ON the transistor 210 thereby driving the voltage on the output node 224 low to approximately ground through the transistors 210 and 218 .
  • the data compression circuit 100 drives the output signals D[ 1 - 2 ] and ⁇ overscore (D) ⁇ [ 1 - 2 ] high and low, respectively.
  • the data compression circuit 100 operates in a complementary manner when the data signals D 1 and D 2 are low. More specifically, when the data signals D 2 and D 2 are low, the NAND gate 200 drives its output high turning the transistors 204 and 208 ON and OFF, respectively, and thereby driving the output signal D[ 1 - 2 ] low through the transistors 204 and 216 .
  • the data signals ⁇ overscore (D 1 ) ⁇ and ⁇ overscore (D 2 ) ⁇ are high when the signals D 1 and D 2 are low causing the NAND gate 202 to drive its output low.
  • the low output from the NAND gate 202 turns the transistors 210 and 214 OFF and ON, respectively, which, in turn, drives the output signal D[ 1 - 2 ] high through the transistors 214 and 220 . If the data signals D 1 and D 2 have different binary values, both the NAND gates 220 and 202 drive their outputs high. In response to the high output from the NAND gate 200 , the output signal D[ 1 - 2 ] is driven low through the transistors 204 and 216 . In the same way, the high output from the NAND gate 202 drives the output signal ⁇ overscore (D) ⁇ [ 1 - 2 ] low through the transistors 210 and 218 .
  • the data compression circuit 100 compresses the complementary data signals D 1 , ⁇ overscore (D 1 ) ⁇ and D 2 , ⁇ overscore (D 2 ) ⁇ to the single pair of output signals D[ 1 - 2 ], ⁇ overscore (D) ⁇ [ 1 - 2 ].
  • the output signals D[ 1 - 2 ] and ⁇ overscore (D) ⁇ [ 1 - 2 ] are high and low, respectively, and when the data signals D 1 and D 2 are low the output signals D[ 1 - 2 ] and D [ 1 - 2 ] are low and high, respectively.
  • the data compression circuit 100 detects when the data signals D 1 and D 2 are unequal and drives the output signals D[ 1 - 2 ] and ⁇ overscore (D) ⁇ [ 1 - 2 ] are low. It should be noted, however, that the data compression circuit 100 is limited to detecting the failure of a single memory cell. This is true because the failure of multiple memory cells could go undetected by the circuit 100 . For example, assume the two memory cells storing data corresponding to the data signals D 1 and D 2 both fail in a way that they always store a binary 1 regardless of the data written to the cell. In this situation, the data compression circuit 100 will not detect an error because the data signals D 1 and D 2 , although erroneous, are equal.
  • the data compression circuit 102 receives the data signals D 3 , ⁇ overscore (D 3 ) ⁇ and D 4 , ⁇ overscore (D 4 ) ⁇ and the test signal TEST, and develops output signals D[ 3 - 4 ] and ⁇ overscore (D) ⁇ [ 3 - 4 ].
  • the data compression circuit 104 receives the output signals D[ 1 - 2 ], D[ 1 - 2 ] from the data compression circuit 100 and the output signals D[ 3 - 4 ] and ⁇ overscore (D) ⁇ [ 3 - 4 ] from the data compression circuit 102 and develops output signals D[ 1 - 4 ] and ⁇ overscore (D) ⁇ [ 1 - 4 ].
  • the output signals D[ 1 - 4 ] and ⁇ overscore (D) ⁇ [ 1 - 4 ] are applied to the inputs of a NOR gate 106 which drives its output high when both the signals D[ 1 - 4 ] and ⁇ overscore (D) ⁇ [ 1 - 4 ] are low.
  • the test signal TEST is applied through an inverter 108 to an enable input of the NOR gate 106 .
  • the NOR gate 106 is enabled and operates as a conventional NOR gate, and when the test signal TEST is inactive low the NOR gate 106 is disabled placing its output in a high impedance state.
  • the output of the NR gate 106 is coupled to an input of an error latch 108 that latches an error signal ERROR active high in response to the output of the NOR gate 106 going high. More specifically, the output of the NOR gate 106 is applied to a set input of an RS flip-flop 110 including a pair of cross-coupled NOR gates 112 and 114 . A clear signal CLEAR is applied to a reset input of the RS flip-flop 110 and is further applied to a gate of an NMOS transistor 116 coupled between the set input of the RS flip-flop 110 and ground. The RS flip-flop 110 develops the error signal ERROR on the output of the NOR gate 114 .
  • the RS flip-flop 110 latches the error signal ERROR active high.
  • the RS flip-flop 110 maintains the error signal ERROR active high until the clear signal CLEAR goes active high.
  • the transistor 116 turns ON driving the set input low and reset input high and the RS flip-flop 110 latches the error signal ERROR inactive low.
  • the error signal ERROR is applied through a transfer gate 118 to the terminal 46 of the memory device 10 .
  • the transfer gate 118 receives the enable signal ⁇ overscore (ENABLE) ⁇ from the control circuit 76 ( FIG. 1 ) on its control input and applies the error signal ERROR on the terminal 46 when the enable signal ⁇ overscore (ENABLE) ⁇ is active low.
  • the memory device 10 operates in two mode, a normal mode and a test mode.
  • the memory device 10 operates in the normal mode outside of the test system 9 .
  • an external circuit (not shown in FIG. 1 ), such as a microprocessor, drives the test mode signal TM inactive low and applies address, data, and control signals on the respective buses of the memory device 10 , and applies the clock signal CLK on the clock terminal 34 .
  • the transfer gates 36 and 38 turn OFF and the signal CLK is transferred through the activated transfer gate 44 to the control circuit 16 .
  • the control circuit 16 controls the address decoder 20 , arrays 22 - 28 , and read/write circuit 30 to perform data transfer operations.
  • the external circuit places address, data, and control signals on the response buses to form a command, such as an ACTIVE, READ, or WRITE command, as understood by one skilled in the art.
  • the commands is latched by the memory device 10 in response to a rising edge of the clock signal CLK.
  • the address decoder 20 decodes the latched memory address and accesses the addressed memory cells in the arrays 22 - 28 .
  • the data stored in the accessed memory cells in the arrays 22 - 28 is transferred through the read/write circuit 30 and onto the data bus DATA where it is available to be read by the external circuit.
  • the address decoder 20 In response to a WRITE command, the address decoder 20 once again decodes the latched address and accesses the addressed memory cells in the arrays 22 - 28 .
  • the read/write circuit 30 then transfers the data placed on the data bus DATA to the addressed memory cells in the arrays 22 - 28 where it is stored.
  • the memory device 10 operates in the test mode when in the test system 8 as shown in FIG. 1 .
  • the memory tester 9 applies data transfer commands to the memory device 10 in the form of address, data, and control signals on the respective buses, as well as the clock signal CLK and the test mode signal TM.
  • the memory tester 9 drives the test mode signal TM active high turning OFF the transfer gate 44 and turning ON the transfer gates 36 and 38 such that the frequency multiplier circuit 32 drives the control circuit 16 with the test clock signal TSTCLK.
  • test mode signal TM is shown as being applied on a single terminal of the memory device 10 , one skilled in the art will realize that the test mode signal TM may take a variety of forms.
  • test mode signal TM may correspond to a separate logic level signal, a “super voltage” applied to one of the pins of the memory device 10 , or a combination of control signals on the control bus such as providing a column address strobe signal ⁇ overscore (CAS) ⁇ before a row address strobe signal ⁇ overscore (RAS) ⁇ to place the memory device 10 in the test mode of operation.
  • CAS column address strobe signal
  • RAS row address strobe signal
  • a test data pattern must be written to all the memory cells in the arrays 22 - 28 .
  • Such a test data pattern may be written to the arrays 22 - 28 in a number of different ways.
  • the memory tester 9 may apply WRITE commands to the memory device 10 to write the desired test data pattern into the memory cells in the arrays 22 - 28 .
  • the memory tester 9 may write such test data to the arrays 22 - 28 either before or after the memory tester 9 places the memory device 10 in the test mode of operation.
  • the control circuit 16 may generate the test data written to the arrays 22 - 24 .
  • the test data pattern written to the memory cells in the arrays 22 - 28 may vary with some memory cells storing binary 0s and others storing binary 1s.
  • the control circuit 16 drives the signals TEST and ⁇ overscore (ENABLE) ⁇ active high and low, respectively, activating the error detection circuit 18 .
  • the control circuit 16 then pulses the clear signal CLEAR active high to ensure the error signal ERROR output by the error detection circuit 18 is initially inactive low.
  • the control circuit 16 thereafter activates a row of memory cells in each of the arrays 22 - 28 and accesses an individual memory cell in each of the activated rows.
  • the data stored in the accessed memory cells in the arrays 22 - 28 corresponds to the data signals D 1 -D 4 , respectively.
  • the data signals D 1 -D 4 are applied to the inputs of the error detection circuit 18 , which operates as previously described to determine whether the data stored in all the accessed memory cells is equal.
  • the error detection circuit 18 maintains the error signal ERROR inactive low, and when the data is unequal the error detection circuit 18 drives the error signal ERROR active high.
  • the memory tester 9 monitors the error signal ERROR on the terminal 46 to determine whether any of the accessed memory cells is defective.
  • the memory tester 9 cannot typically detect the state of the error signal ERROR after the error detection circuit 18 compares the data stored in each group of four memory cells in the arrays 22 - 28 . Instead, the memory tester 9 typically detects the error signal ERROR after a predetermined number of comparisons have been made by the error detection circuit 18 . For example, the control circuit 16 may apply the data stored in every memory cell in the activated rows in the arrays 22 - 28 to the error detection circuit 18 and thereafter detect the state of the error signal ERROR.
  • the memory tester 9 knows that at least one of the memory cells in one of the activated rows in the arrays 22 - 28 is defective.
  • the control circuit 16 pulses the clear signal CLEAR active high to ensure the error signal ERROR in reset inactive low.
  • the control circuit 16 then controls the arrays 22 - 28 and error detection circuit 18 as previously described to activate rows of memory cells in the arrays 22 - 28 and test the memory cells in each of the activated rows.
  • the memory cells in the arrays 22 - 28 are accessed such that the accessed memory cells each store the same binary data if not defective.
  • the test data pattern written to the memory cells and the sequence of activating the cells ensure the cells being accessed store the same binary data if operating properly.
  • the error detection circuit 18 could allow cells storing different data to be accessed and that data applied to the circuit 18 .
  • the data signals D 1 , ⁇ overscore (D 1 ) ⁇ could be coupled through inverters to their associated NAND gates.
  • the data compression circuit 100 indicates no error when the signals D 1 and D 2 have different binary values and detects an error when such values are equal.
  • the test circuit 12 enables the external memory tester 9 operating at a rate determined by a lower frequency clock signal CLK to test the memory device 10 much more quickly than in a conventional test system.
  • the external memory tester 9 drives the memory device 10 with the clock signal CLK and transfers data to and from the memory device 10 at a slower rate corresponding to the lower frequency of the clock signal CLK.
  • the test circuit 12 accesses the memory cells in the arrays 22 - 28 at a much faster rate determined by the higher frequency of the test clock signal TSTCLK.
  • the faster rate at which the memory cells in the arrays 22 - 28 are accessed results in a corresponding decrease in the test time of the memory device 10 including the test circuit 12 .
  • additional time savings in testing the memory device 10 is realized by the data compression performed by the error detection circuit 18 .
  • the tests circuit 12 enables the data stored in four memory cells to be simultaneously accessed and compared to determine whether any of the accessed memory cells is defective.
  • the test circuit 12 reduces the time it takes to read the test data stored in the arrays 22 - 28 to detect a defective memory cell.
  • each memory cell in each of the arrays 22 - 28 must be accessed individually and the data stored in that cell read by the memory tester 9 to determine whether the data stored in the memory cell equals the data initially written to that memory cell.
  • the time it takes to read the data stored in all of the memory cells in the arrays 22 - 28 is reduced because the error detection circuit 18 simultaneously compares the data in four accessed memory cells.
  • the test circuit 12 accesses a single memory cell in each of the arrays 22 - 28 and applies the data stored in each accessed memory cell to a respective input of the error detection circuit 18 .
  • the structure of the error detection circuit 18 and interconnection between the circuit 18 and arrays 22 - 28 may vary.
  • the number of memory-cell arrays may vary and the number of inputs to the error detection circuit 18 may vary accordingly.
  • the memory device 10 may include thirty-two memory-cell arrays each coupled to one input of the error detection circuit 18 .
  • more data signals may be compared by the error detection circuit 18 simply by cascading more data compression circuits 100 - 104 in a circuit analogous to that shown in FIG.
  • test circuit 12 may be utilized in a variety of the memory devices 10 including SDRAMs, asynchronous DRAMs, static RAMs, and packetized SDRAMs such as Synclink DRAMs (“SLDRAMs”).
  • FIG. 4 is a block diagram of a computer system 300 including the memory device 10 of FIG. 1 .
  • the computer system 300 includes computer circuitry 302 for performing various computing functions, such as executing specific software to perform specific calculations or tasks.
  • the computer system 300 includes one or more input devices 304 , such as a keyboard or a mouse, coupled to the computer circuitry 302 to allow an operator to interface with the computer system 300 .
  • the computer system 300 includes one or more output devices 306 coupled to the computer circuitry 302 , such output devices typically being a printer or a video terminal.
  • One or more data storage devices 308 are also typically coupled to the computer circuitry 302 to store data or retrieve data from the external storage media (not shown).
  • Examples of typical data storage devices 308 include hard and floppy disks, tape cassettes, and compact disk read only memories (“CD-ROMs”).
  • the computer circuitry 302 is typically coupled to the memory device 10 through a control bus, a data bus, and an address bus to provide for winding data to and reading data from the memory device 10 as previously explained.

Abstract

A test circuit detects defective memory cells in a memory device. The test circuit includes a test mode terminal adapted to receive a test mode signal. An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. The error detection circuit develops an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data. A control circuit is coupled to the test mode terminal, the error detection circuit, and the memory cells. The control circuit is operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.

Description

TECHNICAL FIELD
The present invention relates generally to the testing of semiconductor memories, and more specifically to a method and circuit for performing on-chip data compression to reduce the time for testing memory cells in a semiconductor memory.
BACKGROUND OF THE INVENTION
During the manufacture of semiconductor memories, such as a synchronous dynamic random access memories (“SDRAMs”), it is necessary to test each memory to ensure it is operating properly. Electronic and computer systems containing semiconductor memories also normally test the memories when power is initially applied to the system. A typical SDRAM includes a number of arrays, each array including a number of memory cells arranged in rows and columns. During testing of the SDRAM, each memory cell must be tested to ensure it is operating properly. In a typical prior art test method, data having a first binary value (e.g., a “1”) is written and read from all memory cells in the arrays, and thereafter data having a second binary value (e.g., a “0”) is typically written to and read from the memory cells. A memory cell is determined to be defective when the data written to the memory cell does not equal that read from the memory cell. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern 101010 . . . written to the memory cells in each row of the arrays.
In a typical test configuration, an automated memory tester is coupled to address, data, and control buses of the SDRAM, and develops signals on these buses to perform the desired tests. The tester applies data transfer commands on the control bus, addresses on the address bus, and either provides or receives data on the data bus depending on whether the data transfer command is a read or write. In addition, the tester develops a clock signal which drives circuitry in the SDRAM to synchronously perform each of the steps involved in a particular data transfer operation, as understood by one skilled in the art. The signals developed by the tester must satisfy particular timing parameters of the SDRAM that are established relative to particular edges of the clock signal.
In modern SDRAMs, the tester may need to develop a clock signal having a frequency of 100 megahertz or greater, and must also develop the associated address, data, and control signals at increasingly faster rates due to the shorter interval between rising edges of the clock signal. As the frequency of operation increases, the design and layout of circuitry associated with a particular application typically become more complex and, as a result, typically more expensive. This is due in part to the potential for coupling electromagnetic energy at high frequencies between circuit lines, the critical nature of the physical line lengths at high frequencies, and the potential for small delays to result in inoperability of the circuit. The tester could supply a lower frequency clock signal to the SDRAM, but this would increase the time and thus the cost of testing the SDRAM. Also, the test would then not be performed at the more stringent high speeds at which the SDRAM may operate during use. Thus, the tester must supply very high frequency clock signals to modem SDRAMs. Testers capable of operating at these higher frequencies are typically more expensive than lower frequency testers. In fact, the cost of such testers typically increases exponentially with increases in the frequency of operation. For example, a tester operating at 50 megahertz may cost approximately $1 million while a tester operating at 100 megahertz can cost up to $5 million.
In addition to the frequency of operation of the tester, the number of data transfer operations the tester must perform in writing data to and reading data from the memory cells affects the time and thus the cost of testing the SDRAM. As the storage capacity of SDRAM increases, the number of data transfers performed in testing every memory cell increases accordingly. For example, in a memory array having n rows and m columns of memory cells, the tester performs n×m cell accesses in writing the first binary data values to all the memory cells in the array, and thereafter performs n×m cell accesses in reading the same data. The tester must once again perform n×m access in writing data having a second binary value to each memory cell, and the same number of accesses in reading this data. The tester thus performs a total of four times n×m cell accessories, each of which requires a bus cycle to perform, in testing each memory cell in the array. In the case of a 16 megabit×4 DRAM, 67,108,864 bus cycles are required to perform a complete test of every memory cell.
There is a need for a test circuit that reduces the time it takes a low frequency memory tester to test the memory cells in a high frequency SDRAM.
SUMMARY OF THE INVENTION
A test circuit detects defective memory cells in a plurality of memory cells in a memory device. The test circuit includes a test mode terminal adapted to receive a test mode signal. An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. The error detection circuit develops an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data. A control circuit is coupled to the test mode terminal, the error detection circuit, and the memory cells. The control circuit is operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a functional block diagram of a test system including a memory device having a test circuit according to one embodiment of the present invention.
FIG. 2 is a functional block diagram of one embodiment of the error detection circuit of FIG. 1.
FIG. 3 is a schematic of one embodiment of the data compression circuits of FIG. 2.
FIG. 4 is a functional block diagram of a computer system including the memory device of FIG. 1.
 DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a functional block diagram of a test system 8 comprising a memory tester 9 coupled to a memory device 10 including a test circuit 12 according to one embodiment of the present invention. The memory tester 9 places the memory device 10 in a test mode during which the test circuit 12 detects the defective memory cells in the memory device 10 and provides a signal to the tester 9 indicating the presence of any such detected defective cells as will be explained in more detail below.
The memory device 10 includes an address decoder 20 receiving address signals on an address bus ADDR. The address decoder 20 decodes the address signals and outputs a decoded address to a number of memory-cell arrays 22-28. The memory-cell arrays 22-28 each include a number of memory cells (not shown in FIG. 1) arranged in rows and columns, each memory cell operable to store a bit of data as known in the art. A read/write circuit 30 is coupled between a data bus DATA and the arrays 22-28, and transfers data to and from the data bus DATA during read and write data transfer operations, respectively. A control circuit 16 controls the address decoder 20, arrays 22-28, and read/write circuit 30 responsive to a clock signal CLK received on a terminal 34. Although the address decoder 20, read/write circuit 30, and control circuit 16 are shown coupled only to the array 22, one skilled in the art will realize that these circuits are coupled to all of the arrays 22-28 to perform their desired functions.
The test circuit 12 includes a conventional frequency multiplier circuit 32 receiving the clock signal CLK through a transfer gate 36. In response to the clock signal CLK, the frequency multiplier circuit 32 develops a test clock signal TSTCLK having a frequency greater than the frequency of the clock signal CLK. The test clock signal TSTCLK is applied through a transfer gate 38 to the control circuit 16. The clock circuit 14 further includes a transfer gate 44 coupled between the clock terminal 34 and the control circuit 16 and receiving the test mode signal TM on its control input.
The test circuit 12 further includes an error detection circuit 18 receiving data signals D1-D4 from the arrays 22-28, respectively, and receiving control signals TEST, CLEAR, and {overscore (ENABLE)} from the control circuit 16. In response to these control signals the error detection circuit 18 compares the binary values of the data signals D1-D4, and develops an error signal ERROR on a terminal 46 indicating the result of this comparison, as will be explained in more detail below. The error detection circuit 18 can compare the binary values of the data signals D1-D4 to each other or to predetermined binary values, as understood by one skilled in the art.
FIG. 2 is a more detailed schematic block diagram of one embodiment of the error detection circuit 18 of FIG. 1. The error detection circuit 18 includes three data compression circuits 100-104 that collectively compress the data signals D1-D4 received from the arrays 22-28, as will be explained in more detail below. The data signals D1-D4 each include a complementary signal portion designated by the overbar in FIG. 2, with these complementary portions being omitted in FIG. 1 for the sake of brevity. A detailed schematic of one embodiment of the data compression circuit 100 is shown in FIG. 3. The data compression circuits 102 and 104 are identical to the data compression circuit 100 and thus, for the sake of brevity, only the circuit 100 will be described in more detail with reference to FIG. 3. The data compression circuit 100 includes a NAND gate 200 receiving the data signals D1 and D2 on its inputs, and a NAND gate 202 receiving the data signals {overscore (D1)} and {overscore (D2)} on its inputs. The output of the NAND gate 200 is applied to a gate of an NMOS drive transistor 204 and to a gate of a PMOS drive transistor 208. In response to the output of the NAND gate 200, the transistors 204 and 208 operate in a complementary manner to develop an output signal D[1-2] on a node 222. A first enable transistor 220 couples the source of the transistor 208 to a supply voltage source VCC in response to the test signal TEST applied to its gate through an inverter 206. A second enable transistor 216 couples the source of the transistor 204 to ground in response to the test signal TEST. The output of the NAND gate 202 is similarly coupled to a gate of an NMOS drive transistor 210 and to a gate of a PMOS drive transistor 214. In response to the output of the NAND gate 202, the transistor 210 and 214 operate in a complementary manner to develop an output signal {overscore (D)}[1-2] on an output node 224. The source of the transistor 210 is coupled through a third enable transistor 218 to ground in response to the test signal TEST, and the source of the transistor 214 coupled to the supply voltage source VCC through the enable transistor 220.
In operation, the data compression circuit 100 operates in an active 20 mode and an inactive mode in response to the test signal TEST. When the test signal TEST is inactive low, the enable transistors 216, 218 and 220 turn OFF isolating the drive transistors 204, 208, 210, and 214 from the supply voltage VCC and the ground. In this mode, high impedances are presented, respectively, on the output nodes 222 and 224 independent of the outputs of the NAND gates 200 and 202. When the test signal TEST is active high, the enable transistors 216 and 218 turn ON coupling the sources of the output transistors 204 and 210, respectively, to ground, and the enable transistor 220 turns ON coupling the sources of the output transistors 208 and 214 to the supply voltage source VCC. In the active mode, the state of the output signals D[1-2] and {overscore (D)}[1-2] is determined by the binary values of the data signals D1, {overscore (D1)} and D2, {overscore (D2)}. For example, assume the data signals D1 and D2 are both high. In response to the high data signals D1 and D2, the NAND gate 200 drives its output low turning OFF the transistor 204 and turning ON the transistor 208 which drives the voltage on the output node 222 high to approximately the supply voltage VCC through the transistors 208 and 220. When the data signals D1 and D2 are high, the data signals {overscore (D1)} and {overscore (D2)} are accordingly low. In response to the low data signals {overscore (D1)} and {overscore (D2)}, the NAND gate 202 drives its output high, turning OFF the transistor 214 and turning ON the transistor 210 thereby driving the voltage on the output node 224 low to approximately ground through the transistors 210 and 218. Thus, when the data signals D1 and D2 are both high, the data compression circuit 100 drives the output signals D[1-2] and {overscore (D)}[1-2] high and low, respectively.
The data compression circuit 100 operates in a complementary manner when the data signals D1 and D2 are low. More specifically, when the data signals D2 and D2 are low, the NAND gate 200 drives its output high turning the transistors 204 and 208 ON and OFF, respectively, and thereby driving the output signal D[1-2] low through the transistors 204 and 216. The data signals {overscore (D1)} and {overscore (D2)} are high when the signals D1 and D2 are low causing the NAND gate 202 to drive its output low. The low output from the NAND gate 202 turns the transistors 210 and 214 OFF and ON, respectively, which, in turn, drives the output signal D[1-2] high through the transistors 214 and 220. If the data signals D1 and D2 have different binary values, both the NAND gates 220 and 202 drive their outputs high. In response to the high output from the NAND gate 200, the output signal D[1-2] is driven low through the transistors 204 and 216. In the same way, the high output from the NAND gate 202 drives the output signal {overscore (D)}[1-2] low through the transistors 210 and 218.
The data compression circuit 100 compresses the complementary data signals D1, {overscore (D1)} and D2, {overscore (D2)} to the single pair of output signals D[1-2], {overscore (D)}[1-2]. When the data signals D1 and D2 are high, the output signals D[1-2] and {overscore (D)}[1-2] are high and low, respectively, and when the data signals D1 and D2 are low the output signals D[1-2] and D [1-2] are low and high, respectively. The data compression circuit 100 detects when the data signals D1 and D2 are unequal and drives the output signals D[1-2] and {overscore (D)}[1-2] are low. It should be noted, however, that the data compression circuit 100 is limited to detecting the failure of a single memory cell. This is true because the failure of multiple memory cells could go undetected by the circuit 100. For example, assume the two memory cells storing data corresponding to the data signals D1 and D2 both fail in a way that they always store a binary 1 regardless of the data written to the cell. In this situation, the data compression circuit 100 will not detect an error because the data signals D1 and D2, although erroneous, are equal.
Returning now to FIG. 2, the data compression circuit 102 receives the data signals D3, {overscore (D3)} and D4, {overscore (D4)} and the test signal TEST, and develops output signals D[3-4] and {overscore (D)}[3-4]. The data compression circuit 104 receives the output signals D[1-2], D[1-2] from the data compression circuit 100 and the output signals D[3-4] and {overscore (D)}[3-4] from the data compression circuit 102 and develops output signals D[1-4] and {overscore (D)}[1-4]. The output signals D[1-4] and {overscore (D)}[1-4] are applied to the inputs of a NOR gate 106 which drives its output high when both the signals D[1-4] and {overscore (D)}[1-4] are low. The test signal TEST is applied through an inverter 108 to an enable input of the NOR gate 106. When the test signal TEST is high, the NOR gate 106 is enabled and operates as a conventional NOR gate, and when the test signal TEST is inactive low the NOR gate 106 is disabled placing its output in a high impedance state. The output of the NR gate 106 is coupled to an input of an error latch 108 that latches an error signal ERROR active high in response to the output of the NOR gate 106 going high. More specifically, the output of the NOR gate 106 is applied to a set input of an RS flip-flop 110 including a pair of cross-coupled NOR gates 112 and 114. A clear signal CLEAR is applied to a reset input of the RS flip-flop 110 and is further applied to a gate of an NMOS transistor 116 coupled between the set input of the RS flip-flop 110 and ground. The RS flip-flop 110 develops the error signal ERROR on the output of the NOR gate 114. In operation, when the clear signal CLEAR is inactive low and the output of the NOR gate 106 goes high, the RS flip-flop 110 latches the error signal ERROR active high. The RS flip-flop 110 maintains the error signal ERROR active high until the clear signal CLEAR goes active high. When the clear signal CLEAR goes high, the transistor 116 turns ON driving the set input low and reset input high and the RS flip-flop 110 latches the error signal ERROR inactive low. The error signal ERROR is applied through a transfer gate 118 to the terminal 46 of the memory device 10. The transfer gate 118 receives the enable signal {overscore (ENABLE)} from the control circuit 76 (FIG. 1) on its control input and applies the error signal ERROR on the terminal 46 when the enable signal {overscore (ENABLE)} is active low.
Returning now to FIG. 1, the overall operation of the test system 8 and operation of the memory device 10 outside of the test system 9 will now be described in more detail. The memory device 10 operates in two mode, a normal mode and a test mode. The memory device 10 operates in the normal mode outside of the test system 9. In the normal mode of operation, an external circuit (not shown in FIG. 1), such as a microprocessor, drives the test mode signal TM inactive low and applies address, data, and control signals on the respective buses of the memory device 10, and applies the clock signal CLK on the clock terminal 34. When the test mode signal TM is inactive low, the transfer gates 36 and 38 turn OFF and the signal CLK is transferred through the activated transfer gate 44 to the control circuit 16. In response to the signal CLK, the control circuit 16 controls the address decoder 20, arrays 22-28, and read/write circuit 30 to perform data transfer operations. During data transfer operations, the external circuit places address, data, and control signals on the response buses to form a command, such as an ACTIVE, READ, or WRITE command, as understood by one skilled in the art. The commands is latched by the memory device 10 in response to a rising edge of the clock signal CLK. In response to a READ command, the address decoder 20 decodes the latched memory address and accesses the addressed memory cells in the arrays 22-28. The data stored in the accessed memory cells in the arrays 22-28 is transferred through the read/write circuit 30 and onto the data bus DATA where it is available to be read by the external circuit. In response to a WRITE command, the address decoder 20 once again decodes the latched address and accesses the addressed memory cells in the arrays 22-28. The read/write circuit 30 then transfers the data placed on the data bus DATA to the addressed memory cells in the arrays 22-28 where it is stored.
The memory device 10 operates in the test mode when in the test system 8 as shown in FIG. 1. In the test mode of operation, the memory tester 9 applies data transfer commands to the memory device 10 in the form of address, data, and control signals on the respective buses, as well as the clock signal CLK and the test mode signal TM. To place the memory device 10 in the test mode of operation, the memory tester 9 drives the test mode signal TM active high turning OFF the transfer gate 44 and turning ON the transfer gates 36 and 38 such that the frequency multiplier circuit 32 drives the control circuit 16 with the test clock signal TSTCLK. In response to the test clock signals TSTCLK, the control circuit 16 controls the arrays 22-28 and the error detection circuit 18 to test for defective memory cells in the arrays 22-28, as will now be described in more detail. Although the test mode signal TM is shown as being applied on a single terminal of the memory device 10, one skilled in the art will realize that the test mode signal TM may take a variety of forms. For example, the test mode signal TM may correspond to a separate logic level signal, a “super voltage” applied to one of the pins of the memory device 10, or a combination of control signals on the control bus such as providing a column address strobe signal {overscore (CAS)} before a row address strobe signal {overscore (RAS)} to place the memory device 10 in the test mode of operation.
Before the control circuit 16 begins testing memory cells in the arrays 22-28, a test data pattern must be written to all the memory cells in the arrays 22-28. Such a test data pattern may be written to the arrays 22-28 in a number of different ways. First, the memory tester 9 may apply WRITE commands to the memory device 10 to write the desired test data pattern into the memory cells in the arrays 22-28. The memory tester 9 may write such test data to the arrays 22-28 either before or after the memory tester 9 places the memory device 10 in the test mode of operation. Alternatively, after being placed in the test mode the control circuit 16 may generate the test data written to the arrays 22-24. The test data pattern written to the memory cells in the arrays 22-28 may vary with some memory cells storing binary 0s and others storing binary 1s.
After the desired test data has been written to the arrays 22-28, the control circuit 16 drives the signals TEST and {overscore (ENABLE)} active high and low, respectively, activating the error detection circuit 18. The control circuit 16 then pulses the clear signal CLEAR active high to ensure the error signal ERROR output by the error detection circuit 18 is initially inactive low. The control circuit 16 thereafter activates a row of memory cells in each of the arrays 22-28 and accesses an individual memory cell in each of the activated rows. The data stored in the accessed memory cells in the arrays 22-28 corresponds to the data signals D1-D4, respectively. The data signals D1-D4 are applied to the inputs of the error detection circuit 18, which operates as previously described to determine whether the data stored in all the accessed memory cells is equal. When the data stored in the accessed memory cells is equal, the error detection circuit 18 maintains the error signal ERROR inactive low, and when the data is unequal the error detection circuit 18 drives the error signal ERROR active high. The memory tester 9 monitors the error signal ERROR on the terminal 46 to determine whether any of the accessed memory cells is defective. Notice that since the control circuit 16 is operating at a higher frequency determined by the test clock signal TSTCLK, the memory tester 9 cannot typically detect the state of the error signal ERROR after the error detection circuit 18 compares the data stored in each group of four memory cells in the arrays 22-28. Instead, the memory tester 9 typically detects the error signal ERROR after a predetermined number of comparisons have been made by the error detection circuit 18. For example, the control circuit 16 may apply the data stored in every memory cell in the activated rows in the arrays 22-28 to the error detection circuit 18 and thereafter detect the state of the error signal ERROR. If the error signal ERROR is active, the memory tester 9 knows that at least one of the memory cells in one of the activated rows in the arrays 22-28 is defective. After the memory tester 9 has detected the state of the error signal ERROR, the control circuit 16 pulses the clear signal CLEAR active high to ensure the error signal ERROR in reset inactive low. The control circuit 16 then controls the arrays 22-28 and error detection circuit 18 as previously described to activate rows of memory cells in the arrays 22-28 and test the memory cells in each of the activated rows. The memory cells in the arrays 22-28 are accessed such that the accessed memory cells each store the same binary data if not defective. Thus, the test data pattern written to the memory cells and the sequence of activating the cells ensure the cells being accessed store the same binary data if operating properly. One skilled in the art will realize, however, other embodiments of the error detection circuit 18 could allow cells storing different data to be accessed and that data applied to the circuit 18. For example, in FIG. 3 the data signals D1, {overscore (D1)} could be coupled through inverters to their associated NAND gates. In such an embodiment, the data compression circuit 100 indicates no error when the signals D1 and D2 have different binary values and detects an error when such values are equal.
The test circuit 12 enables the external memory tester 9 operating at a rate determined by a lower frequency clock signal CLK to test the memory device 10 much more quickly than in a conventional test system. In a conventional test system, the external memory tester 9 drives the memory device 10 with the clock signal CLK and transfers data to and from the memory device 10 at a slower rate corresponding to the lower frequency of the clock signal CLK. With the test circuit 12, however, once the external test circuit 48 has transferred the desired test data pattern into the memory cells in the arrays 22-28, the test circuit 12 accesses the memory cells in the arrays 22-28 at a much faster rate determined by the higher frequency of the test clock signal TSTCLK. The faster rate at which the memory cells in the arrays 22-28 are accessed results in a corresponding decrease in the test time of the memory device 10 including the test circuit 12. In addition, additional time savings in testing the memory device 10 is realized by the data compression performed by the error detection circuit 18. The tests circuit 12 enables the data stored in four memory cells to be simultaneously accessed and compared to determine whether any of the accessed memory cells is defective. Thus, the test circuit 12 reduces the time it takes to read the test data stored in the arrays 22-28 to detect a defective memory cell. In a conventional test system, each memory cell in each of the arrays 22-28 must be accessed individually and the data stored in that cell read by the memory tester 9 to determine whether the data stored in the memory cell equals the data initially written to that memory cell. With the test circuit 12, however, the time it takes to read the data stored in all of the memory cells in the arrays 22-28 is reduced because the error detection circuit 18 simultaneously compares the data in four accessed memory cells.
In the embodiment of FIG. 1, the test circuit 12 accesses a single memory cell in each of the arrays 22-28 and applies the data stored in each accessed memory cell to a respective input of the error detection circuit 18. One skilled in the art will realize the structure of the error detection circuit 18 and interconnection between the circuit 18 and arrays 22-28 may vary. The number of memory-cell arrays may vary and the number of inputs to the error detection circuit 18 may vary accordingly. For example, the memory device 10 may include thirty-two memory-cell arrays each coupled to one input of the error detection circuit 18. One skilled in the art will realize more data signals may be compared by the error detection circuit 18 simply by cascading more data compression circuits 100-104 in a circuit analogous to that shown in FIG. 2. Alternatively, a number of memory cells in a single array may be simultaneously accessed and the data applied to the error detection circuit 18. Furthermore, different data can be written to the arrays 22-28 as long as the logic functions implemented by the data compression circuits 100, 102 are designed to decode the pattern of data written to the arrays 22-28. In addition, the test circuit 12 may be utilized in a variety of the memory devices 10 including SDRAMs, asynchronous DRAMs, static RAMs, and packetized SDRAMs such as Synclink DRAMs (“SLDRAMs”).
FIG. 4 is a block diagram of a computer system 300 including the memory device 10 of FIG. 1. The computer system 300 includes computer circuitry 302 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. In addition, the computer system 300 includes one or more input devices 304, such as a keyboard or a mouse, coupled to the computer circuitry 302 to allow an operator to interface with the computer system 300. Typically, the computer system 300 includes one or more output devices 306 coupled to the computer circuitry 302, such output devices typically being a printer or a video terminal. One or more data storage devices 308 are also typically coupled to the computer circuitry 302 to store data or retrieve data from the external storage media (not shown). Examples of typical data storage devices 308 include hard and floppy disks, tape cassettes, and compact disk read only memories (“CD-ROMs”). The computer circuitry 302 is typically coupled to the memory device 10 through a control bus, a data bus, and an address bus to provide for winding data to and reading data from the memory device 10 as previously explained.
It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. Therefore, the present invention is to be limited only by the appended claims.

Claims (29)

1. A test circuit for detecting defective memory cells in a plurality of memory cells in a memory device, the test circuit comprising:
a test mode terminal adapted to receive a test mode signal;
an error detection circuit including a plurality of inputs and an output, each input coupled to some of the plurality of memory cells, the error detection circuit developing an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data, the error detection circuit comprising:
a first data compression circuit including first and second pairs of complementary inputs adapted to receive first and second complementary data signals, respectively, and having a pair of outputs;
a second data compression circuit including first and second pairs of complementary inputs adapted to receive third and fourth complementary data signals, respectively, and having a pair of outputs;
a third data compression circuit including a first pair of complementary inputs coupled respectively to the outputs of the first data compression circuit, and a second pair of complementary inputs coupled respectively to the outputs of the second data compression circuit and having a pair of outputs;
a logic gate having an output and having inputs coupled respectively to the outputs of the third data compression circuit, and
a latch having a set input coupled to the output of the logic gate and an output coupled to a data terminal of the memory device; and
a control circuit coupled to the test mode terminal, the error detection circuit, and the memory-cells, the control circuit operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.
2. The test circuit of claim 1 wherein the memory cells are located in a plurality of arrays, each array coupled to an input of the error detection circuit and the control circuit simultaneously accessing at least one memory cell in each of the plurality of arrays.
3. The test circuit of claim 1 wherein the error detection circuit comprises the data signals applied on its inputs and develops the error signal in response to the compressed data.
4. The test circuit of claim 1 wherein the plurality of memory cells are located in a plurality of arrays.
5. A test circuit for detecting defective memory cells in a plurality of memory-cell arrays in a memory device, the test circuit comprising:
a test mode terminal adapted to receive a test mode signal;
an external clock terminal adapted to receive an external clock signal having a frequency;
a clock multiplier circuit having an input coupled to the external clock terminal, the multiplier circuit developing an internal clock signal on an output in response to the external clock signal, the internal clock signal having a frequency greater than the frequency of the external clock signal;
an error detection circuit including an output coupled to a terminal of the memory device, a clear terminal adapted to receive a clear signal, an enable signal adapted to receive an enable signal, and further including a plurality of inputs, each input coupled to one of the plurality of memory-cell arrays, the error detection circuit operable, when the enable signal is active, to develop an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data, and to drive the error signal inactive responsive to the clear signal, the error detection circuit comprising:
a first data compression circuit including first and second pairs of complementary inputs adapted to receive first and second complementary data signals, respectively and having a pair of outputs;
a second data compression circuit including first and second pairs of complementary inputs adapted to receive third and fourth complementary data signals, respectively and having a pair of outputs;
a third data compression circuit including a first pair of complementary inputs coupled respectively to the outputs of the first data compression circuit, and a second pair of complementary inputs coupled respectively to the outputs of the second data compression circuit, and having a pair of outputs;
a logic gate having an output and having inputs coupled respectively to the outputs of the third data compression circuit; and
a latch having an input coupled to the output of the logic gate and an output coupled to a data terminal of the memory device; and
a control circuit coupled to the test mode terminal, the output of the clock multiplier circuit, and the memory-cell arrays, the control circuit operable, when the test mode signal is active, responsive to the internal clock signal to apply the data of accessed memory cells in the arrays to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values, the control circuit applying the data of accessed memory cells to the error detection circuit until all memory cells in the arrays have been accessed, and activating the clear signal after the data of a predetermined number of memory cells has bean applied to the error detection circuit.
6. The test circuit of claim 5 wherein the control circuit simultaneously accesses at least one memory cell in each of the plurality of arrays and applies the data stored in the accessed memory cells it associated inputs of the error detection circuit.
7. The test circuit of claim 5 wherein the error detection circuit compresses the data applied on its inputs and develops the error signal in response to the compressed data.
8. A memory device, comprising:
an address bus;
a control bus;
a data bus;
a test mode terminal adapted to receive a test mode signal;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a read/write circuit coupled to the data bus;
an array coupled to the address decoder and read/write circuit, the array including a plurality of memory cells; and
a test circuit coupled to the data bus, comprising:
an error detection circuit including a plurality of inputs and an output, each input coupled to some of the plurality of memory cells, the error detection circuit developing an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data, the error detection circuit comprising:
a first data compression circuit including first and second pairs of complementary inputs adapted to receive first and second complementary data signals, respectively, and having a pair of outputs;
a second data compression circuit including first and second pairs of complementary inputs adapted to receive third and fourth complementary data signals, respectively and having a pair of outputs;
a third data compression circuit including a first pair of complementary inputs coupled respectively to the outputs of the first data compression circuit, and a second pair of complementary inputs coupled respectively to the outputs of the second data compression circuit, and having a pair of outputs;
a logic gate having an output and having inputs coupled respectively to the outputs of the third data compression circuit; and
a latch having a set input coupled to the output of the logic gate and an output coupled to a data terminal of the memory device; and
a control circuit coupled to the test mode terminal, the error detection circuit, and the array, the control circuit operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.
9. The memory device of claim 8 wherein each memory cell comprises:
an access transistor having a gate terminal coupled to a respective word line associated with each row of memory cells in the array, and a drain terminal coupled to one of a respective pair of complementary digit lines associated with each column of memory cells and a source terminal; and
a capacitor having a first plate coupled to the source terminal, and a second plate coupled to receive a reference voltage.
10. The memory device of claim 8, further including a plurality of arrays.
11. A test system for detecting defects in a memory device having address, data and control buses a memory cell array having a plurality of memory cells arranged in rows and columns, and a test mode terminal adapted to receive a test mode signal, the test system comprising:
an error detection circuit including a plurality of inputs and an output, each input coupled to some of the plurality of memory cells, the error detection circuit developing an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data, the error detection circuit comprising:
a first data compression circuit including first and second pairs of complementary inputs adapted to receive first and second complementary data signals, respectively, and having a pair of outputs;
a second data compression circuit including first and second pairs of complementary inputs adapted to receive third and fourth complementary data signals, respectively, and having a pair of outputs;
a third data compression circuit including a first pair of complementary inputs coupled respectively to the outputs of the first data compression circuit, and a second pair of complementary inputs coupled respectively to the outputs of the second data compression circuit and having a pair of outputs;
a logic gate having an output and having inputs coupled respectively to the outputs of the third data compression circuit; and
a latch having a set of input coupled to the output of the logic gate and an output coupled to a data terminal of the memory device;
a control circuit coupled to the test mode terminal, the error detection circuit, and the memory-cells, the control circuit operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary value; and
a memory tester coupled to the address, data, and control buses of the memory device and to the test method terminal, the memory tester activating the test mode signal to place the memory device into a test mode, storing a predetermined test pattern of data in the memory cells, and detecting a defect in the memory device when the error signal goes active.
12. The system of claim 11 wherein the memory tester sequentially applies separate predetermined test patterns of data that are stored in the memory cells, the memory tester determining at least once after applying a respective test pattern and before applying a subsequent test pattern whether the error signal is active.
13. A computer system, comprising:
a data input device;
a data output device; and
computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device having a data terminal adapted to receive a data signal and having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data, and a test circuit having a test mode terminal adapted to receive a test mode signal, the test circuit comprising:
an error detection circuit including a plurality of inputs and an output, each input coupled to some of the plurality of memory cells, the error detection circuit developing an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data, the error detection circuit comprising:
a first data compression circuit including first and second pairs of complementary inputs adapted to receive first and second complementary data signals, respectively, and having a pair of outputs;
a second data compression circuit including first and second pairs of complementary inputs adapted to receive third and fourth complementary data signals, respectively, and having a pair of outputs;
a third data compression circuit including a first pair of complementary inputs coupled respectively to the outputs of the first data compression circuit, and a second pair of complementary inputs coupled respectively to the outputs of the second data compression circuit, and having a pair of outputs;
a logic gate having an output and having inputs coupled respectively to the outputs of the third data compression circuit; and
a latch having a set input coupled to the output of the logic gate and an output coupled to a data terminal of the memory device; and
a control circuit coupled to the test mode terminal, the error detection circuit, and the memory cells, the control circuit operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.
14. The computer system of claim 13 wherein the memory cells are located in a plurality of arrays.
15. An error detection circuit for detecting defective memory cells in a plurality of memory cells in a memory device, the plurality of memory cells arranged in a plurality of memory-cell arrays, the error detection circuit adapted to receive a test mode signal and being coupled to each memory-cell array and to a terminal of the memory device, the error detection circuit operable when the test mode signal is active to simultaneously receive data from at least one memory cell in each of the plurality of memory-cell arrays and to apply an active error signal on the terminal when the data is different from expected values, the error detection circuit including a plurality of data compression circuits coupled to progressively compress the data received from the at least one memory cells and generate a data compression signal having a value indicative of the result of the data compression, and the error detection circuit generating the error signal responsive to the data compression signal.
16. The error detection circuit of claim 15 wherein the data compression signal comprises a complementary pair of signals and wherein the error detection circuit further includes a logic gate coupled to the receive the complementary signals and having an output, and further including a latch coupled to the output of the logic gate and an output coupled to the terminal of the memory device.
17. The error detection circuit of claim 15 wherein the memory cells are located in a plurality of arrays, each array coupled to the error detection circuit and the error detection circuit simultaneously receiving data from at least one memory cell in each of the plurality of arrays.
18. A memory device, comprising:
an address bus;
a control bus;
a data bus;
a test mode terminal adapted to receive a test mode signal;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a read/write circuit coupled to the data bus;
a plurality of memory-cell arrays coupled to the address decoder and read/write circuit, the arrays including a plurality of memory cells; and
an error detection circuit for detecting defective memory cells in each array, the error detection circuit adapted to receive the test mode signal and being coupled to each memory-cell array and to one of the address, control, and data busses, the error detection circuit operable when the test mode signal is active to simultaneously receive data from at least one memory cell in each of the plurality of memory-cell arrays and to apply an active error signal on one of the address, control, and data busses when the data is different from expected values, the error detection circuit including a plurality of data compression circuits coupled to progressively compress the data received from the at least one memory cells and generate a data compression signal having a value indicative of the result of the data compression, and the error detection circuit generating the error signal responsive to the data compression signal.
19. The memory device of claim 18 wherein the data compression signal comprises a complementary pair of signals and wherein the error detection circuit further includes a logic gate coupled to the receive the complementary signals and having an output, and further including a latch coupled to the output of the logic gate and an output coupled to the terminal of the memory device.
20. A test system for detecting defects in a memory device having address, data and control buses, a memory-cell array having a plurality of memory cells arranged in rows and columns, and a test mode terminal adapted to receive a test mode signal, the test system comprising:
an error detection circuit coupled to the test mode terminal and being coupled to the memory-cell array and to one of the address, control, and data busses, the error detection circuit operable when the test mode signal is active to receive from accessed memory cells and to apply an active error signal on one of the address, control, and data busses when the data is different from expected values, the error detection circuit including a plurality of data compression circuits coupled to progressively compress data from accessed memory cells.
21. The test system of claim 20 wherein the memory tester sequentially applies separate predetermined test patterns of data that are stored in the memory cells, the memory tester determining at least once after applying a respective test pattern and before applying a subsequent test pattern whether the error signal is active.
22. A computer system, comprising:
a data input device;
a data output device; and
computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device including,
an address bus;
a control bus;
a data bus;
a test mode terminal adapted to receive a test mode signal;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a read/write circuit coupled to the data bus;
a plurality of memory-cell arrays coupled to the address decoder and read/write circuit, the arrays including a plurality of memory cells; and
an error detection circuit for detecting defective memory cells in each array, the error detection circuit adapted to receive the test mode signal and being coupled to each memory-cell array and to one of the address, control, and data busses, the error detection circuit operable when the test mode signal is active to simultaneously receive data from at least one memory cell in each of the plurality of memory-cell arrays and to apply an active error signal on one of the address, control, and data busses when the data is different from expected values, the error detection circuit including a plurality of data compression circuits coupled to progressively compress the data from the at least one memory cells and generate a data compression signal having a value indicative of the result of the data compression, and the error detection circuit generating the error signal responsive to the data compression signal.
23. The computer system of claim 22 wherein the data compression signal comprises a complementary pair of signals and wherein the error detection circuit further includes a logic gate coupled to the receive the complementary signals and having an output, and further including a latch coupled to the output of the logic gate and an output coupled to the terminal of the memory device.
24. A method of detecting defective memory cells in a memory device including a plurality of memory-cell arrays, the method comprising:
placing the memory device in a test mode;
storing test data in the memory cells in the plurality of arrays;
accessing memory cells in at least some of the arrays;
progressively compressing the data stored in the accessed memory cells to generate a compression signal;
generating an error signal responsive to the data compression signal;
storing the error signal;
placing the error signal on a terminal of the memory device; and
detecting a defective memory cell responsive to the error signal being active.
25. The method of claim 24 wherein storing test data in the memory cells in the plurality of arrays includes transferring the same binary value of data to all memory cells in the arrays.
26. The method of claim 24 wherein placing the memory device in a test mode occurs after the step of storing test data.
27. A method of detecting defective memory cells in a memory device, comprising:
writing test data to the memory cells;
reading the test data from the memory cells;
compressing the data stored in the accessed memory cells a first time to generate a first set of data compression signals;
compressing the first set of data compression signals to generate an output data compression signal;
generating an error signal responsive to the output data compression signal; and
detecting a defective memory cell responsive to the error signal.
28. The method of claim 27 wherein writing test data to the memory cells comprises writing the same binary value to all the memory cells.
29. A method of detecting defective memory cells in a memory device, comprising:
writing test data to the memory cells;
reading the test data from the memory cells;
an error detection circuit for detecting defective memory cells in each array, the error detection circuit adapted to receive the test mode signal and being coupled to the memory-cell arrays and to one of the address, control, and data buses, the error detection circuit operable when the test mode signal is active to receive data from accessed memory cells and to apply an active error signal on one of the address, control, and data busses when the data is different from expected values, the error detection circuit including a plurality of data compression circuits coupled to progressively compress data form accessed memory cells and generate a data compression signal having a value indicative of the result of the data compression, and the error detection circuit generating the error signal responsive to the data compression signal.
US10/139,131 1998-04-30 2002-05-02 Data compression circuit and method for testing memory devices Expired - Lifetime USRE38956E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/139,131 USRE38956E1 (en) 1998-04-30 2002-05-02 Data compression circuit and method for testing memory devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/070,558 US6058056A (en) 1998-04-30 1998-04-30 Data compression circuit and method for testing memory devices
US10/139,131 USRE38956E1 (en) 1998-04-30 2002-05-02 Data compression circuit and method for testing memory devices

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/070,558 Reissue US6058056A (en) 1998-04-30 1998-04-30 Data compression circuit and method for testing memory devices

Publications (1)

Publication Number Publication Date
USRE38956E1 true USRE38956E1 (en) 2006-01-31

Family

ID=22096027

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/070,558 Ceased US6058056A (en) 1998-04-30 1998-04-30 Data compression circuit and method for testing memory devices
US10/139,131 Expired - Lifetime USRE38956E1 (en) 1998-04-30 2002-05-02 Data compression circuit and method for testing memory devices

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/070,558 Ceased US6058056A (en) 1998-04-30 1998-04-30 Data compression circuit and method for testing memory devices

Country Status (1)

Country Link
US (2) US6058056A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040184327A1 (en) * 2003-01-31 2004-09-23 Yuichi Okuda Semiconductor memory device and test method
US20040210809A1 (en) * 2003-04-17 2004-10-21 Hynix Semiconductor Inc. Input/output compression test circuit
US20080005630A1 (en) * 2006-06-30 2008-01-03 Micron Technology, Inc. Memory device testing system and method using compressed fail data
US20080082871A1 (en) * 2006-09-28 2008-04-03 Samsung Electronics Co., Ltd. Semiconductor memory device and testing method of the same
US20090091985A1 (en) * 2007-10-04 2009-04-09 Hynix Semiconductor, Inc. Input circuit of semiconductor memory apparatus and control method of the same
US20150033089A1 (en) * 2013-07-26 2015-01-29 SK Hynix Inc. Semiconductor device

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6178532B1 (en) * 1998-06-11 2001-01-23 Micron Technology, Inc. On-chip circuit and method for testing memory devices
US6072737A (en) * 1998-08-06 2000-06-06 Micron Technology, Inc. Method and apparatus for testing embedded DRAM
US6295618B1 (en) * 1998-08-25 2001-09-25 Micron Technology, Inc. Method and apparatus for data compression in memory devices
US6034900A (en) 1998-09-02 2000-03-07 Micron Technology, Inc. Memory device having a relatively wide data bus
US6115303A (en) * 1998-10-09 2000-09-05 Micron Technology, Inc. Method and apparatus for testing memory devices
JP3495276B2 (en) * 1999-01-14 2004-02-09 日本電気株式会社 Semiconductor storage device
US6735729B1 (en) * 1999-08-18 2004-05-11 Micron Technology, Inc Compression circuit for testing a memory device
KR100370234B1 (en) * 1999-09-14 2003-01-29 삼성전자 주식회사 Apparatus for detecting faulty cells in semiconductor memory and method therefor
US6675312B1 (en) 2000-06-30 2004-01-06 Cypress Semiconductor Corp. Majority vote circuit for test mode clock multiplication
US6400188B1 (en) * 2000-06-30 2002-06-04 Cypress Semiconductor Corp. Test mode clock multiplication
US6928593B1 (en) * 2000-09-18 2005-08-09 Intel Corporation Memory module and memory component built-in self test
JP4125492B2 (en) * 2001-02-01 2008-07-30 株式会社日立製作所 Semiconductor integrated circuit device, test method, and manufacturing method of semiconductor integrated circuit device
JP4115676B2 (en) * 2001-03-16 2008-07-09 株式会社東芝 Semiconductor memory device
US6404250B1 (en) * 2001-03-28 2002-06-11 Infineon Technologies Richmond, Lp On-chip circuits for high speed memory testing with a slow memory tester
DE10121309B4 (en) 2001-05-02 2004-01-29 Infineon Technologies Ag Test circuit for testing a circuit to be tested
DE10124923B4 (en) * 2001-05-21 2014-02-06 Qimonda Ag Test method for testing a data memory and data memory with integrated test data compression circuit
DE10141026B4 (en) * 2001-08-22 2011-06-22 Qimonda AG, 81739 Method for testing memory units to be tested and test device
US7035965B2 (en) 2001-08-30 2006-04-25 Micron Technology, Inc. Flash memory with data decompression
ITRM20010556A1 (en) * 2001-09-12 2003-03-12 Micron Technology Inc DECODER TO DECODE SWITCHING COMMANDS IN INTEGRATED CIRCUIT TEST MODE.
US6898138B2 (en) * 2002-08-29 2005-05-24 Micron Technology, Inc. Method of reducing variable retention characteristics in DRAM cells
KR100452335B1 (en) * 2002-11-25 2004-10-12 삼성전자주식회사 Circuit and method for extending test data of semiconductor memory device possible high speed operation test
DE10260184B4 (en) * 2002-12-20 2005-08-25 Infineon Technologies Ag Memory module with a test device
US9015390B2 (en) * 2003-04-25 2015-04-21 Micron Technology, Inc. Active memory data compression system and method
KR100498502B1 (en) * 2003-06-09 2005-07-01 삼성전자주식회사 Semiconductor memory device providing for latency compensation by stacking reference data and test method thereof
KR100510553B1 (en) * 2003-10-30 2005-08-26 삼성전자주식회사 Memory device and input signal control method of memory device
JP4403023B2 (en) * 2004-06-14 2010-01-20 株式会社リコー Semiconductor memory device and memory access method
DE102004047719A1 (en) * 2004-09-30 2006-01-26 Infineon Technologies Ag Device for testing circuit unit with increased clock frequency has device for switching connection device between normal and frequency doubling modes with clock signal and frequency doubled clock signal fed to circuit unit respectively
US7506226B2 (en) * 2006-05-23 2009-03-17 Micron Technology, Inc. System and method for more efficiently using error correction codes to facilitate memory device testing
KR100809690B1 (en) * 2006-07-14 2008-03-07 삼성전자주식회사 Semiconductor memory device capable of low frequency test operation and test method of the same
US9710384B2 (en) * 2008-01-04 2017-07-18 Micron Technology, Inc. Microprocessor architecture having alternative memory access paths
JP5196538B2 (en) * 2008-02-12 2013-05-15 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit design method, semiconductor integrated circuit design program, and semiconductor integrated circuit
KR20120120798A (en) * 2011-04-25 2012-11-02 에스케이하이닉스 주식회사 Memory and test method for memory
KR20130131992A (en) * 2012-05-25 2013-12-04 에스케이하이닉스 주식회사 Test circuit and method of semiconductor memory apparatus
US10430190B2 (en) 2012-06-07 2019-10-01 Micron Technology, Inc. Systems and methods for selectively controlling multithreaded execution of executable code segments
US20230352111A1 (en) * 2022-04-29 2023-11-02 Changxin Memory Technologies, Inc. Memory array detection circuit and detection method, and memory

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148398A (en) * 1989-07-04 1992-09-15 Fujitsu Limited Semiconductor memory device with built-in test circuit and method for testing the same
US5231605A (en) * 1991-01-31 1993-07-27 Micron Technology, Inc. DRAM compressed data test mode with expected data
US5568437A (en) * 1995-06-20 1996-10-22 Vlsi Technology, Inc. Built-in self test for integrated circuits having read/write memory
US5859804A (en) * 1991-10-16 1999-01-12 International Business Machines Corporation Method and apparatus for real time two dimensional redundancy allocation
US5913928A (en) * 1997-05-09 1999-06-22 Micron Technology, Inc. Data compression test mode independent of redundancy
US5936901A (en) * 1998-03-19 1999-08-10 Micron Technology, Inc. Shared data lines for memory write and memory test operations

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148398A (en) * 1989-07-04 1992-09-15 Fujitsu Limited Semiconductor memory device with built-in test circuit and method for testing the same
US5231605A (en) * 1991-01-31 1993-07-27 Micron Technology, Inc. DRAM compressed data test mode with expected data
US5859804A (en) * 1991-10-16 1999-01-12 International Business Machines Corporation Method and apparatus for real time two dimensional redundancy allocation
US5568437A (en) * 1995-06-20 1996-10-22 Vlsi Technology, Inc. Built-in self test for integrated circuits having read/write memory
US5913928A (en) * 1997-05-09 1999-06-22 Micron Technology, Inc. Data compression test mode independent of redundancy
US6202179B1 (en) * 1997-05-09 2001-03-13 Micron Technology, Inc. Method and apparatus for testing cells in a memory device with compressed data and for replacing defective cells
US5936901A (en) * 1998-03-19 1999-08-10 Micron Technology, Inc. Shared data lines for memory write and memory test operations

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040184327A1 (en) * 2003-01-31 2004-09-23 Yuichi Okuda Semiconductor memory device and test method
US20040210809A1 (en) * 2003-04-17 2004-10-21 Hynix Semiconductor Inc. Input/output compression test circuit
US7171597B2 (en) * 2003-04-17 2007-01-30 Hynix Semiconductor Inc. Input/output compression test circuit
US20080005630A1 (en) * 2006-06-30 2008-01-03 Micron Technology, Inc. Memory device testing system and method using compressed fail data
US7596729B2 (en) 2006-06-30 2009-09-29 Micron Technology, Inc. Memory device testing system and method using compressed fail data
US20080082871A1 (en) * 2006-09-28 2008-04-03 Samsung Electronics Co., Ltd. Semiconductor memory device and testing method of the same
US7734967B2 (en) * 2006-09-28 2010-06-08 Samsung Electronics Co., Ltd. Semiconductor memory device and testing method of the same
US20090091985A1 (en) * 2007-10-04 2009-04-09 Hynix Semiconductor, Inc. Input circuit of semiconductor memory apparatus and control method of the same
US7668025B2 (en) * 2007-10-04 2010-02-23 Hynix Semiconductor Inc. Input circuit of semiconductor memory apparatus and control method of the same
US20150033089A1 (en) * 2013-07-26 2015-01-29 SK Hynix Inc. Semiconductor device
US9236145B2 (en) * 2013-07-26 2016-01-12 SK Hynix Inc. Semiconductor device

Also Published As

Publication number Publication date
US6058056A (en) 2000-05-02

Similar Documents

Publication Publication Date Title
USRE38956E1 (en) Data compression circuit and method for testing memory devices
US6178532B1 (en) On-chip circuit and method for testing memory devices
US7136316B2 (en) Method and apparatus for data compression in memory devices
US6072737A (en) Method and apparatus for testing embedded DRAM
US6684356B2 (en) Self-test ram using external synchronous clock
US5638331A (en) Burn-in test circuit and method in semiconductor memory device
US6907555B1 (en) Self-test circuit and memory device incorporating it
US6311299B1 (en) Data compression circuit and method for testing embedded memory devices
US6141276A (en) Apparatus and method for increasing test flexibility of a memory device
US5919269A (en) Supervoltage detection circuit having a multi-level reference voltage
US6195762B1 (en) Circuit and method for masking a dormant memory cell
JP4216405B2 (en) Semiconductor memory device having built-in parallel test circuit
US5285419A (en) Read/write memory with improved test mode data compare
US6161204A (en) Method and apparatus for testing SRAM memory cells
JP5587141B2 (en) Semiconductor device
JP3251253B2 (en) Semiconductor storage device
JP2004288299A (en) Semiconductor memory device
Kim et al. Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs
Wang A Universal Test Pattern Generator for DDR SDRAM
JPH03104100A (en) Semiconductor memory device

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001

Effective date: 20180629

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001

Effective date: 20190731