USRE39426E1 - Thermally enhanced flip chip package and method of forming - Google Patents

Thermally enhanced flip chip package and method of forming Download PDF

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Publication number
USRE39426E1
USRE39426E1 US09/379,985 US37998599A USRE39426E US RE39426 E1 USRE39426 E1 US RE39426E1 US 37998599 A US37998599 A US 37998599A US RE39426 E USRE39426 E US RE39426E
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Prior art keywords
flip chip
thermally conductive
planar member
substrate
chip package
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US09/379,985
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Eric Arthur Johnson
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GlobalFoundries Inc
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International Business Machines Corp
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Priority claimed from US08/715,212 external-priority patent/US5726079A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
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Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
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Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • This invention relates generally to encapsulated flip chips and more particularly to a flip chip package having a thermally conductive member encapsulated with the flip chip.
  • Flip chips are small semiconductor dies having terminations all on one side in the form of solder pads or bump contacts. Typically, the surface of the chip has been passivated or otherwise treated. The flip chip derives its name from the practice of flipping, or turning, the chip over after manufacture, prior to attaching the chip to a matching substrate.
  • Thermally conductive caps have also been provided for flip chips.
  • a capped chip has a thin layer of a thermally conductive grease between the chip and the cap.
  • the present invention is directed to overcoming the problems set forth above. It is desirable to have a flip chip package that provides low thermal resistance, and is economical to manufacture. It is also desirable to have such a flip chip package and method of manufacture that uses conventional transfer mold techniques. It is also desirable to have such a flip chip package that does not require the presence of a thermally conductive grease between the chip and a heat conducting member.
  • a flip chip package includes a substrate having a plurality of electrical circuits disposed within the substrate, a flip chip mounted on the substrate in electrical communication with predefined ones of the electrical circuits disposed in the substrate, and a thermally conductive planar member disposed in thermally conductive contact with an upper surface of the flip chip.
  • the flip chip package also includes the substantially rigid dielectric material that surrounds the edge surfaces of the thermally conductive planar member, the edge surfaces of the flip chip, and at least a portion of the substrate.
  • the flip chip package embodying the present invention includes include the thermally conductive planar member having a thickness selected to provide a composite structure with the flip chip that extends a predetermined distance above the substrate.
  • a method of forming a thermally enhanced flip chip package includes providing a substrate and a flip chip which are connected together such that the electrical contacts on the flip chip are in electrical communication with predetermined ones of the electrical contacts on the substrate.
  • the method also includes providing a thermally conductive planar member which is placed on the upper surface of the flip chip in thermally conductive communication with the upper surface.
  • the assembled planar member, flip chip and substrate are placed in a mold cavity wherein a predefined portion of the substrate cooperates to form a substantially closed cavity.
  • the moldable dielectric material is injected into the closed mold cavity and, after curing, forms a substantially rigid covering about the edges of the thermally conductive planar member, the flip chip, and the predefined portion of the substrate.
  • thermally enhanced flip chip package includes selecting a thermally conductive planar member having a thickness that is selected so that when the thermally conductive planar member is placed on the flip chip, the combined thickness of the planar member and the distance that the flip chip extends above the surface of the substrate, are substantially equal to the height of the aforementioned mold cavity.
  • FIG. 1 is a schematic sectional view of a flip chip package embodying the present invention, showing the flip chip and substrate components of the package in elevation;
  • FIG. 2 is a flow diagram of the principal steps carried out in forming a flip chip package, in accordance with the method embodying the present invention.
  • the flip chip package 10 includes a flip chip 12 that has a plurality of electrical contacts 14 that are electronically connected, for example by soldered joints, to corresponding contacts associated with one or more electrical circuits disposed in a substrate member.
  • the substrate member 16 is typically a laminated circuit board having a number of electrical circuits defined within the member and is adapted for interconnection with other components of an electronic assembly.
  • the flip chip 12 has a planar upper surface 12 18 that is spaced from the substrate 16 by a predefined distance, and a plurality of edge surfaces 20 that extend around a defined perimeter of the planar surface 18 and are disposed in substantially perpendicular relationship with the planar surface 18 .
  • the thermally enhanced flip chip package 10 embodying the present invention includes a thermally conductive planar member 22 that is disposed in thermally conductive communication with the planar upper surface 18 of the flip chip 12 .
  • the thermally conductive planar member 22 has a plurality of edge surfaces 24 that extend around the periphery of the planar member 22 .
  • the thermally enhanced flip chip package embodying the present invention also includes a substantially rigid dielectric material 26 , such as Toshiba XK6000 thermoset plastic, that surrounds, in intimate bonded contact, the edge surfaces 24 of the thermally conductive planar member 22 , the edge surfaces 20 of the flip chip 12 , and at least a portion of the laminated substrate 16 .
  • the dielectric material 26 effectively encapsulates the flip chip 12 , and a portion of the planar member 22 and the substrate 16 , without covering the upper exposed surface of the thermally conductive planar member 22 .
  • the thermally conductive planar members 22 may be formed by stamping from sheets, in a variety of thicknesses, and at very low cost. By using the appropriate thickness of planar member 22 , various thicknesses of chips may be accommodated within a single mold. For that purpose, it is desirable that the thermally conductive planar member 22 have a thickness that is selected to provide a composite structure, when mounted on top of the flip chip 12 , that extends a fixed predetermined distance above the substrate member 16 . Thus, by simply varying the thickness of the planar member 22 , the same mold cavity may be used for variously sized chips.
  • the thermally conducted conductive planar member 22 is placed in the mold cavity prior to inserting the flip chip 12 attached to the substrate member 16 into the mold cavity, after which the dielectric material 26 is injected into the cavity.
  • the thermally conductive planar member 22 may be prebonded to the planar upper surface 18 of the flip chip 12 by a thermally conductive adhesive material 28 prior to placing the bonded assembly into the mold cavity and injecting the dielectric material 26 into the cavity.
  • the thermally conductive planar material is formed of copper, which has a thermal coefficient of expansion substantially equal to that of laminated glass-epoxy printed wiring boards.
  • the method of forming an enhanced flip chip package 10 embodying the present invention includes providing a substrate member 16 having a plurality of electrical contacts disposed on an upper surface of the substrate member, as indicated at block 30 in FIG. 2 , and also providing a flip chip 12 having a plurality of electrical contacts 14 disposed on a lower surface, as indicated at block 32 .
  • the flip chip 12 is attached to the substrate member 16 , as indicated at block 34 , typically by a heating cycle in which solder interconnections are formed.
  • an underfill material such as Dexter's HYSOLTM 4511 epoxy may be used to provide electrical isolation between the connected contacts.
  • a thermally conductive planar member 22 preferably a copper plate, is provided as indicated at block 36 , and then placed on the upper surface 18 of the flip chip 12 so that the planar member 22 is in thermal communication with the upper surface of the flip chip 12 , as indicated at block 38 , either by intimate contact or by an adhesive bond to the upper surface 18 .
  • the aligned thermally conductive planar member 22 , the flip chip 12 , and the substrate member 16 are then placed in a mold cavity, as indicated at block 40 .
  • a portion of the substrate member 16 i.e., the immediate area surrounding the mounted flip chip 12 , cooperates with other predefined surfaces of the mold cavity to form a substantially closed cavity.
  • a moldable dielectric material such as a highly-filled epoxy, is then injected into the transfer mold, as indicated at block 42 , and surrounds the edge surfaces 24 of the planar member 22 and the flip chip 12 . As can be seen in FIG.
  • the dielectric material 26 also is forced into intimate contact against a portion of a lower surface of the thermally conductive member 22 and the surrounding area of the surface of the substrate member 16 , thus essentially providing effective encapsulation of the flip chip 12 and the thermally conductive planar member 22 with the substrate member 16 .
  • a substantially rigid dielectric covering is thereby formed over the thermally conductive planar member 22 , the flip chip 12 , and the predefined portion of the substrate member 16 , providing an integral, essentially inseparable, package 10 .
  • the formed package 10 is removed from the mold, as indicated at block 46 .
  • a single mold cavity may be advantageously used for a variety of differently sized flip chips 12 by varying the thickness of the planar member 22 . If accurately sized, there will be no dielectric material over the top exposed surface of the planar member 22 . This is desirable so that the heat conductive path from the flip chip 12 has a minimum number of interfacial resistances in the path of heat flow. Thus, it is desirable to control the thickness of the planar member 22 so that its upper surface is flush with the surface of the mold compound on the finished part. In this arrangement, no adhesive material would be required between the thermally conductive planar member 22 and the flip chip 12 , although a thermally conductive adhesive material as may be used, if desired, as an assembly aid.
  • the flip chip package arrangement and method of forming provides a flip chip package 10 that is reliable in performance and easy to manufacture. These objectives are accomplished by using the transfer mold technique to encapsulate the chip, along with a thermally conductive planar member 22 that is used as an insert during molding. Alternatively, the insert 22 maybe may be attached to the top of the flip chip 12 by use of a small amount of a thermally conductive adhesive material.
  • the planar member 22 may be stamped from sheets, of varying thicknesses, at very low cost. By using the appropriate thickness of insert, any thickness chip can be accommodated within a single mold.
  • the thickness of the planar member 22 should be selected to match the height of the cavity in the mold, when combined with the flip chip 12 , to avoid excessive loads on the chip-to-substrate interconnection when the mold is clamped.
  • the thermal performance of a flip chip package 10 embodying the present invention will be substantially identical to that of a capped chip, using thermal grease.
  • the flip chip package 10 embodying the present invention has the advantage of avoiding any possibility of pumping which may deplete the grease layer and increase the thermal resistance, as may occur with capped chips.
  • the performance of the flip chip package 10 embodying the present invention is significantly better than that of any package which uses overmold without the thermally conductive planar member 22 .
  • bending of the package 10 is reduced as a result of balancing the expansion of the substrate member 16 and the planar member 22 , providing high reliability and improved coplanarity when embodied in a Ball Grid Array (BGA) package.
  • BGA Ball Grid Array

Abstract

A thermally conductive planar member is in thermally conductive communication with a flip chip encapsulated within a dielectric material that surrounds portions of the thermally conductive planar member, the flip-chip, and a predefined portion of a substrate member. The present invention provides a flip chip package having pick-and-place capability without the thermal resistance disadvantage of capped chip packages.

Description

This application is a division of application of Ser. No. 08/666,155 filed Jun. 19, 1996, now abandoned.
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to encapsulated flip chips and more particularly to a flip chip package having a thermally conductive member encapsulated with the flip chip.
2. Background Art
Flip chips are small semiconductor dies having terminations all on one side in the form of solder pads or bump contacts. Typically, the surface of the chip has been passivated or otherwise treated. The flip chip derives its name from the practice of flipping, or turning, the chip over after manufacture, prior to attaching the chip to a matching substrate.
Flip chip packages require a cover of some type over the silicone silicon chip to protect it and to provide a large flat surface for pick-and-place operations. However, any cover or encapsulant above the chip increases the thermal resistance path to an ambient environment and, hence, the operational temperature of the chip.
Thermally conductive caps have also been provided for flip chips. Typically, a capped chip has a thin layer of a thermally conductive grease between the chip and the cap.
However, it has been found that during thermal cycling, the grease has a tendency to be pumped, or displaced from the interface between the chip and the cap, thus increasing the thermal resistance of the interface.
The present invention is directed to overcoming the problems set forth above. It is desirable to have a flip chip package that provides low thermal resistance, and is economical to manufacture. It is also desirable to have such a flip chip package and method of manufacture that uses conventional transfer mold techniques. It is also desirable to have such a flip chip package that does not require the presence of a thermally conductive grease between the chip and a heat conducting member.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a flip chip package includes a substrate having a plurality of electrical circuits disposed within the substrate, a flip chip mounted on the substrate in electrical communication with predefined ones of the electrical circuits disposed in the substrate, and a thermally conductive planar member disposed in thermally conductive contact with an upper surface of the flip chip. The flip chip package also includes the substantially rigid dielectric material that surrounds the edge surfaces of the thermally conductive planar member, the edge surfaces of the flip chip, and at least a portion of the substrate.
Other features of the flip chip package embodying the present invention includes include the thermally conductive planar member having a thickness selected to provide a composite structure with the flip chip that extends a predetermined distance above the substrate.
In accordance with another aspect of the present invention, a method of forming a thermally enhanced flip chip package includes providing a substrate and a flip chip which are connected together such that the electrical contacts on the flip chip are in electrical communication with predetermined ones of the electrical contacts on the substrate. The method also includes providing a thermally conductive planar member which is placed on the upper surface of the flip chip in thermally conductive communication with the upper surface. The assembled planar member, flip chip and substrate are placed in a mold cavity wherein a predefined portion of the substrate cooperates to form a substantially closed cavity. The moldable dielectric material is injected into the closed mold cavity and, after curing, forms a substantially rigid covering about the edges of the thermally conductive planar member, the flip chip, and the predefined portion of the substrate.
Other features of the method of forming a thermally enhanced flip chip package include selecting a thermally conductive planar member having a thickness that is selected so that when the thermally conductive planar member is placed on the flip chip, the combined thickness of the planar member and the distance that the flip chip extends above the surface of the substrate, are substantially equal to the height of the aforementioned mold cavity.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic sectional view of a flip chip package embodying the present invention, showing the flip chip and substrate components of the package in elevation; and
FIG. 2 is a flow diagram of the principal steps carried out in forming a flip chip package, in accordance with the method embodying the present invention.
 DETAILED DESCRIPTION OF A PRESENTLY PREFERRED EXEMPLARY EMBODIMENT
A flip chip package 10 embodying the present invention, is shown schematically in FIG. 1. The flip chip package 10 includes a flip chip 12 that has a plurality of electrical contacts 14 that are electronically connected, for example by soldered joints, to corresponding contacts associated with one or more electrical circuits disposed in a substrate member. The substrate member 16 is typically a laminated circuit board having a number of electrical circuits defined within the member and is adapted for interconnection with other components of an electronic assembly. The flip chip 12 has a planar upper surface 12 18 that is spaced from the substrate 16 by a predefined distance, and a plurality of edge surfaces 20 that extend around a defined perimeter of the planar surface 18 and are disposed in substantially perpendicular relationship with the planar surface 18.
Importantly, the thermally enhanced flip chip package 10 embodying the present invention includes a thermally conductive planar member 22 that is disposed in thermally conductive communication with the planar upper surface 18 of the flip chip 12. The thermally conductive planar member 22 has a plurality of edge surfaces 24 that extend around the periphery of the planar member 22.
The thermally enhanced flip chip package embodying the present invention also includes a substantially rigid dielectric material 26, such as Toshiba XK6000 thermoset plastic, that surrounds, in intimate bonded contact, the edge surfaces 24 of the thermally conductive planar member 22, the edge surfaces 20 of the flip chip 12, and at least a portion of the laminated substrate 16. The dielectric material 26 effectively encapsulates the flip chip 12, and a portion of the planar member 22 and the substrate 16, without covering the upper exposed surface of the thermally conductive planar member 22.
In one embodiment of the present invention, it is desirable to form the flip chip package 10 by transfer mold techniques. To reduce the number of molds that may be required to accommodate variously sized chips, the thermally conductive planar members 22 may be formed by stamping from sheets, in a variety of thicknesses, and at very low cost. By using the appropriate thickness of planar member 22, various thicknesses of chips may be accommodated within a single mold. For that purpose, it is desirable that the thermally conductive planar member 22 have a thickness that is selected to provide a composite structure, when mounted on top of the flip chip 12, that extends a fixed predetermined distance above the substrate member 16. Thus, by simply varying the thickness of the planar member 22, the same mold cavity may be used for variously sized chips.
In the preferred embodiment, the thermally conducted conductive planar member 22 is placed in the mold cavity prior to inserting the flip chip 12 attached to the substrate member 16 into the mold cavity, after which the dielectric material 26 is injected into the cavity. Alternatively, the thermally conductive planar member 22 may be prebonded to the planar upper surface 18 of the flip chip 12 by a thermally conductive adhesive material 28 prior to placing the bonded assembly into the mold cavity and injecting the dielectric material 26 into the cavity.
Preferably, the thermally conductive planar material is formed of copper, which has a thermal coefficient of expansion substantially equal to that of laminated glass-epoxy printed wiring boards.
The method of forming an enhanced flip chip package 10 embodying the present invention includes providing a substrate member 16 having a plurality of electrical contacts disposed on an upper surface of the substrate member, as indicated at block 30 in FIG. 2, and also providing a flip chip 12 having a plurality of electrical contacts 14 disposed on a lower surface, as indicated at block 32. The flip chip 12 is attached to the substrate member 16, as indicated at block 34, typically by a heating cycle in which solder interconnections are formed. If desired, an underfill material such as Dexter's HYSOL™ 4511 epoxy may be used to provide electrical isolation between the connected contacts.
A thermally conductive planar member 22, preferably a copper plate, is provided as indicated at block 36, and then placed on the upper surface 18 of the flip chip 12 so that the planar member 22 is in thermal communication with the upper surface of the flip chip 12, as indicated at block 38, either by intimate contact or by an adhesive bond to the upper surface 18.
The aligned thermally conductive planar member 22, the flip chip 12, and the substrate member 16 are then placed in a mold cavity, as indicated at block 40. A portion of the substrate member 16, i.e., the immediate area surrounding the mounted flip chip 12, cooperates with other predefined surfaces of the mold cavity to form a substantially closed cavity. A moldable dielectric material, such as a highly-filled epoxy, is then injected into the transfer mold, as indicated at block 42, and surrounds the edge surfaces 24 of the planar member 22 and the flip chip 12. As can be seen in FIG. 1, the dielectric material 26 also is forced into intimate contact against a portion of a lower surface of the thermally conductive member 22 and the surrounding area of the surface of the substrate member 16, thus essentially providing effective encapsulation of the flip chip 12 and the thermally conductive planar member 22 with the substrate member 16.
After curing the moldable dielectric material 28 26, as indicated at block 44, a substantially rigid dielectric covering is thereby formed over the thermally conductive planar member 22, the flip chip 12, and the predefined portion of the substrate member 16, providing an integral, essentially inseparable, package 10. After curing, the formed package 10 is removed from the mold, as indicated at block 46.
Preferably, in carrying out the method of forming a thermally integrated flip chip package 10, a single mold cavity may be advantageously used for a variety of differently sized flip chips 12 by varying the thickness of the planar member 22. If accurately sized, there will be no dielectric material over the top exposed surface of the planar member 22. This is desirable so that the heat conductive path from the flip chip 12 has a minimum number of interfacial resistances in the path of heat flow. Thus, it is desirable to control the thickness of the planar member 22 so that its upper surface is flush with the surface of the mold compound on the finished part. In this arrangement, no adhesive material would be required between the thermally conductive planar member 22 and the flip chip 12, although a thermally conductive adhesive material as may be used, if desired, as an assembly aid.
In summary, the flip chip package arrangement and method of forming provides a flip chip package 10 that is reliable in performance and easy to manufacture. These objectives are accomplished by using the transfer mold technique to encapsulate the chip, along with a thermally conductive planar member 22 that is used as an insert during molding. Alternatively, the insert 22 maybe may be attached to the top of the flip chip 12 by use of a small amount of a thermally conductive adhesive material.
The planar member 22 may be stamped from sheets, of varying thicknesses, at very low cost. By using the appropriate thickness of insert, any thickness chip can be accommodated within a single mold. The thickness of the planar member 22 should be selected to match the height of the cavity in the mold, when combined with the flip chip 12, to avoid excessive loads on the chip-to-substrate interconnection when the mold is clamped.
The thermal performance of a flip chip package 10 embodying the present invention, preferably without an adhesive layer, will be substantially identical to that of a capped chip, using thermal grease. Furthermore, the flip chip package 10 embodying the present invention has the advantage of avoiding any possibility of pumping which may deplete the grease layer and increase the thermal resistance, as may occur with capped chips. Importantly, the performance of the flip chip package 10 embodying the present invention, is significantly better than that of any package which uses overmold without the thermally conductive planar member 22. In addition, bending of the package 10 is reduced as a result of balancing the expansion of the substrate member 16 and the planar member 22, providing high reliability and improved coplanarity when embodied in a Ball Grid Array (BGA) package.
Although the present invention is described in terms of a preferred exemplary embodiment, those skilled in the art will recognize that changes in the order in which various components, e.g., the substrate member 16, the thermally conductive planar member 22, and the flip chip 12, are provided may be varied made without departing from the spirit of the invention. Such changes are intended to fall within the scope of the following claims. Other aspects, features, and advantages of the present invention may be obtained from a study of this disclosure and the drawings, along with the appended claims.

Claims (4)

1. A method of forming a flip chip package, comprising:
providing a substrate member having a plurality of electrical contacts disposed thereon;
providing a flip chip having a plurality of electrical contacts disposed on a lower surface, a planar upper surface, and a plurality of edge surfaces extending between said lower and said upper surfaces;
connecting the electrical contacts of said flip chip with selected ones of the electrical contacts on a top surface of said substrate;
providing a thermally conductive planar member having a plurality of peripherally disposed edge surfaces;
placing said thermally conductive planar member in thermally conductive communication with said upper surface of the flip chip;
placing said thermally conductive planar member, said flip chip, and said substrate member in a mold cavity wherein a predefined portion of said substrate member cooperates with said mold cavity to define a sealable cavity;
injecting a moldable dielectric material into said sealable cavity;
curing said moldable dielectric material and thereby forming a sealed rigid dielectric covering about the edge surfaces of said thermally conductive planar member, so that said moldable dielectric material is prevented from extending below said substrate member, the edge surfaces of said flip chip, and said predefined portion of said substrate member and forming an encapsulated flip chip package comprising said thermally conductive planar member, said flip chip, and said predefined portion of said substrate member, and
removing said flip chip package from said sealed covering mold cavity.
2. A method of forming a flip chip package, as set forth in claim 1 4, wherein said mold cavity has a first selected height and said thermally conductive planar member has a thickness selected so that when mounted on the upper planar surface of the flip chip, said planar member extends a second selected height being substantially equal to the first selected height of said mold cavity.
3. A method of forming a flip chip package, as set forth in claim 1 4, wherein placing said thermally conductive planar member on in thermally conductive communication with said upper surface of the flip chip includes bonding said planar member to the upper surface of the flip chip with a thermally conductive adhesive material.
4. A method of forming a flip chip package, as set forth in claim 1, further comprising the step, after providing a thermally conductive planar member, of placing said thermally conductive planar member in thermally conductive communication with said upper surface of the flip chip.
US09/379,985 1996-06-19 1999-08-24 Thermally enhanced flip chip package and method of forming Expired - Lifetime USRE39426E1 (en)

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US66615596A 1996-06-19 1996-06-19
US08/715,212 US5726079A (en) 1996-06-19 1996-09-17 Thermally enhanced flip chip package and method of forming
US09/379,985 USRE39426E1 (en) 1996-06-19 1999-08-24 Thermally enhanced flip chip package and method of forming

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090218703A1 (en) * 2008-02-29 2009-09-03 Soo Gil Park Lamination Tape for Reducing Chip Warpage and Semiconductor Device Containing Such Tape
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US20090218703A1 (en) * 2008-02-29 2009-09-03 Soo Gil Park Lamination Tape for Reducing Chip Warpage and Semiconductor Device Containing Such Tape
US20140335655A1 (en) * 2008-09-27 2014-11-13 Rui Huang Integrated circuit package system with mounting structure

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