USRE40552E1 - Dynamic random access memory using imperfect isolating transistors - Google Patents
Dynamic random access memory using imperfect isolating transistors Download PDFInfo
- Publication number
- USRE40552E1 USRE40552E1 US10/032,431 US3243101A USRE40552E US RE40552 E1 USRE40552 E1 US RE40552E1 US 3243101 A US3243101 A US 3243101A US RE40552 E USRE40552 E US RE40552E
- Authority
- US
- United States
- Prior art keywords
- sense
- bit line
- voltage
- logic
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
Description
Claims (25)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/032,431 USRE40552E1 (en) | 1990-04-06 | 2001-12-21 | Dynamic random access memory using imperfect isolating transistors |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB909007789A GB9007789D0 (en) | 1990-04-06 | 1990-04-06 | Method for dram sensing current control |
US68074791A | 1991-04-05 | 1991-04-05 | |
GB9107164A GB2242768A (en) | 1990-04-06 | 1991-04-05 | DRAM sensing control; connecting bitlines to sense amplifier |
US08/147,038 US5414662A (en) | 1990-04-06 | 1993-11-04 | Dynamic random access memory using imperfect isolating transistors |
US08/853,507 USRE37641E1 (en) | 1990-04-06 | 1997-05-08 | Dynamic random access memory using imperfect isolating transistors |
US10/032,431 USRE40552E1 (en) | 1990-04-06 | 2001-12-21 | Dynamic random access memory using imperfect isolating transistors |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/147,038 Reissue US5414662A (en) | 1990-04-06 | 1993-11-04 | Dynamic random access memory using imperfect isolating transistors |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE40552E1 true USRE40552E1 (en) | 2008-10-28 |
Family
ID=39874457
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/032,431 Expired - Lifetime USRE40552E1 (en) | 1990-04-06 | 2001-12-21 | Dynamic random access memory using imperfect isolating transistors |
Country Status (1)
Country | Link |
---|---|
US (1) | USRE40552E1 (en) |
Citations (95)
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-
2001
- 2001-12-21 US US10/032,431 patent/USRE40552E1/en not_active Expired - Lifetime
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