USRE41538E1 - Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby - Google Patents
Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby Download PDFInfo
- Publication number
- USRE41538E1 USRE41538E1 US11/113,454 US11345405A USRE41538E US RE41538 E1 USRE41538 E1 US RE41538E1 US 11345405 A US11345405 A US 11345405A US RE41538 E USRE41538 E US RE41538E
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- US
- United States
- Prior art keywords
- forming
- layer
- copper
- barrier layer
- dopant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims (75)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/113,454 USRE41538E1 (en) | 1999-07-22 | 2005-04-22 | Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14503699P | 1999-07-22 | 1999-07-22 | |
US15015699P | 1999-08-20 | 1999-08-20 | |
US09/619,587 US6521532B1 (en) | 1999-07-22 | 2000-07-19 | Method for making integrated circuit including interconnects with enhanced electromigration resistance |
US09/642,140 US6551872B1 (en) | 1999-07-22 | 2000-08-18 | Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby |
US11/113,454 USRE41538E1 (en) | 1999-07-22 | 2005-04-22 | Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/642,140 Reissue US6551872B1 (en) | 1999-07-22 | 2000-08-18 | Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE41538E1 true USRE41538E1 (en) | 2010-08-17 |
Family
ID=27386204
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/642,140 Ceased US6551872B1 (en) | 1999-07-22 | 2000-08-18 | Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby |
US11/113,454 Expired - Lifetime USRE41538E1 (en) | 1999-07-22 | 2005-04-22 | Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/642,140 Ceased US6551872B1 (en) | 1999-07-22 | 2000-08-18 | Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby |
Country Status (1)
Country | Link |
---|---|
US (2) | US6551872B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140352135A1 (en) * | 2013-05-30 | 2014-12-04 | Dyi-chung Hu | Circuit board structure with embedded fine-pitch wires and fabrication method thereof |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6509262B1 (en) * | 2000-11-30 | 2003-01-21 | Advanced Micro Devices, Inc. | Method of reducing electromigration in copper lines by calcium-doping copper surfaces in a chemical solution |
JP2003045877A (en) * | 2001-08-01 | 2003-02-14 | Sharp Corp | Semiconductor device and its manufacturing method |
US6515368B1 (en) * | 2001-12-07 | 2003-02-04 | Advanced Micro Devices, Inc. | Semiconductor device with copper-filled via includes a copper-zinc/alloy film for reduced electromigration of copper |
US6693356B2 (en) * | 2002-03-27 | 2004-02-17 | Texas Instruments Incorporated | Copper transition layer for improving copper interconnection reliability |
US7279423B2 (en) * | 2002-10-31 | 2007-10-09 | Intel Corporation | Forming a copper diffusion barrier |
US7026244B2 (en) * | 2003-08-08 | 2006-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low resistance and reliable copper interconnects by variable doping |
US7229922B2 (en) * | 2003-10-27 | 2007-06-12 | Intel Corporation | Method for making a semiconductor device having increased conductive material reliability |
US20050110142A1 (en) * | 2003-11-26 | 2005-05-26 | Lane Michael W. | Diffusion barriers formed by low temperature deposition |
KR100688055B1 (en) * | 2004-05-10 | 2007-02-28 | 주식회사 하이닉스반도체 | Method for manufacturing metal-interconnect using barrier metal formed low temperature |
US8308053B2 (en) * | 2005-08-31 | 2012-11-13 | Micron Technology, Inc. | Microfeature workpieces having alloyed conductive structures, and associated methods |
US7473634B2 (en) * | 2006-09-28 | 2009-01-06 | Tokyo Electron Limited | Method for integrated substrate processing in copper metallization |
FR2913283A1 (en) * | 2007-03-02 | 2008-09-05 | St Microelectronics Crolles 2 | Planar or U-shaped capacitive coupling device for dynamic RAM, has silicon regions forming roughness with respect to adjacent regions of same level in films, and electrodes and insulators forming conformal layer above silicon regions |
US7843063B2 (en) * | 2008-02-14 | 2010-11-30 | International Business Machines Corporation | Microstructure modification in copper interconnect structure |
US8288276B2 (en) * | 2008-12-30 | 2012-10-16 | International Business Machines Corporation | Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion |
WO2010143609A1 (en) * | 2009-06-12 | 2010-12-16 | 株式会社アルバック | Method for producing electronic device, electronic device, semiconductor device, and transistor |
DE102010063299A1 (en) * | 2010-12-16 | 2012-06-21 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Performance increase in metallization systems with microstructure devices by incorporation of a barrier interlayer |
US8981564B2 (en) * | 2013-05-20 | 2015-03-17 | Invensas Corporation | Metal PVD-free conducting structures |
KR102654482B1 (en) * | 2016-12-06 | 2024-04-03 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
Citations (44)
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US4233067A (en) | 1978-01-19 | 1980-11-11 | Sumitomo Electric Industries, Ltd. | Soft copper alloy conductors |
JPS60110868A (en) | 1983-11-18 | 1985-06-17 | Mitsubishi Metal Corp | Surface hardened au alloy member |
US4592891A (en) | 1984-06-14 | 1986-06-03 | Nippon Mining Co., Ltd. | Corrosion-resistant copper alloy |
JPS62127438A (en) | 1985-11-26 | 1987-06-09 | Nippon Mining Co Ltd | Bonding wire for semiconductor device |
JPS62133050A (en) | 1985-12-03 | 1987-06-16 | Nippon Mining Co Ltd | Manufacture of high strength and high conductivity copper-base alloy |
US4732731A (en) | 1985-08-29 | 1988-03-22 | The Furukawa Electric Co., Ltd. | Copper alloy for electronic instruments and method of manufacturing the same |
US4750029A (en) | 1984-08-31 | 1988-06-07 | Mitsubishi Shindoh Co., Ltd. | Copper base lead material for leads of semiconductor devices |
JPS6428337A (en) | 1987-07-24 | 1989-01-30 | Furukawa Electric Co Ltd | High-strength and high-conductivity copper alloy |
JPS6456842A (en) | 1987-08-27 | 1989-03-03 | Nippon Mining Co | Copper alloy foil for flexible circuit board |
US4908275A (en) | 1987-03-04 | 1990-03-13 | Nippon Mining Co., Ltd. | Film carrier and method of manufacturing same |
JPH02230756A (en) | 1989-03-03 | 1990-09-13 | Seiko Epson Corp | Copper electrode wiring material |
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US5130274A (en) | 1991-04-05 | 1992-07-14 | International Business Machines Corporation | Copper alloy metallurgies for VLSI interconnection structures |
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JPH09157775A (en) | 1995-09-27 | 1997-06-17 | Nikko Kinzoku Kk | Copper alloy for electronic equipment |
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US6037664A (en) | 1997-08-20 | 2000-03-14 | Sematech Inc | Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer |
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US6180523B1 (en) | 1998-10-13 | 2001-01-30 | Industrial Technology Research Institute | Copper metallization of USLI by electroless process |
US6181012B1 (en) * | 1998-04-27 | 2001-01-30 | International Business Machines Corporation | Copper interconnection structure incorporating a metal seed layer |
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US6214728B1 (en) | 1998-11-20 | 2001-04-10 | Chartered Semiconductor Manufacturing, Ltd. | Method to encapsulate copper plug for interconnect metallization |
US6249055B1 (en) | 1998-02-03 | 2001-06-19 | Advanced Micro Devices, Inc. | Self-encapsulated copper metallization |
US6268291B1 (en) * | 1995-12-29 | 2001-07-31 | International Business Machines Corporation | Method for forming electromigration-resistant structures by doping |
US6303498B1 (en) | 1999-08-20 | 2001-10-16 | Taiwan Semiconductor Manufacturing Company | Method for preventing seed layer oxidation for high aspect gap fill |
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2000
- 2000-08-18 US US09/642,140 patent/US6551872B1/en not_active Ceased
-
2005
- 2005-04-22 US US11/113,454 patent/USRE41538E1/en not_active Expired - Lifetime
Patent Citations (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4233067A (en) | 1978-01-19 | 1980-11-11 | Sumitomo Electric Industries, Ltd. | Soft copper alloy conductors |
JPS60110868A (en) | 1983-11-18 | 1985-06-17 | Mitsubishi Metal Corp | Surface hardened au alloy member |
US4592891A (en) | 1984-06-14 | 1986-06-03 | Nippon Mining Co., Ltd. | Corrosion-resistant copper alloy |
US4750029A (en) | 1984-08-31 | 1988-06-07 | Mitsubishi Shindoh Co., Ltd. | Copper base lead material for leads of semiconductor devices |
US4732731A (en) | 1985-08-29 | 1988-03-22 | The Furukawa Electric Co., Ltd. | Copper alloy for electronic instruments and method of manufacturing the same |
JPS62127438A (en) | 1985-11-26 | 1987-06-09 | Nippon Mining Co Ltd | Bonding wire for semiconductor device |
JPS62133050A (en) | 1985-12-03 | 1987-06-16 | Nippon Mining Co Ltd | Manufacture of high strength and high conductivity copper-base alloy |
US4908275A (en) | 1987-03-04 | 1990-03-13 | Nippon Mining Co., Ltd. | Film carrier and method of manufacturing same |
US4986856A (en) | 1987-06-25 | 1991-01-22 | The Furukawa Electric Co., Ltd. | Fine copper wire for electronic instruments and method of manufacturing the same |
JPS6428337A (en) | 1987-07-24 | 1989-01-30 | Furukawa Electric Co Ltd | High-strength and high-conductivity copper alloy |
JPS6456842A (en) | 1987-08-27 | 1989-03-03 | Nippon Mining Co | Copper alloy foil for flexible circuit board |
JPH02230756A (en) | 1989-03-03 | 1990-09-13 | Seiko Epson Corp | Copper electrode wiring material |
US5143867A (en) | 1991-02-13 | 1992-09-01 | International Business Machines Corporation | Method for depositing interconnection metallurgy using low temperature alloy processes |
US5130274A (en) | 1991-04-05 | 1992-07-14 | International Business Machines Corporation | Copper alloy metallurgies for VLSI interconnection structures |
US6147402A (en) | 1992-02-26 | 2000-11-14 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5719447A (en) | 1993-06-03 | 1998-02-17 | Intel Corporation | Metal alloy interconnections for integrated circuits |
US5624506A (en) | 1993-09-30 | 1997-04-29 | Kabushiki Kaisha Kobe Seiko Sho | Copper alloy for use in electrical and electronic parts |
US5592024A (en) | 1993-10-29 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device having a wiring layer with a barrier layer |
US5694184A (en) | 1995-08-01 | 1997-12-02 | Kabushiki Kaisha Toshiba | Liquid crystal display device |
JPH09157775A (en) | 1995-09-27 | 1997-06-17 | Nikko Kinzoku Kk | Copper alloy for electronic equipment |
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