USRE41653E1 - Method of forming metal wiring of semiconductor device - Google Patents

Method of forming metal wiring of semiconductor device Download PDF

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USRE41653E1
USRE41653E1 US12/284,848 US28484808A USRE41653E US RE41653 E1 USRE41653 E1 US RE41653E1 US 28484808 A US28484808 A US 28484808A US RE41653 E USRE41653 E US RE41653E
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metal wiring
film
forming
interlayer insulating
insulating film
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Dong Joon Kim
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Sk Keyfoundry Inc
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MagnaChip Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • E—FIXED CONSTRUCTIONS
    • E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
    • E02B—HYDRAULIC ENGINEERING
    • E02B3/00—Engineering works in connection with control or use of streams, rivers, coasts, or other marine sites; Sealings or joints for engineering works in general
    • E02B3/04—Structures or apparatus for, or methods of, protecting banks, coasts, or harbours
    • E02B3/12—Revetment of banks, dams, watercourses, or the like, e.g. the sea-floor
    • E02B3/14—Preformed blocks or slabs for forming essentially continuous surfaces; Arrangements thereof
    • A—HUMAN NECESSITIES
    • A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
    • A01K—ANIMAL HUSBANDRY; CARE OF BIRDS, FISHES, INSECTS; FISHING; REARING OR BREEDING ANIMALS, NOT OTHERWISE PROVIDED FOR; NEW BREEDS OF ANIMALS
    • A01K61/00—Culture of aquatic animals
    • A01K61/10—Culture of aquatic animals of fish
    • E—FIXED CONSTRUCTIONS
    • E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
    • E02B—HYDRAULIC ENGINEERING
    • E02B3/00—Engineering works in connection with control or use of streams, rivers, coasts, or other marine sites; Sealings or joints for engineering works in general
    • E02B3/04—Structures or apparatus for, or methods of, protecting banks, coasts, or harbours
    • E02B3/12—Revetment of banks, dams, watercourses, or the like, e.g. the sea-floor
    • E02B3/129—Polyhedrons, tetrapods or similar bodies, whether or not threaded on strings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Definitions

  • the present invention relates to a method of forming a metal wiring of a semiconductor device, and more specifically, to a method of forming a metal wiring of a semiconductor device, which is formed by a dual damascene process.
  • an anti-diffusion film formation process serves to form an anti-diffusion film in a via hole and on a sidewall of a metal wiring trench, thus preventing diffusion of a metal material, which will be formed in a subsequent process.
  • the anti-diffusion film is usually formed by a sputtering process employing high-density metal plasma. In this time, deposited metal ions are deposited on the via hole and the metal wiring trench with straightness. Thus, there is a problem in that the step coverage of the anti-diffusion film is degraded as a design rule of a device reduces.
  • the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of forming a metal wiring of a semiconductor device in which the step coverage of an anti-diffusion film, which is deposited on a via hole and a metal wiring trench, can be improved.
  • a method of forming a metal wiring of a semiconductor device comprising the steps of: sequentially forming a first anti-diffusion film, a second interlayer insulating film, a third interlayer insulating film and a capping film on a first interlayer insulating film in which a first metal wiring is formed, patterning the capping film, the third interlayer insulating film, the second interlayer insulating film and the first anti-diffusion film so that the first metal wiring is exposed, thus forming a via hole, patterning the capping film and the third interlayer insulating film so that a given surface of the second interlayer insulating film is exposed on the result in which the via hole is formed, thus forming a metal wiring trench, forming a second anti-diffusion film in the via hole and the metal wiring trench, and sequentially forming copper seed layers in the via hole and the metal wiring trench in which the second anti-diffusion film is formed, and then forming
  • the second anti-diffusion film is formed through a three-step process.
  • the three-step process preferably includes sequentially performing an ionized sputtering process, a high pressure sputtering process and a bias sputtering process.
  • the ionized sputtering process is performed by applying a low pressure of 3 Torr or less, high power of 5 kW or more, and high magnetic field.
  • the high pressure sputtering process is performed by applying a high pressure of 3 Torr or more, lower power of 5 kW or less, and no magnetic field.
  • the bias sputtering process is performed under the condition in which a low pressure of 3 Torr or less is applied, RF of about 250 to 500 W is applied to the substrate, and remote plasma in which argon (Ar) ions are supplied is used.
  • FIGS. 1 to 3 are cross-sectional views for explaining a method of forming a metal wiring of a semiconductor device according to the present invention.
  • FIGS. 1 to 3 are cross-sectional views for explaining a method of forming a metal wiring of a semiconductor device according to the present invention.
  • a first anti-diffusion film 14 a second interlayer insulating film 16 made of a low dielectric film, a third interlayer insulating film 18 and a capping film 20 are sequentially formed on a first interlayer insulating film 10 in which a first metal wiring 12 formed using a material such as copper is formed.
  • a first photoresist pattern (not shown) for defining a via hole is formed on the capping film 20 .
  • the capping film 20 , the third interlayer insulating film 18 , the second interlayer insulating film 16 and the first anti-diffusion film 14 are etched using the pattern as an etch mask, thus forming a via hole VH.
  • a second photoresist pattern (not shown) for defining a trench pattern is formed.
  • the capping film 20 and the third interlayer insulating film 18 are then etched by using the pattern as an etch mask, thus forming a trench pattern MT.
  • the cleaning process is a process of stripping the metal oxide film formed in the exposed via hole or the etch residues generated during the process. It can be performed by using a sputtering etch process or a receive cleaning process.
  • a second anti-diffusion film 24 is formed on the resulting entire surface from which the metal oxide film 22 and the etch residues are removed, including the via hole and the metal wiring trench.
  • the second anti-diffusion film 24 can be formed through a three-step sputtering process; an ionized sputtering process, a high pressure sputtering process and a bias sputtering process.
  • the ionized sputtering process being the first sputtering process
  • high power and strong magnetic field are applied to a target so that a metal is ionized, and straightness is then increased with magnetic field, thus forming a second-1 anti-diffusion film.
  • the top of a metal wiring trench MT and the bottom of a via hole VH are deposited thickly, and the sidewalls of the metal wiring trench and the via hole VH are relatively thinly deposited.
  • the first sputtering process is performed by applying a low pressure ( ⁇ 3 Torr), high power (>5 kW) and strong magnetic field.
  • a second-2 anti-diffusion film is formed on the second-1 anti-diffusion film by applying low power to a target on which the process will be performed and low magnetic field to a chamber so that a metal is not ionized but has a shape of a nuclear particle, unlike the ionized process of the first sputtering process.
  • the second-2 anti-diffusion film does not reach the bottom of the via hole, but is usually deposited on a top corner and a sidewall of the metal wiring trench. Accordingly, deposition at the sidewall, which falls short in the first sputtering process, can be secured.
  • lots of a metal which is used to deposit the anti-diffusion film, is deposited on the top corner as well as the sidewall of the metal wiring trench.
  • the second sputtering process is performed by applying a high pressure (>3 Torr), low power ( ⁇ 5 kW) and no magnetic field.
  • the top corner of the metal wiring trench is much etched than other portion in a second sputtering process by means of a 2D effect.
  • the metal which is deposited a lot, can be removed in a second sputtering etch process. (Overhang of a pattern can be reduced).
  • the anti-diffusion film at the bottom of the via hole is also removed by way of a self-bias that is generated in a substrate.
  • a thickness of the anti-diffusion film at the via bottom can be reduced, but also a step coverage characteristic of the via bottom, which is weak because the anti-diffusion film re-sputtered at the via bottom is deposited on the sidewall of the via bottom, can be compensated for.
  • the third sputtering process is performed by applying RF of about 250 to 500 W to the substrate at a low pressure ( ⁇ 3 Torr). This process is performed by using remote plasma into which an argon (Ar) ion is supplied.
  • a copper seed layer (not shown) is formed on the resulting entire surface.
  • An electroplating process is then performed to form a copper layer in the via hole VH and the trench pattern MT.
  • a polishing process such as CMP (Chemical Mechanical Polishing) is performed on the resulting surface until the second anti-diffusion film 24 is exposed. Thereby, formation of a via plug V and a metal wiring M is completed.
  • an anti-diffusion film is formed through a three-step sputtering process. Accordingly, a sidewall coverage of the anti-diffusion film can be secured.
  • an interfacial phenomenon reduction in a wetting characteristic of an anti-diffusion film at the interface
  • a high pressure sputtering process being a second sputtering process
  • a thickness of an anti-diffusion film at a via bottom can be reduced due to a bias sputtering process being a third sputtering process. Therefore, contact resistance can be reduced.
  • a metal seed layer deposition process as well as an anti-diffusion film process are employed, continuity of a metal seed layer at a via bottom can be improved, and a void phenomenon, which can occur in a subsequent EP process as a design rule of the device rapidly decreases, can be thus reduced. Accordingly, reliability of a device can be improved.

Abstract

Disclosed herein is a method of forming a metal wiring of a semiconductor device. A method of forming a metal wiring of a semiconductor device comprises the steps of sequentially forming a first anti-diffusion film, a second interlayer insulating film, a third interlayer insulating film and a capping film on a first interlayer insulating film in which a first metal wiring is formed, patterning the capping film, the third interlayer insulating film, the second interlayer insulating film and the first anti-diffusion film so that the first metal wiring is exposed, thus forming a via hole, patterning the capping film and the third interlayer insulating film so that a given surface of the second interlayer insulating film is exposed on the result in which the via hole is formed, thus forming a metal wiring trench, forming a second anti-diffusion film in the via hole and the metal wiring trench, and sequentially forming copper seed layers in the via hole and the metal wiring trench in which the second anti-diffusion film is formed, and then forming a copper layer by means of an electroplating process, thus forming a via and a metal wiring.

Description

BACKGROUND
1. Field of the Invention
The present invention relates to a method of forming a metal wiring of a semiconductor device, and more specifically, to a method of forming a metal wiring of a semiconductor device, which is formed by a dual damascene process.
2. Discussion of Related Art
Generally, upon formation process of a metal wiring of a semiconductor device, an anti-diffusion film formation process serves to form an anti-diffusion film in a via hole and on a sidewall of a metal wiring trench, thus preventing diffusion of a metal material, which will be formed in a subsequent process.
However, the anti-diffusion film is usually formed by a sputtering process employing high-density metal plasma. In this time, deposited metal ions are deposited on the via hole and the metal wiring trench with straightness. Thus, there is a problem in that the step coverage of the anti-diffusion film is degraded as a design rule of a device reduces.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of forming a metal wiring of a semiconductor device in which the step coverage of an anti-diffusion film, which is deposited on a via hole and a metal wiring trench, can be improved.
In order to achieve the above object, according to the present invention, there is provided a method of forming a metal wiring of a semiconductor device, comprising the steps of: sequentially forming a first anti-diffusion film, a second interlayer insulating film, a third interlayer insulating film and a capping film on a first interlayer insulating film in which a first metal wiring is formed, patterning the capping film, the third interlayer insulating film, the second interlayer insulating film and the first anti-diffusion film so that the first metal wiring is exposed, thus forming a via hole, patterning the capping film and the third interlayer insulating film so that a given surface of the second interlayer insulating film is exposed on the result in which the via hole is formed, thus forming a metal wiring trench, forming a second anti-diffusion film in the via hole and the metal wiring trench, and sequentially forming copper seed layers in the via hole and the metal wiring trench in which the second anti-diffusion film is formed, and then forming a copper layer by means of an electroplating process, thus forming a via and a metal wiring.
Preferably, the second anti-diffusion film is formed through a three-step process.
The three-step process preferably includes sequentially performing an ionized sputtering process, a high pressure sputtering process and a bias sputtering process.
It is preferred that the ionized sputtering process is performed by applying a low pressure of 3 Torr or less, high power of 5 kW or more, and high magnetic field.
It is preferable that the high pressure sputtering process is performed by applying a high pressure of 3 Torr or more, lower power of 5 kW or less, and no magnetic field.
Preferably, the bias sputtering process is performed under the condition in which a low pressure of 3 Torr or less is applied, RF of about 250 to 500 W is applied to the substrate, and remote plasma in which argon (Ar) ions are supplied is used.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 to 3 are cross-sectional views for explaining a method of forming a metal wiring of a semiconductor device according to the present invention.
 DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Now, the preferred embodiments according to the present invention will be described with reference to the accompanying drawings. Since preferred embodiments are provided for the purpose that the ordinary skilled in the art are able to understand the present invention, they may be modified in various manners and the scope of the present invention is not limited by the preferred embodiments described later. Further, in the drawing, the thickness and size of each layer are exaggerated for explanation's convenience and clarity. Like reference numerals are used to identify the same or similar parts. Meanwhile, in case where it is described that one film is “on” the other film or a semiconductor substrate, the one film may directly contact the other film or the semiconductor substrate. Or, a third film may be intervened between the one film and the other film or the semiconductor substrate.
FIGS. 1 to 3 are cross-sectional views for explaining a method of forming a metal wiring of a semiconductor device according to the present invention.
Referring to FIG. 1, a first anti-diffusion film 14, a second interlayer insulating film 16 made of a low dielectric film, a third interlayer insulating film 18 and a capping film 20 are sequentially formed on a first interlayer insulating film 10 in which a first metal wiring 12 formed using a material such as copper is formed.
A first photoresist pattern (not shown) for defining a via hole is formed on the capping film 20. The capping film 20, the third interlayer insulating film 18, the second interlayer insulating film 16 and the first anti-diffusion film 14 are etched using the pattern as an etch mask, thus forming a via hole VH. After the first photoresist pattern (not shown) is stripped, a second photoresist pattern (not shown) for defining a trench pattern is formed. The capping film 20 and the third interlayer insulating film 18 are then etched by using the pattern as an etch mask, thus forming a trench pattern MT. In this time, byproducts, which are generated in the etch process for forming the via hole VH and the trench pattern MT, remain on the first metal wiring 12. Furthermore, as the metal surface reacts in the etch process, a metal oxide film 22 (where, as the first metal wiring is copper, a copper oxide film, i.e., CuO is formed). Since the metal oxide film and the polymeric residues degrade characteristics of the first metal wiring 12 and a second metal wiring, which will be formed through burial of the via hole and the trench pattern, they must be removed. Accordingly, a cleaning process is performed on the entire resulting surface.
The cleaning process is a process of stripping the metal oxide film formed in the exposed via hole or the etch residues generated during the process. It can be performed by using a sputtering etch process or a receive cleaning process.
Referring to FIG. 2, a second anti-diffusion film 24 is formed on the resulting entire surface from which the metal oxide film 22 and the etch residues are removed, including the via hole and the metal wiring trench.
The second anti-diffusion film 24 can be formed through a three-step sputtering process; an ionized sputtering process, a high pressure sputtering process and a bias sputtering process.
In the ionized sputtering process being the first sputtering process, high power and strong magnetic field are applied to a target so that a metal is ionized, and straightness is then increased with magnetic field, thus forming a second-1 anti-diffusion film. In this time, in the second-1 anti-diffusion film, the top of a metal wiring trench MT and the bottom of a via hole VH are deposited thickly, and the sidewalls of the metal wiring trench and the via hole VH are relatively thinly deposited.
Furthermore, the first sputtering process is performed by applying a low pressure (<3 Torr), high power (>5 kW) and strong magnetic field.
Thereafter, in the high pressure sputtering process being the second sputtering process, a second-2 anti-diffusion film is formed on the second-1 anti-diffusion film by applying low power to a target on which the process will be performed and low magnetic field to a chamber so that a metal is not ionized but has a shape of a nuclear particle, unlike the ionized process of the first sputtering process. In this time, the second-2 anti-diffusion film does not reach the bottom of the via hole, but is usually deposited on a top corner and a sidewall of the metal wiring trench. Accordingly, deposition at the sidewall, which falls short in the first sputtering process, can be secured. In this time, in the second sputtering process, lots of a metal, which is used to deposit the anti-diffusion film, is deposited on the top corner as well as the sidewall of the metal wiring trench.
Moreover, the second sputtering process is performed by applying a high pressure (>3 Torr), low power (<5 kW) and no magnetic field.
Meanwhile, in the bias sputtering process of the third sputtering process, the top corner of the metal wiring trench is much etched than other portion in a second sputtering process by means of a 2D effect. The metal, which is deposited a lot, can be removed in a second sputtering etch process. (Overhang of a pattern can be reduced). Furthermore, the anti-diffusion film at the bottom of the via hole is also removed by way of a self-bias that is generated in a substrate. Accordingly, not only a thickness of the anti-diffusion film at the via bottom can be reduced, but also a step coverage characteristic of the via bottom, which is weak because the anti-diffusion film re-sputtered at the via bottom is deposited on the sidewall of the via bottom, can be compensated for.
Furthermore, the third sputtering process is performed by applying RF of about 250 to 500 W to the substrate at a low pressure (<3 Torr). This process is performed by using remote plasma into which an argon (Ar) ion is supplied.
Referring to FIG. 3, a copper seed layer (not shown) is formed on the resulting entire surface. An electroplating process is then performed to form a copper layer in the via hole VH and the trench pattern MT. A polishing process such as CMP (Chemical Mechanical Polishing) is performed on the resulting surface until the second anti-diffusion film 24 is exposed. Thereby, formation of a via plug V and a metal wiring M is completed.
As described above, according to the present invention, an anti-diffusion film is formed through a three-step sputtering process. Accordingly, a sidewall coverage of the anti-diffusion film can be secured.
Furthermore, according to the present invention, an interfacial phenomenon (reduction in a wetting characteristic of an anti-diffusion film at the interface), which can occur in a sidewall because of a high pressure sputtering process being a second sputtering process, can be improved by means of a high pressure sputtering method. It is thus possible to improve reliability.
Furthermore, according to the present invention, a thickness of an anti-diffusion film at a via bottom can be reduced due to a bias sputtering process being a third sputtering process. Therefore, contact resistance can be reduced.
Furthermore, according to the present invention, if a metal seed layer deposition process as well as an anti-diffusion film process are employed, continuity of a metal seed layer at a via bottom can be improved, and a void phenomenon, which can occur in a subsequent EP process as a design rule of the device rapidly decreases, can be thus reduced. Accordingly, reliability of a device can be improved.
Although the foregoing description has been made with reference to the preferred embodiments, it is to be understood that changes and modifications of the present invention may be made by the ordinary skilled in the art without departing from the spirit and scope of the present invention and appended claims.

Claims (6)

1. A method of forming a metal wiring of a semiconductor device, comprising the steps of:
sequentially forming a first anti-diffusion film, a second interlayer insulating film, a third interlayer insulating film and a capping film on a first interlayer insulating film in which a first metal wiring is formed;
patterning the capping film, the third interlayer insulating film, the second interlayer insulating film and the first anti-diffusion film so that the first metal wiring is exposed, thus forming a via hole;
patterning the capping film and the third interlayer insulating film so that a given surface of the second interlayer insulating film is exposed on the result in which the via hole is formed, thus forming a metal wiring trench;
forming a second anti-diffusion film in the via hole and the metal wiring trench by sequentially performing an ionized sputtering process, a high pressure sputtering process and a bias sputtering process; and
sequentially forming copper seed layers in the via hole and the metal wiring trench in which the second anti-diffusion film is formed, and then forming a copper layer by means of an electroplating process, thus forming a via and a metal wiring.
2. The method as claimed in claim 1, wherein the ionized sputtering process is performed by applying a low pressure of 3 Torr or less, high power of 5 kW or more, and high magnetic field.
3. The method as claimed in claim 1, wherein the high pressure sputtering process is performed by applying a high pressure of 3 Torr or more, lower power of 5 kW or less, and no magnetic field.
4. The method as claimed in claim 1, wherein the bias sputtering process is performed under the condition in which a low pressure of 3 Torr or less is applied, RF of about 250 W to 500 W is applied to the substrate, and remote plasma in which argon (Ar) ions are supplied is used.
5. The method as claimed in claim 1, wherein the ionized sputtering process includes the steps of:
applying high power and strong magnetic field to a target to ionize a metal;
increasing straightness with the magnetic field; and
depositing a second anti-diffusion film on a top of the metal wiring trench and a bottom of the via hole relatively thickly, and on sidewalls of the metal wiring trench and the via hole relatively thinly.
6. The method as claimed in claim 1, wherein the high pressure sputtering process includes the steps of:
applying low power to a target on which the process will be performed and low magnetic field to a chamber; and
depositing a second anti-diffusion film on a top corner and a sidewall of the metal wiring trench.
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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895266A (en) 1996-02-26 1999-04-20 Applied Materials, Inc. Titanium nitride barrier layers
JPH11340226A (en) 1998-05-22 1999-12-10 Sony Corp Manufacture of semiconductor device
KR20000075302A (en) 1999-05-31 2000-12-15 김영환 Method for forming wiring using multi-step sputtering of aluminum in semiconductor device
JP2001524753A (en) 1997-11-26 2001-12-04 アプライド マテリアルズ インコーポレイテッド Damage-free coating engraving deposition method
US20020009873A1 (en) 2000-07-24 2002-01-24 Tatsuya Usami Semiconductor device and method of manufacturing the same
KR20030000823A (en) 2001-06-27 2003-01-06 주식회사 하이닉스반도체 Method for forming interconnect structures of semiconductor device
US6538324B1 (en) 1999-06-24 2003-03-25 Nec Corporation Multi-layered wiring layer and method of fabricating the same
US20040168908A1 (en) 2003-02-28 2004-09-02 Michael Friedemann Method of forming a conductive barrier layer having improved coverage within critical openings
US20040214430A1 (en) 2003-04-28 2004-10-28 Hartmut Ruelke Nitrogen-enriched low-k barrier layer for a copper metallization layer
US6815339B2 (en) 2002-06-29 2004-11-09 Hynix Semiconductor Inc. Method for forming copper metal line in semiconductor device
US20050194691A1 (en) 2004-03-08 2005-09-08 Fujitsu Limited Method of forming wiring structure and semiconductor device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895266A (en) 1996-02-26 1999-04-20 Applied Materials, Inc. Titanium nitride barrier layers
US20040171250A1 (en) 1997-11-26 2004-09-02 Tony Chiang Method of preventing diffusion of copper through a tantalum-comprising barrier layer
JP2001524753A (en) 1997-11-26 2001-12-04 アプライド マテリアルズ インコーポレイテッド Damage-free coating engraving deposition method
US20020029958A1 (en) 1997-11-26 2002-03-14 Applied Materials, Inc. Damage-free sculptured coating deposition
US6758947B2 (en) 1997-11-26 2004-07-06 Applied Materials, Inc. Damage-free sculptured coating deposition
US20050085068A1 (en) 1997-11-26 2005-04-21 Tony Chiang Method of depositing a metal seed layer on semiconductor substrates
JPH11340226A (en) 1998-05-22 1999-12-10 Sony Corp Manufacture of semiconductor device
KR20000075302A (en) 1999-05-31 2000-12-15 김영환 Method for forming wiring using multi-step sputtering of aluminum in semiconductor device
US6538324B1 (en) 1999-06-24 2003-03-25 Nec Corporation Multi-layered wiring layer and method of fabricating the same
US20020009873A1 (en) 2000-07-24 2002-01-24 Tatsuya Usami Semiconductor device and method of manufacturing the same
KR20030000823A (en) 2001-06-27 2003-01-06 주식회사 하이닉스반도체 Method for forming interconnect structures of semiconductor device
US6815339B2 (en) 2002-06-29 2004-11-09 Hynix Semiconductor Inc. Method for forming copper metal line in semiconductor device
US20040168908A1 (en) 2003-02-28 2004-09-02 Michael Friedemann Method of forming a conductive barrier layer having improved coverage within critical openings
US20040214430A1 (en) 2003-04-28 2004-10-28 Hartmut Ruelke Nitrogen-enriched low-k barrier layer for a copper metallization layer
US20050194691A1 (en) 2004-03-08 2005-09-08 Fujitsu Limited Method of forming wiring structure and semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Official action issued in corresponding Korean application No. 2004-21783 dated Apr. 26, 2006.

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KR100607809B1 (en) 2006-08-02
US20050221607A1 (en) 2005-10-06
CN1722405A (en) 2006-01-18
CN100533707C (en) 2009-08-26

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