USRE41691E1 - Method and apparatus for performing joint timing recovery of multiple received signals - Google Patents
Method and apparatus for performing joint timing recovery of multiple received signals Download PDFInfo
- Publication number
- USRE41691E1 USRE41691E1 US11/805,865 US80586507A USRE41691E US RE41691 E1 USRE41691 E1 US RE41691E1 US 80586507 A US80586507 A US 80586507A US RE41691 E USRE41691 E US RE41691E
- Authority
- US
- United States
- Prior art keywords
- sum
- signal
- nco
- adjusting
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
- H04L25/062—Setting decision thresholds using feedforward techniques only
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
- H04L25/063—Setting decision thresholds using feedback techniques only
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Radio Transmission System (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims (14)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/805,865 USRE41691E1 (en) | 2001-04-13 | 2007-05-23 | Method and apparatus for performing joint timing recovery of multiple received signals |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/835,030 US6947498B2 (en) | 2001-04-13 | 2001-04-13 | Method and apparatus for performing joint timing recovery of multiple received signals |
US11/805,865 USRE41691E1 (en) | 2001-04-13 | 2007-05-23 | Method and apparatus for performing joint timing recovery of multiple received signals |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/835,030 Reissue US6947498B2 (en) | 2001-04-13 | 2001-04-13 | Method and apparatus for performing joint timing recovery of multiple received signals |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE41691E1 true USRE41691E1 (en) | 2010-09-14 |
Family
ID=25268399
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/835,030 Ceased US6947498B2 (en) | 2001-04-13 | 2001-04-13 | Method and apparatus for performing joint timing recovery of multiple received signals |
US11/805,865 Expired - Lifetime USRE41691E1 (en) | 2001-04-13 | 2007-05-23 | Method and apparatus for performing joint timing recovery of multiple received signals |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/835,030 Ceased US6947498B2 (en) | 2001-04-13 | 2001-04-13 | Method and apparatus for performing joint timing recovery of multiple received signals |
Country Status (1)
Country | Link |
---|---|
US (2) | US6947498B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7257156B2 (en) * | 2001-12-06 | 2007-08-14 | Pulse˜Link, Inc. | Systems and methods for equalization of received signals in a wireless communication network |
US8045935B2 (en) | 2001-12-06 | 2011-10-25 | Pulse-Link, Inc. | High data rate transmitter and receiver |
US7317756B2 (en) | 2001-12-06 | 2008-01-08 | Pulse-Link, Inc. | Ultra-wideband communication apparatus and methods |
KR100462471B1 (en) * | 2002-09-05 | 2004-12-17 | 한국전자통신연구원 | Apparatus for compensating phase error of digital signal and method of the same |
CN101567687A (en) * | 2008-04-21 | 2009-10-28 | 扬智科技股份有限公司 | Signal generation circuit |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3555194A (en) * | 1967-11-17 | 1971-01-12 | Nippon Electric Co | Interstation synchronization apparatus |
US5321850A (en) * | 1991-10-09 | 1994-06-14 | Telefonaktiebolaget L M Ericsson | Diversity radio receiver automatic frequency control |
US6169907B1 (en) * | 1997-10-21 | 2001-01-02 | Interwave Communications International Ltd. | Power control of remote communication devices |
US6307413B1 (en) | 1999-12-23 | 2001-10-23 | Cypress Semiconductor Corp. | Reference-free clock generator and data recovery PLL |
US20020049936A1 (en) * | 2000-07-31 | 2002-04-25 | Vadim Gutnik | Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals |
US20020136342A1 (en) * | 2001-03-20 | 2002-09-26 | Gct Semiconductor, Inc. | Sample and hold type fractional-N frequency synthesezer |
US20030016087A1 (en) * | 2001-07-19 | 2003-01-23 | Matsushita Electric Industrial Co., Ltd. | Phase-locked loop circuit and data reproduction apparatus |
US20030085739A1 (en) * | 2001-11-07 | 2003-05-08 | Hirofumi Totsuka | Method of and apparatus for detecting difference between frequencies, and phase locked loop circuit |
-
2001
- 2001-04-13 US US09/835,030 patent/US6947498B2/en not_active Ceased
-
2007
- 2007-05-23 US US11/805,865 patent/USRE41691E1/en not_active Expired - Lifetime
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3555194A (en) * | 1967-11-17 | 1971-01-12 | Nippon Electric Co | Interstation synchronization apparatus |
US5321850A (en) * | 1991-10-09 | 1994-06-14 | Telefonaktiebolaget L M Ericsson | Diversity radio receiver automatic frequency control |
US6169907B1 (en) * | 1997-10-21 | 2001-01-02 | Interwave Communications International Ltd. | Power control of remote communication devices |
US6307413B1 (en) | 1999-12-23 | 2001-10-23 | Cypress Semiconductor Corp. | Reference-free clock generator and data recovery PLL |
US20020049936A1 (en) * | 2000-07-31 | 2002-04-25 | Vadim Gutnik | Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals |
US20020136342A1 (en) * | 2001-03-20 | 2002-09-26 | Gct Semiconductor, Inc. | Sample and hold type fractional-N frequency synthesezer |
US20030016087A1 (en) * | 2001-07-19 | 2003-01-23 | Matsushita Electric Industrial Co., Ltd. | Phase-locked loop circuit and data reproduction apparatus |
US20030085739A1 (en) * | 2001-11-07 | 2003-05-08 | Hirofumi Totsuka | Method of and apparatus for detecting difference between frequencies, and phase locked loop circuit |
Non-Patent Citations (5)
Title |
---|
Gutnik et al., "Clock Distribution Circuits and Methods of Operating Same That Use Multiple Clock Circuits Connected By Phase Detector Circuits To Generate and Synchronize Local Clock Signals". |
Lee et al., "Sample and Hold Type Fractional-N Frequency Synthesizer". |
Totsuke, "Method of and Apparatus for Detecting Difference Between Frequencies, And Phase Locked Loop Circuit". |
U.S. Appl. No. 60/221,709, filed on Jul 31, 2000. * |
Yamane et al., "Phase-Locked Loop Circuit and Data Reproduction Apparatus". |
Also Published As
Publication number | Publication date |
---|---|
US20020150177A1 (en) | 2002-10-17 |
US6947498B2 (en) | 2005-09-20 |
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Owner name: SARNOFF CORPORATION, NEW JERSEY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:REED, CHARLES, JR.;REEL/FRAME:019707/0718 Effective date: 20010412 Owner name: TRANSPACIFIC IP LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SARNOFF CORPORATION;REEL/FRAME:019707/0720 Effective date: 20060719 |
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