| Numéro de publication||USRE41849 E1|
|Type de publication||Octroi|
| Numéro de demande||US 11/159,427|
| Date de publication||19 oct. 2010|
| Date de dépôt||22 juin 2005|
| Date de priorité||22 déc. 1999|
|État de paiement des frais||Payé|
|Autre référence de publication||US6532509, US6587906, US20030105901|
| Numéro de publication||11159427, 159427, US RE41849 E1, US RE41849E1, US-E1-RE41849, USRE41849 E1, USRE41849E1|
| Inventeurs||Gilbert Wolrich, Debra Bernstein, Matthew J. Adiletta, William Wheeler|
| Cessionnaire d'origine||Intel Corporation|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Citations de brevets (132), Citations hors brevets (44), Référencé par (1), Classifications (8), Événements juridiques (5) |
|Liens externes: USPTO, Cession USPTO, Espacenet|
Parallel multi-threaded processing
US RE41849 E1
A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
1. A method for using a parallel, multi-threaded processor system comprising:
processing threads with a plurality of microengines, at least one microengine capable of processing at least two independent threads;
processing commands issued by the microengines using a plurality of system resource interface units that each include at least one commands queue; and
utilizing a global command arbiter including a pointer to store the identity of thea last agent that had a request granted to determine whether a particular microengine command request should be granted.
2. The method of claim 1 wherein each microengine utilizes a FIFO commands register.
3. The method of claim 1 wherein the system resource units include at least one of a core controller, a SDRAM controller, a SRAM controller, a PCI bus interface and an FBUS interface.
4. The method of claim 3 wherein in at least one of the SDRAM controller, the SRAM controller and the FBUS interface utilize three command queues.
5. The method of claim 3 wherein in at least one of the SDRAM controller and the SRAM controller utilize a high priority queue.
6. The method of claim 3 wherein the SRAM controller utilizes a read lock fail queue.
7. The method of claim 3 wherein the PCI bus interface utilizes a single command register.
8. The method of claim 1, wherein the agent comprises at least one of the following: a microengine and a microengine thread.
9. The method of claim 1, wherein the threads comprise at least one thread that operates on a packet.
10. A communications system comprising:
at least one Ethernet medium access controller (MAC);
a multithreaded processor, the processor including:
a plurality of microengines for processing a plurality of hardware threads;
at least one of an ASB translator, a PCI bus interface, a SDRAM controller, a SRAM controller, and an bus interface to the Ethernet MAC; and
a global command arbiter including a pointer to store the identity of thea last agent that had a request granted to determine whether a particular command request should be granted.
11. The system of claim 10 further comprising a FIFO commands register for each microengine.
12. The system of claim 10 wherein at least one of the SDRAM controller, the SRAM controller and the FBUS interface includes three command queues.
13. The system of claim 10 wherein at least one of the SDRAM controller and the SRAM controller includes a high priority queue.
14. The system of claim 10 wherein the SRAM controller includes a read lock fail queue.
15. The system of claim 10 wherein the PCI bus interface includes a single command register.
16. The methodsystem of claim 10, wherein the agent comprises at least one of the following: a microengine and a microengine thread.
17. The methodsystem of claim 10, wherein the threads comprise at least one thread that operates on a packet received via the at least one Ethernet MAC.
18. A method comprising:
identifying a last programmable unit of a plurality of multiple multi-threaded programmable units within an integrated circuit to have a request granted; and
based, at least in part, on the identifying of the last programmable unit of the plurality of multiple multi-threaded programmable units within the integrated circuit to have a request granted, selecting a different one of the multiple multi-threaded programmable units within the integrated circuit to have a next request granted.
19. The method of claim 18, wherein the plurality of multiple multi-threaded programmable units within the integrated circuit are associated with a sequence of the multiple multi-threaded programmable units within the integrated circuit; and wherein selecting the one of the multiple multi-threaded programmable units within the integrated circuit to have a next request granted comprises selecting a next one of the multiple multi-threaded programmable units within the integrated circuit in the sequence.
20. The method of claim 18
, further comprising:
selecting a memory access operation issued by the selected one of the multiple multi-threaded programmable units within the integrated circuit.
21. An integrated circuit, comprising:
multiple multi-threaded programmable units in the integrated circuit; and
logic, communicatively coupled to the multiple multi
-threaded programmable units, to:
identify a last programmable unit of the plurality of multiple multi-threaded programmable units within the integrated circuit to have a request granted; and
based, at least in part, on the identified last programmable unit of the plurality of multiple multi-threaded programmable units within the integrated circuit to have a request granted, select a one of the multiple multi-threaded programmable units within the integrated circuit to have a next request granted.
22. The integrated circuit of claim 21, wherein the plurality of multiple multi-threaded programmable units within the integrated circuit are associated with a sequence of the multiple multi-threaded programmable units; and wherein the logic to select the one of the multiple multi-threaded programmable units within the integrated circuit to have a next request granted comprises logic to select a next one of the multiple multi-threaded programmable units in the sequence.
23. The integrated circuit of claim 21, wherein the logic comprises an arbiter coupled to the multiple multi-threaded programmable units and to a memory controller to a memory shared by the multiple multi-threaded programmable units.
24. The integrated circuit of claim 21
, wherein the logic further comprises logic to:
select a memory access operation issued by the selected one of the multiple multi-threaded programmable units within the integrated circuit.
25. A method for using a parallel, multi-threaded processor system comprising:
processing threads with a plurality of microengines, at least one microengine capable of processing at least two independent threads;
processing commands issued by the microengines using a plurality of system resource interface units that each include at least one commands queue; and
storing an identity of a last agent that had a request granted to determine whether a particular microengine command request should be granted, wherein a pointer is included to store the identity.
26. The method of claim 25, wherein each microengine utilizes a FIFO commands register.
27. The method of claim 25, wherein the system resource units include at least one of a core controller, a SDRAM controller, a SRAM controller, a PCI bus interface and an FBUS interface.
28. The method of claim 27, wherein at least one of the SDRAM controller, the SRAM controller and the FBUS interface utilize three command queues.
29. The method of claim 27, wherein in at least one of the SDRAM controller and the SRAM controller utilize a high priority queue.
30. The method of claim 27, wherein the SRAM controller utilizes a read lock fail queue.
31. The method of claim 27, wherein the PCI bus interface utilizes a single command register.
32. The method of claim 25, wherein the agent comprises at least one of the following: a microengine and a microengine thread.
33. The method of claim 25, wherein the threads comprise at least one thread that operates on a packet.
34. A communications system comprising:
at least one Ethernet medium access controller (MAC);
a multithreaded processor, the processor including:
a plurality of microengines for processing a plurality of hardware threads;
at least one of an ASB translator, a PCI bus interface, a SDRAM controller, a SRAM controller, and an bus interface to the Ethernet MAC; and
a pointer to store an identity of a last agent that had a request granted, the system configured to determine whether a particular command request should be granted.
35. The system of claim 34 further comprising a FIFO commands register for each microengine.
36. The system of claim 34 wherein at least one of the SDRAM controller, the SRAM controller and the FBUS interface includes three command queues.
37. The system of claim 34 wherein at least one of the SDRAM controller and the SRAM controller includes a high priority queue.
38. The system of claim 34 wherein the SRAM controller includes a read lock fail queue.
39. The system of claim 34 wherein the PCI bus interface includes a single command register.
40. The system of claim 34, wherein the agent comprises at least one of the following: a microengine and a microengine thread.
41. The system of claim 34, wherein the threads comprise at least one thread that operates on a packet received via the at least one Ethernet MAC.
This application is a continuation of U.S. application Ser. No. 09/470,541 filed on Dec. 22, 1999, now U.S. Pat. No. 6,532,509.
BACKGROUND OF THE INVENTION
This invention relates to a protocol for providing parallel, multi-threaded processors with high bandwidth access to shared resources.
Parallel processing is an efficient form of computer information processing of concurrent events. Certain problems may be solved by applying parallel computer processing, which demands concurrent execution of many programs to do more than one thing at the same time. Unlike a serial paradigm where all tasks are performed sequentially at a single station, or a pipelined machine where tasks are performed at specialized stations, parallel processing requires that a plurality of stations have the capability to perform all tasks. In general, all or a plurality of the stations work simultaneously and independently on the same or common elements of a problem.
Types of computer processing include single instruction stream, single data stream, which is the conventional serial von Neumann computer that includes a single stream of instructions. A second processing type is the single instruction stream, multiple data streams process (SIMD). This processing scheme may include multiple arithmetic-logic processors and a single control processor. Each of the arithmetic-logic processors performs operations on the data in lock step and are synchronized by the control processor. A third type is multiple instruction streams, single data stream (MISD) processing which involves processing the same data stream flows through a linear array of processors executing different instruction streams. A fourth processing type is multiple instruction streams, multiple data streams (MIMD) processing which uses multiple processors, each executing its own instruction stream to process a data stream fed to each of the processors. MIMD processors may have several instruction processing units and therefore several data streams.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, a parallel, hardware-based, multi-threaded processor includes a global command arbiter for determining the allocation of access to system resources. The multi-threaded processor system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol based on the shared system resources and command type to grant or deny a microengine command request for a shared resource. The processor system may be advantageously realized on an integrated circuit chip with minimal wiring and buffer storage elements.
The technique according to the invention provides each microengine with fair access to the shared system resources based on command priority and resource utilization. Consequently, the microengines have high bandwidth access to the shared system resources.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a communication system employing a hardware-based multithreaded processor.
FIG. 2 is a simplified block diagram of a global arbitration system for a multithreaded process according to the invention.
FIGS. 3A and 3B illustrate a flow chart of an implementation of a global command arbitration process according to the invention.
FIG. 1 illustrates a communication system 10 that includes a parallel, hardware-based multithreaded processor 12. The system 10 is especially useful for tasks that can be broken into parallel subtasks or functions, and the hardware-based multithreaded processor 12 is particularly useful for tasks that are bandwidth oriented rather than latency oriented.
The hardware-based multithreaded processor 12 may be an integrated circuit, and may be coupled to a bus such as a PCI bus 14, a memory system 16 and a second bus 18. In the illustrated implementation, the hardware-based multi-threaded processor 12 has multiple microengines 22a to 22f that each includes multiple hardware-controlled threads that can be simultaneously active and that may independently work on a task. The multithreaded processor 12 also includes a central or core controller 20 that assists in loading microcode control for other resources and performs other general purpose computer-type functions such as handling protocols, handling exceptions, and providing extra support for packet processing, which may occur if the microengines pass the packets off for more detailed processing. In one embodiment, the core controller 20 is a Strong Arm® (Arm is a trademark of ARM Limited, United Kingdom) based architecture embedded general-purpose microprocessor, which includes an operating system. The operating system enables the core processor 20 to call functions to operate on the microengines 22a-22f. The core processor 20 can use any supported operating system but preferably utilizes a real time operating system. Suitable operating systems for a core processor implemented as a Strong Arm architecture microprocessor may include Microsoft NT real-time, VXWorks and μCUS, which is a freeware operating system available over the Internet.
The plurality of functional microengines 22a-22f each maintain a plurality of program counters in hardware, and maintain states associated with the program counters. Each of the six microengines 22a-22f is capable of processing four independent hardware threads. Such processing allows one thread to start executing just after another thread issues a memory reference and then waits until that reference completes before doing more work. This behavior is critical to maintaining efficient hardware execution of the microegines because memory latency may be significant. Stated differently, if only a single thread execution was supported, the microengines would sit idle for a significant number of cycles waiting for references to return and thereby reduce overall computational throughput. Multi-threaded execution allows the microengines to mask memory latency by performing useful independent work across several threads. Effectively, a corresponding plurality of sets of threads can be simultaneously active on each of the microengines 22a-22f while only one is actually operating at any one time.
The six microengines 22a-22f operate with shared system resources including the memory system 16, the PCI bus 14 and the FBUS 18. The memory system 16 may be accessed via a Synchronous Dynamic Random Access Memory (SDRAM) controller 26a and a Static Random Access Memory (SRAM) controller 26b. SDRAM memory 16a and SDRAM controller 26a may be typically used for processing large volumes of data or high bandwidth data, such as processing network payloads from network packets. The SRAM controller 26b and SRAM memory 16b may be used in a networking implementation for low latency, fast access tasks or low bandwidth data, such as accessing look-up tables, memory for the core processor 20, and so forth.
The six microengines 22a-22f access either the SDRAM 16a or SRAM 16b based on characteristics of the data. Low latency, low bandwidth data is stored in and fetched from SRAM 16b, whereas higher bandwidth data for which latency is not as important is stored in and fetched from SDRAM 16a. The microengines 22a-22f can execute memory reference instructions to either the SDRAM controller 26a or SRAM controller 26b.
Advantages of hardware multithreading can be explained in the context of SRAM or SDRAM memory accesses. For example, an SRAM access requested by a Thread_0 from a microengine will cause the SRAM controller 26b to initiate an access to the SRAM memory 16b. The SRAM controller 26b controls arbitration for the SRAM bus 15, accesses the SRAM 16b, fetches the data from the SRAM 16b, and returns data to a requesting microengine 22a-22b. During a SRAM access, if the microengine 22a had only a single thread that could operate, that microengine would be dormant until data was returned from the SRAM. By employing hardware context swapping within each of the microengines 22a-22f, another thread such as Thread_1 can function while the first thread, Thread_0, is awaiting the read data to return. Hardware context swapping enables other contexts with unique program counters to execute in that same microengine. Continuing the example, during execution Thread_1 may access the SDRAM memory 16a. While Thread_1 operates on the SDRAM unit, and Thread_0 is operating on the SRAM unit, a new thread such as Thread_2 can now operate in the microengine 22a. Thread_2 can operate for a certain amount of time until it needs to access memory or perform some other long latency operation, such as making an access to a bus interface. Therefore, the processor 12 can simultaneously perform a bus operation, SRAM operation and SDRAM operation with all being completed or operated upon by one microengine 22a, which microengine 22a has one more thread available to process more work in the data path.
The hardware context swapping also synchronizes completion of tasks. For example, it is possible that two threads could hit the same-shared resource such as the SRAM 16b. Each one of the separate functional units, such as the interface 28, the SRAM controller 26a, and the SDRAM controller 26b, reports back a flag signaling completion of an operation when a requested task from one of the microengine thread contexts is completed. When the flag is received by the microengine, the microengine can determine which thread to turn on.
The processor 12 includes a bus interface 28 that couples the processor to a second bus 18. In an implementation, an FBUS interface 28 couples the processor 12 to the so-called FBUS 18 (FIFO bus). The FBUS is a 64-bit wide FIFO bus, used to interface to Media Access Controller (MAC) devices. The FBUS interface 28 is responsible for controlling and interfacing the processor 12 to the FBUS 18.
The processor 12 also includes a PCI bus interface 24 that couples other system components that reside on the PCI bus 14 to the processor 12. The PCI bus interface 24 also provides a high-speed data path 24a to the SDRAM memory 16a. The data path 24a permits data to be moved quickly from the SDRAM 16a to the PCI bus 14, via direct memory access (DMA) transfers. The hardware based multithreaded processor 12 can employ a plurality of DMA channels so if one target of a DMA transfer is busy, another one of the DMA channels can take over the PCI bus 14 to deliver information to another target to maintain high processor 12 efficiency. The PCI bus interface 24 supports image transfers, target operations and master operations. Target operations are operations where slave devices on bus 14 access the SDRAM through reads and writes that are serviced as a slave to target operation. In master operations, the processor core 20 sends data directly to or receives data directly from the PCI interface 24.
Each of the functional units of the processor 12 are coupled to one or more internal buses. In an implementation, the internal buses are dual 32-bit buses (i.e., one bus for read and one for write). The multithreaded processor 12 also is constructed such that the sum of the bandwidths of the internal buses exceeds the bandwidth of external buses coupled to the processor 12. The internal core processor bus 32 may be an Advanced System Bus (ASB bus) that couples the processor core 20 to the memory controllers 26a and 26b and to an ASB translator 30. The ASB bus is a subset of an “AMBA” bus that is used with the Strong Arm processor core. The processor 12 also includes a private bus 34 that couples the microengine units to SRAM controller 26b, ASB translator 30 and FBUS interface 28. A memory bus 38 couples the SDRAM controller 26a, the PCI bus interface 24, the FBUS interface 28 and memory system 16 together, including Flash ROM 16c which is used for boot operations and the like.
The hardware-based multithreaded processor 12 may be utilized as a network processor. As a network processor, the hardware-based multithreaded processor 12 interfaces to network devices such as a media access controller (MAC) device such as a 10/100BaseT Octal MAC 13a or a Gigabit Ethernet device 13b. In general, the hardware-based multi-threaded processor 12 can interface to any type of communication device or interface that receives/sends large amount of data. The communication system 10 functioning in a networking application could receive a plurality of network packets from the devices 13a, 13b and process each of those packets independently in a parallel manner.
The processor 12 may also be utilized as a print engine for a postscript processor, as a processor for a storage subsystem such as RAID disk storage, or as a matching engine. In the securities industry for example, the advent of electronic trading requires the use of electronic matching engines to match orders between buyers and sellers. These and other parallel types of tasks can be accomplished on the system 10.
FIG. 2 shows a global arbitration system 40 for use with the multithreaded processor 12 of FIG. 1. A global command arbiter 42 is connected to each of the microengines 22a-22f, to the SDRAM controller 26a, to the SRAM controller 26b, to the interface 28 and to the PCI interface 24. The global command arbiter 42 functions to provide high bandwidth access to the shared system resources utilizing a minimal amount of buffer storage elements and minimal wiring. The global command arbiter provides each microengine 22a-22f with fair access to the common system resources of the SDRAM, SRAM, PCI interface registers and FBUS interface registers based on command priority and resource utilization, which is explained below.
In an implementation, each microengine 22a-22f has a two-command deep first-in, first-out (FIFO) register for issuing command requests for SDRAM 16a and SRAM 16b memory access, and for issuing command requests for access to registers in the PCI interface 24 and FBUS interface 28. The SDRAM controller 26a queues commands from the microengines in one of four FIFO command queue structures: an eight-entry high-priority queue 44, a sixteen-entry odd bank queue 46, a sixteen-entry even bank queue 48, and a twenty-four entry maintain order queue 50. A single physical random access memory (RAM) structure with four input pointers and four output pointers may be used to implement the SDRAM queues 44, 46, 48, 50. A reference request from a microengine may include a bit set called the “optimized MEM bit” which will be sorted into either the odd bank queue 46 or the even bank queue 48. If the memory reference request does not have a memory optimization bit set, the default will be to go into the order queue 50. The order queue 50 maintains the order of reference requests from the microengines 22a-22f. With a series of odd and even banks references it may be required that a signal is returned to both the odd and even banks. If the microengine 22f sorts the memory references into odd bank and even bank references and one of the banks, for example the even bank, is drained of memory references before the odd bank but the signal is asserted on the last even reference, the SDRAM controller 26a could conceivably signal back to a microengine that the memory request had completed, even though the odd bank reference had not been serviced. This occurrence could cause a coherency problem. The situation is avoided by providing the order queue 50 which permits a microengine to have multiple memory references outstanding, of which only its last memory reference needs to signal a completion.
The SDRAM controller 26a also included a high priority queue 44. If an incoming memory reference from one of the microengines goes directly to the high priority queue then it is operated upon at a higher priority than other memory references in the other queues.
A feature of the SDRAM controller 26a is that when a memory reference is stored in the queues, in addition to the optimized MEM bit that may be set, a “chaining bit” may be set to require special handling of contiguous memory references. A microengine context may issue chained memory references when the second and/or third reference of the chain must be scheduled by the SDRAM controller 26a immediately after the initial chained memory request. The global command arbiter 42 must ensure that chained references are delivered to consecutive locations of the same SDRAM controller queue.
The SRAM controller 26b also has four command queues: an eight-entry high priority queue 62, a sixteen-entry read queue 64, a sixteen-entry write order queue 66 and a twenty-four entry read-lock fail queue 68. A single physical RAM structure may be used to implement the four queues. The SRAM controller 26b is optimized based on the type of memory operation; i.e., a read or a write operation, and the predominant function that the SRAM performs is read operations.
The read lock fail queue 68 is used to hold read memory reference requests that fail because of a lock existing on a portion of memory. That is, one of the microengines issues a memory request that has a read lock request that is processed in an address and control queue. The memory request will operate on either the write order queue 66 or the read queue 64 and will recognize it as a read lock request. The SRAM controller 26b will access a lock lookup device to determine whether this memory location is already locked. If this memory location is locked from any prior read lock request, then this memory lock request will fail and will be stored in the read lock fail queue 68. If it is unlocked or if the lock lookup device shows no lock on that address, then the address of that memory reference will be used by the SRAM interface 26b to perform a traditional SRAM address read/write request to SRAM memory 16b. A command controller and address generator will also enter the lock into the lock look up device so that subsequent read lock requests will find the memory location locked. A memory location is unlocked by clearing a valid bit in a content addressable memory (CAM) of the SRAM controller. After an unlock, the read lock fail queue 68 becomes the highest priority queue giving all queued read lock misses a chance to issue a memory lock request. The read-lock miss queue is loaded by the SRAM controller itself and not directly from a microengine output buffer. The global arbiter 42 ensures that a command from a microengine to a SRAM queue is not selected on the same cycle that the SRAM controller must write a read-lock miss entry.
The FBUS interface 28 includes three command queues: an eight-entry push queue 72, an eight-entry pull queue 74 and an eight-entry hash queue 76. The pull queue is used when data is moved from a microengine to an FBUS interface resource, the push queue is used for reading data from the FBUS interface to a microengine, and the hash queue is used for sending from one to three hash arguments to a polynomial hash unit within the FBUS interface and for getting the hash result returned. The FBUS interface 28 in a network application can perform header processing of incoming packets from the FBUS 18. A key function performed by the FBUS interface 28 is extraction of packet headers, and a hashed lookup of microprogrammable source/destination/protocol in SRAM memory 16b. If the hash does not successfully resolve, then the packet header is subjected to more sophisticated processing.
The PCI bus interface 24 includes a single, two-entry direct memory access (DMA) command register 78. The DMA register provides a completion signal to the initiating microengine thread.
The global command arbiter 42 operates to select commands from the two-deep output command queues of each microengine for transmission to a destination queue in one of the functional units. The functional units include the core controller 20, the PCI interface 24, the SDRAM controller 26a, the SRAM controller 26b, the FBUS interface 28 and the microengines 22a to 22f. Each microengine request to the global command arbiter 42 is a three-bit encoded field that specifies the command type and destination. Each microengine global command arbiter request is serviced with the following priority:
||1. SDRAM chained commands
||5. PCI bus
The global arbiter maintains a pointer that indicates the last microengine request granted. If more than one request is present at the same priority, the global command arbiter selects the next higher numbered microengine (with a wrap-around feature). For example, the microengines 22a to 22f may be numbered from 1 to 6 in an implementation so that if a request from microengine 6 was the last one granted, then when priority is not an issue a request from microengine 1 is next up for consideration.
The three SRAM controller command queues 62, 64 and 66 are loaded directly from microengine commands. Since an SRAM command could be granted every cycle, it is possible that up to 6 additional SRAM commands will be granted and are in the pipeline, all of which could be destined for the same SRAM queue before a signal indicating that the queue is full is received by the global command arbiter. Thus, the SRAM controller asserts an SRAM_queue_full signal to the global command arbiter 42 if there is less than seven (7) empty entries in any SRAM command queue loaded from the microengines. For example, if the high priority queue has two entries filled then the SRAM_queue_full signal is asserted (because eight entries minus two entries is six). Similarly, if the read queue or the order queue contains ten entries then the SRAM_queue_full signal is asserted. This protocol is followed because a six cycle minimum latency exists from the assertion of a command request from a microengine and the command actually being stored in a destination queue.
The following diagram illustrates the timing of a request for a command destined for a queue in a system resource:
|1 ||2 ||3 ||4 ||5 ||6 ||7 ||8 ||9 |
|Req ||arb ||gat ||bus ||cmd ||rcv ||full ||arb ||NOGNT |
| ||req ||arb ||gnt ||bus ||cmd ||rcv ||full ||arb |
| || ||req ||arb ||gnt ||bus ||cmd ||rcv ||full |
| || || ||req ||arb ||gat ||bus ||cmd ||rcv |
| || || || ||req ||arb ||gnt ||bus ||cmd |
| || || || || ||req ||arb ||gnt ||bus |
| || || || || || ||req ||arb ||NOGNT |
Where: req=bus request from the microengine;
- arb=arbitrate requests;
- gnt=drive grant to appropriate microengine;
- bus=enable tri-state bus driver;
- cmd=drive command onto fx_cmd_bus;
- rcv=receiving box queues command;
- full=full_status_que signal driven if necessary;
- nognt=a grant is not sent to queues that sent “full” by cycle 7.
Referring to the above timing diagram, in the first cycle, a request is sent to the global command arbiter. In cycle two, arbitration is performed and in cycle three the request is granted to the requesting microengine. In cycle four, a bus is enabled and in cycle five the command is driven onto the bus. In cycle six the receiving unit (SDRAM controller, SRAM controller, PCI bus interface or FBUS interface) queues the command. In cycle seven a full_status_que command is driven if necessary (e.g. that queue contains less than a minimum number of available entry spaces). In cycle eight, the global command arbiter is deciding whether another request should be granted to that system resource, but sees that the full_status_queue signal was generated. The arbiter then acts to deny requests (nognt) to the queue which sent a full signal by the seventh cycle.
The FBUS interface 28 has 3 command queues (pull, hash, push) which all contain eight (8) entries. Commands to the FBUS interface are not granted in consecutive cycles. Thus, when any of the 3 FBUS interface queues reaches four (4) entries (instead of the two discussed above for an eight entry queue) a FBUS_queue_full signal is sent to the global command arbiter since only a maximum of 3 commands can be in transit to the FBUS interface queues prior to the global arbiter detecting FBUS_queue_full.
The SDRAM controller 26a has 4 command queues (high=8, even=16, odd=16, order=24). The threshold for asserting SDRAM_queue_full is the same as for the SRAM, i.e. less than 7 entries available in any queue. However, commands to the SDRAM controller are not granted on consecutive cycles. This insures queue entry space for any SDRAM chained commands from a particular microengine, which must be granted, even after SDRAM_queue_full asserts. It is necessary to always transfer SDRAM chained commands to avoid a live-lock condition, in which the SDRAM controller is waiting for the chained command in one queue while the command is “stuck” in a microengine because the global arbiter is no longer granting SDRAM commands since a different SDRAM queue is “full”. A limit is placed on the chain length of SDRAM commands to three as a coding restriction. In addition, when a chained SDRAM command is granted to a microengine, the next SDRAM command to be granted must also come from the same microengine so that the paired commands arrive in the selected SDRAM queue contiguously.
The restrictions of not sending commands to the FBUS on consecutive cycles, and not sending commands to the SDRAM on consecutive cycles do not degrade system performance since each command requires many cycles to actually execute. The restriction is not placed on SRAM commands since the SRAM queue sizing is more than adequate, and more SRAM references requiring fewer cycles with lower latency are issued in most applications.
FIGS. 3A and 3B illustrate an implementation of a global command arbiter protocol process 100. The global command arbiter reviews 102 the command requests in the FIFO registers of the microengines 22a-22f. If all of the requests have the same priority 104, a pointer is checked 106 to determine the identity of the last microengine that had a request granted, and then the request of the next higher microengine is considered. Before granting the command request, the arbiter checks 108 to see if a queue_full_signal has been asserted. If so, the command request is denied 110 and the pointer is incremented 111 so that the next microengine's request will be considered. However, if no queue_full_signal has been asserted, then the command request is granted 112 and the flow returns to 102.
Referring again to step 104 of FIG. 3A, if the command requests in the microengines 22a to 22f have different priorities, then the global command arbiter checks 114 to see if a SDRAM request with a chained bit set has been granted previously. If so, then the SDRAM request from the same microengine that sent the previous SDRAM request with a chained bit is granted 116. Next, the SDRAM queues are checked 118 to determine if any contain less than “N” empty entries, where N is equal to the number of microengines plus one. In the implementation described above, the SDRAM_queue_full signal will be asserted 120 if any SDRAM queue contains less than seven (7) empty entries and then the flow returns to 102. If checking the queues 118 determines that the SDRAM queues have space for seven or more entries, then the flow returns to 102.
If there was no history of an SDRAM command request with a chained bit set 114, the global command arbiter determines 122 if there is a SRAM command request. If there is a SRAM request, the SRAM queues are checked 124 to see if any SRAM queue contains less than N empty entries. If so, then a SRAM_queue_full signal is asserted 126, the command request is denied and the flow moves to 134 where the arbiter determines if a SDRAM request has been made. However, if the answer 124 is no, then the arbiter checks 128 to see if the SRAM controller 26b needs to write a read_lock_miss entry. If so, then the command request is denied in step 130 and the flow moves to 134; if not, then the command request is granted 132 and the flow returns to 102.
If the answer was no at 122, then the arbiter checks 134 (see FIG. 3B) to see if a SDRAM request is being made. If so, the arbiter determines 136 if the last granted request was also a SDRAM command request. If it was, then the request is denied 138 and the flow goes to 146 where the arbiter determines if an FBUS command request has been made. Commands are not granted to the SDRAM controller in consecutive cycles to ensure that there is adequate queue entry space for a SDRAM chained command which is always granted when it occurs (even after a SDRAM_queue_full signal has been asserted). If the last granted command request was not an SDRAM command the SDRAM queues are checked 140 to see if any contains less than N entries. If so, then an SDRAM_queue_full signal is asserted 142, access is denied 138 and the flow moves to 146. If the SDRAM queues have adequate entry space, then the command request is granted 144 and the flow returns to 102.
If a SDRAM request is not being made 134, then the arbiter checks 146 to see if an FBUS command request has been made. If so, the arbiter checks 148 to see if the last granted request was a FBUS request. If so, then the request is denied 150 and the flow moves to 160 where the arbiter determines if a PCI command request has been made. Command requests to the FBUS are not granted in consecutive cycles to improve processing efficiency of the system. If the last granted request was not an FBUS command request 148, then the FBUS queues are checked 152 to see if any contain less than “F” empty entries. For the example discussed above where there are six microengines and each of the FBUS command queues (pull, hash, push) contains eight entries, F equals five (5) since only a maximum of three (3) commands can be in transit to the FBI queues. Thus, if four or fewer entries are available in any FBUS queue, then the FBUS_queue_full signal is asserted 154, the command is denied 150 and the flow moves to 160. However, if the FBUS queues have adequate space, the request is granted 156 and the flow returns to 102.
If an FBUS request is not made 146, a PCI command request has been asserted 160. Direct memory access is granted and a completion signal is sent, then the flow returns to 102.
It is to be understood that while implementations of the invention have been described, the foregoing description is intended to illustrate and not limit the invention, which is defined by the scope of the appended claims. For example, the flow chart depicted in FIGS. 3A and 3B could be modified to accommodate more, less or different system resources. Other aspects, advantages, and modifications are within the scope of the following claims.
| Brevet cité|| Date de dépôt|| Date de publication|| Déposant|| Titre|
|US3373408||16 avr. 1965||12 mars 1968||Rca Corp||Computer capable of switching between programs without storage and retrieval of the contents of operation registers|
|US3478322||23 mai 1967||11 nov. 1969||Ibm||Data processor employing electronically changeable control storage|
|US3623001||6 janv. 1970||23 nov. 1971||Peripheral Business Equipment||Input data preparation system|
|US3736566||18 août 1971||29 mai 1973||Ibm||Central processing unit with hardware controlled checkpoint and retry facilities|
|US3792441||8 mars 1972||12 févr. 1974||Burroughs Corp||Micro-program having an overlay micro-instruction|
|US3889243||18 oct. 1973||10 juin 1975||Ibm||Stack mechanism for a data processor|
|US3940745||26 avr. 1974||24 févr. 1976||Ing. C. Olivetti & C., S.P.A.||Data processing unit having a plurality of hardware circuits for processing data at different priority levels|
|US4016548||11 avr. 1975||5 avr. 1977||Sperry Rand Corporation||Communication multiplexer module|
|US4032899||19 janv. 1976||28 juin 1977||International Business Machines Corporation||Apparatus and method for switching of data|
|US4075691||6 nov. 1975||21 févr. 1978||Bunker Ramo Corporation||Communication control unit|
|US4130890||8 juin 1977||19 déc. 1978||Itt Industries, Inc.||Integrated DDC memory with bitwise erase|
|US4400770||10 nov. 1980||23 août 1983||International Business Machines Corporation||Cache synonym detection and handling means|
|US4514807||13 févr. 1984||30 avr. 1985||Tatsuo Nogi||Parallel computer|
|US4523272||8 avr. 1982||11 juin 1985||Hitachi, Ltd.||Bus selection control in a data transmission apparatus for a multiprocessor system|
|US4658351||9 oct. 1984||14 avr. 1987||Wang Laboratories, Inc.||Task control means for a multi-tasking data processing system|
|US4709347||17 déc. 1984||24 nov. 1987||Honeywell Inc.||Method and apparatus for synchronizing the timing subsystems of the physical modules of a local area network|
|US4745544||12 déc. 1985||17 mai 1988||Texas Instruments Incorporated||Master/slave sequencing processor with forced I/O|
|US4788640||17 janv. 1986||29 nov. 1988||Intel Corporation||Priority logic system|
|US4831358||21 déc. 1982||16 mai 1989||Texas Instruments Incorporated||Communications system employing control line minimization|
|US4858108||12 mars 1986||15 août 1989||Hitachi, Ltd.||Priority control architecture for input/output operation|
|US4866664||9 mars 1987||12 sept. 1989||Unisys Corporation||Intercomputer communication control apparatus & method|
|US4890218||10 août 1988||26 déc. 1989||Raytheon Company||Variable length instruction decoding apparatus having cross coupled first and second microengines|
|US4890222||24 juin 1987||26 déc. 1989||Honeywell Inc.||Apparatus for substantially syncronizing the timing subsystems of the physical modules of a local area network|
|US4991112||21 déc. 1988||5 févr. 1991||U.S. Philips Corporation||Graphics system with graphics controller and DRAM controller|
|US5115507||25 mars 1991||19 mai 1992||U.S. Philips Corp.||System for management of the priorities of access to a memory and its application|
|US5140685||16 sept. 1991||18 août 1992||Unisys Corporation||Record lock processing for multiprocessing data system with majority voting|
|US5142683||7 oct. 1991||25 août 1992||Unisys Corporation||Intercomputer communication control apparatus and method|
|US5155831||24 avr. 1989||13 oct. 1992||International Business Machines Corporation||Data processing system with fast queue store interposed between store-through caches and a main memory|
|US5155854 *||3 févr. 1989||13 oct. 1992||Digital Equipment Corporation||System for arbitrating communication requests using multi-pass control unit based on availability of system resources|
|US5168555||6 sept. 1989||1 déc. 1992||Unisys Corporation||Initial program load control|
|US5173897||19 déc. 1990||22 déc. 1992||Alcatel N.V.||Method of restoring the correct cell sequence, particularly in an atm exchange, and output unit therefor|
|US5251205||4 sept. 1990||5 oct. 1993||Digital Equipment Corporation||Multiple protocol routing|
|US5255239||13 août 1991||19 oct. 1993||Cypress Semiconductor Corporation||Bidirectional first-in-first-out memory device with transparent and user-testable capabilities|
|US5263169 *||20 oct. 1991||16 nov. 1993||Zoran Corporation||Bus arbitration and resource management for concurrent vector signal processor architecture|
|US5313454||1 avr. 1992||17 mai 1994||Stratacom, Inc.||Feedback control system|
|US5347648||15 juil. 1992||13 sept. 1994||Digital Equipment Corporation||Digital computer system|
|US5367678 *||6 déc. 1990||22 nov. 1994||The Regents Of The University Of California||Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically|
|US5379295||31 juil. 1991||3 janv. 1995||Nec Corporation||Cross-connect system for asynchronous transfer mode|
|US5379432||19 juil. 1993||3 janv. 1995||Taligent, Inc.||Object-oriented interface for a procedural operating system|
|US5390329||20 juil. 1994||14 févr. 1995||Cray Research, Inc.||Responding to service requests using minimal system-side context in a multiprocessor environment|
|US5392391||18 oct. 1991||21 févr. 1995||Lsi Logic Corporation||High performance graphics applications controller|
|US5392411||3 févr. 1993||21 févr. 1995||Matsushita Electric Industrial Co., Ltd.||Dual-array register file with overlapping window registers|
|US5392412||3 oct. 1991||21 févr. 1995||Standard Microsystems Corporation||Data communication controller for use with a single-port data packet buffer|
|US5404464||11 févr. 1993||4 avr. 1995||Ast Research, Inc.||Bus control system and method that selectively generate an early address strobe|
|US5404469||25 févr. 1992||4 avr. 1995||Industrial Technology Research Institute||Multi-threaded microprocessor architecture utilizing static interleaving|
|US5404482||22 juin 1992||4 avr. 1995||Digital Equipment Corporation||Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills|
|US5432918||22 juin 1992||11 juil. 1995||Digital Equipment Corporation||Method and apparatus for ordering read and write operations using conflict bits in a write queue|
|US5448702||2 mars 1993||5 sept. 1995||International Business Machines Corporation||Adapters with descriptor queue management capability|
|US5450351||19 nov. 1993||12 sept. 1995||International Business Machines Corporation||Content addressable memory implementation with random access memory|
|US5452437||18 nov. 1991||19 sept. 1995||Motorola, Inc.||Methods of debugging multiprocessor system|
|US5452452||4 juin 1993||19 sept. 1995||Cray Research, Inc.||System having integrated dispatcher for self scheduling processors to execute multiple types of processes|
|US5459842||26 juin 1992||17 oct. 1995||International Business Machines Corporation||System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory|
|US5459843||28 juil. 1994||17 oct. 1995||International Business Machines Corporation||RISC-type pipeline processor having N slower execution units operating in parallel interleaved and phase offset manner with a faster fetch unit and a faster decoder|
|US5463625||1 oct. 1993||31 oct. 1995||International Business Machines Corporation||High performance machine for switched communications in a heterogeneous data processing network gateway|
|US5467452||14 juil. 1993||14 nov. 1995||International Business Machines Corporation||Routing control information via a bus selectively controls whether data should be routed through a switch or a bus according to number of destination processors|
|US5475856||17 oct. 1994||12 déc. 1995||International Business Machines Corporation||Dynamic multi-mode parallel processing array|
|US5485455||28 janv. 1994||16 janv. 1996||Cabletron Systems, Inc.||Network having secure fast packet switching and guaranteed quality of service|
|US5515296||29 juin 1994||7 mai 1996||Intel Corporation||Computer-implemented process|
|US5517648||16 mars 1995||14 mai 1996||Zenith Data Systems Corporation||Symmetric multiprocessing system with unified environment and distributed system functions|
|US5539737||30 déc. 1994||23 juil. 1996||Advanced Micro Devices, Inc.||Programmable disrupt of multicast packets for secure networks|
|US5542070||19 déc. 1994||30 juil. 1996||Ag Communication Systems Corporation||Method for rapid development of software systems|
|US5542088||29 avr. 1994||30 juil. 1996||Intergraph Corporation||Method and apparatus for enabling control of task execution|
|US5544236||10 juin 1994||6 août 1996||At&T Corp.||Access to unsubscribed features|
|US5550816||29 déc. 1994||27 août 1996||Storage Technology Corporation||Method and apparatus for virtual switching|
|US5557766||21 oct. 1992||17 sept. 1996||Kabushiki Kaisha Toshiba||High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous bank pointers to specify a return bank|
|US5568476||26 oct. 1994||22 oct. 1996||3Com Corporation||Method and apparatus for avoiding packet loss on a CSMA/CD-type local area network using receive-sense-based jam signal|
|US5568617||13 janv. 1994||22 oct. 1996||Hitachi, Ltd.||Processor element having a plurality of processors which communicate with each other and selectively use a common bus|
|US5574922||17 juin 1994||12 nov. 1996||Apple Computer, Inc.||Processor with sequences of processor instructions for locked memory updates|
|US5581729||31 mars 1995||3 déc. 1996||Sun Microsystems, Inc.||Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system|
|US5592622||10 mai 1995||7 janv. 1997||3Com Corporation||Network intermediate system with message passing architecture|
|US5613071||14 juil. 1995||18 mars 1997||Intel Corporation||Method and apparatus for providing remote memory access in a distributed memory multiprocessor system|
|US5613136||29 oct. 1993||18 mars 1997||University Of Iowa Research Foundation||Locality manager having memory and independent code, bus interface logic, and synchronization components for a processing element for intercommunication in a latency tolerant multiple processor|
|US5617327||30 juil. 1993||1 avr. 1997||Xilinx, Inc.||Method for entering state flow diagrams using schematic editor programs|
|US5623489||17 avr. 1995||22 avr. 1997||Ipc Information Systems, Inc.||Channel allocation system for distributed digital switching network|
|US5627829||6 juin 1995||6 mai 1997||Gleeson; Bryan J.||Method for reducing unnecessary traffic over a computer network|
|US5630074||15 mai 1995||13 mai 1997||Network Systems Corporation||Inter-program communication and scheduling method for personal computers|
|US5630130||10 déc. 1993||13 mai 1997||Centre Electronique Horloger S.A.||Multi-tasking low-power controller having multiple program counters|
|US5633865||29 juil. 1996||27 mai 1997||Netvantage||Apparatus for selectively transferring data packets between local area networks|
|US5644623||31 janv. 1996||1 juil. 1997||Safco Technologies, Inc.||Automated quality assessment system for cellular networks by using DTMF signals|
|US5649110||7 nov. 1994||15 juil. 1997||Ben-Nun; Michael||Traffic shaping system with virtual circuit table time stamps for asynchronous transfer mode networks|
|US5649157||30 mars 1995||15 juil. 1997||Hewlett-Packard Co.||Memory controller with priority queues|
|US5651002||12 juil. 1995||22 juil. 1997||3Com Corporation||Internetworking device with enhanced packet header translation and memory|
|US5659687||18 avr. 1996||19 août 1997||Electronics & Telecommunications Research Institute||Device for controlling memory data path in parallel processing computer system|
|US5680641||16 août 1995||21 oct. 1997||Sharp Microelectronics Technology, Inc.||Multiple register bank system for concurrent I/O operation in a CPU datapath|
|US5689566||24 oct. 1995||18 nov. 1997||Nguyen; Minhtam C.||Network with secure communications sessions|
|US5692126||24 janv. 1995||25 nov. 1997||Bell Atlantic Network Services, Inc.||Data communication network|
|US5699537||22 déc. 1995||16 déc. 1997||Intel Corporation||Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions|
|US5701434||16 mars 1995||23 déc. 1997||Hitachi, Ltd.||Interleave memory controller with a common access queue|
|US5717898||10 mai 1995||10 févr. 1998||Intel Corporation||Cache coherency mechanism for multiprocessor computer systems|
|US5721870||22 mai 1995||24 févr. 1998||Nec Corporation||Lock control for a shared main storage data processing system|
|US5724574||2 avr. 1996||3 mars 1998||Remote Systems Company, Llc||Method and apparatus for transferring data to a remote workstation using communications established as a background function at time workstation|
|US5740402||13 juin 1995||14 avr. 1998||Silicon Graphics, Inc.||Conflict resolution in interleaved memory systems with multiple parallel accesses|
|US5742587||28 févr. 1997||21 avr. 1998||Lanart Corporation||Load balancing port switching hub|
|US5742782||14 avr. 1995||21 avr. 1998||Hitachi, Ltd.||Information processing apparatus|
|US5742822||19 déc. 1995||21 avr. 1998||Nec Corporation||Multithreaded processor which dynamically discriminates a parallel execution and a sequential execution of threads|
|US5745913||5 août 1996||28 avr. 1998||Exponential Technology, Inc.||Multi-processor DRAM controller that prioritizes row-miss requests to stale banks|
|US5751987||4 mai 1995||12 mai 1998||Texas Instruments Incorporated||Distributed processing memory chip with embedded logic having both data memory and broadcast memory|
|US5754764||22 févr. 1994||19 mai 1998||National Semiconductor Corp.||Combination of input output circuitry and local area network systems|
|US5761507||5 mars 1996||2 juin 1998||International Business Machines Corporation||Client/server architecture supporting concurrent servers within a server with a transaction manager providing server/connection decoupling|
|US5761522||18 avr. 1996||2 juin 1998||Fuji Xerox Co., Ltd.||Program control system programmable to selectively execute a plurality of programs|
|US5764915||8 mars 1996||9 juin 1998||International Business Machines Corporation||Object-oriented communication interface for network protocol access using the selected newly created protocol interface object and newly created protocol layer objects in the protocol stack|
|US5768528||24 mai 1996||16 juin 1998||V-Cast, Inc.||Client-server system for delivery of online information|
|US6014729 *||29 sept. 1997||11 janv. 2000||Firstpass, Inc.||Shared memory arbitration apparatus and method|
|US6347344 *||14 oct. 1998||12 févr. 2002||Hitachi, Ltd.||Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor|
|US6532509 *||22 déc. 1999||11 mars 2003||Intel Corporation||Arbitrating command requests in a parallel multi-threaded processing system|
|US6665755 *||22 déc. 2000||16 déc. 2003||Nortel Networks Limited||External memory engine selectable pipeline architecture|
|US6934780 *||3 oct. 2003||23 août 2005||Nortel Networks Limited||External memory engine selectable pipeline architecture|
|US6959002 *||18 juil. 2001||25 oct. 2005||Integrated Device Technology, Inc.||Traffic manager for network switch port|
|US6967963 *||1 déc. 1998||22 nov. 2005||3Com Corporation||Telecommunication method for ensuring on-time delivery of packets containing time-sensitive data|
|US6976095 *||30 déc. 1999||13 déc. 2005||Intel Corporation||Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch|
|US6981077 *||22 déc. 2000||27 déc. 2005||Nortel Networks Limited||Global access bus architecture|
|US6983350 *||31 août 1999||3 janv. 2006||Intel Corporation||SDRAM controller for parallel processor architecture|
|US7006495 *||31 août 2001||28 févr. 2006||Intel Corporation||Transmitting multicast data packets|
|US7065569 *||9 janv. 2001||20 juin 2006||Turin Networks, Inc.||System and method for remote traffic management in a communication network|
|US7069548 *||28 juin 2002||27 juin 2006||Intel Corporation||Inter-procedure global register allocation method|
|US7096277 *||7 août 2002||22 août 2006||Intel Corporation||Distributed lookup based on packet contents|
|US7100102 *||18 sept. 2003||29 août 2006||Intel Corporation||Method and apparatus for performing cyclic redundancy checks|
|US7111072 *||13 sept. 2000||19 sept. 2006||Cosine Communications, Inc.||Packet routing system and method|
|US7111296 *||8 juil. 2003||19 sept. 2006||Intel Corporation||Thread signaling in multi-threaded processor|
|US7124196 *||7 août 2002||17 oct. 2006||Intel Corporation||Processing a network packet using queues|
|US7126952 *||28 sept. 2001||24 oct. 2006||Intel Corporation||Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method|
|US7149786 *||4 oct. 1999||12 déc. 2006||Jetter Ag||Network for data transmission|
|US7181742 *||19 nov. 2002||20 févr. 2007||Intel Corporation||Allocation of packets and threads|
|US7191321 *||19 août 2003||13 mars 2007||Intel Corporation||Microengine for parallel processor architecture|
|US7206858 *||19 sept. 2002||17 avr. 2007||Intel Corporation||DSL transmit traffic shaper structure and procedure|
|US7248584 *||7 août 2002||24 juil. 2007||Intel Corporation||Network packet processing|
|EP0379709A2 *||21 déc. 1989||1 août 1990||International Business Machines Corporation||Single-fifo high speed combining switch|
|EP0464715A2 *||28 juin 1991||8 janv. 1992||Digital Equipment Corporation||Interlock queueing|
|EP0633678A1 *||29 juin 1993||11 janv. 1995||ALCATEL BELL Naamloze Vennootschap||Resequencing method and resequencing device realizing such a method|
|EP0745933A2 *||7 mai 1996||4 déc. 1996||International Business Machines Corporation||Multiple port register file with interleaved write ports|
|EP0773648A1 *||7 nov. 1995||14 mai 1997||ALCATEL BELL Naamloze Vennootschap||Method and apparatus for managing multicast connections|
|EP0809180A2 *||22 mai 1997||26 nov. 1997||Seiko Epson Corporation||Data processing circuit, microcomputer, and electronic equipment|
|1||"10-/100-Mbps Ethernet Media Access Controller (MAC) Core", NEC, 1988, pp. 1-5.|
|2||"Enterprise Hardware, Intel Expected to Unveil New Networking Chip," News.Com, Aug. 26, 1999, (accessed on Aug. 23, 2005), pp. 1-5.|
|3|| *||"Performance modeling and architecture exploration of network processors" by Govind et al. (abstract only) Publication Date: Sep. 19-22, 2005.|
|4||"The ATM Forum Technical Committee Traffic Management Specification Version 4.1", The ATM Forum (Mar. 1999).|
|5||"Enterprise Hardware, Intel Expected to Unveil New Networking Chip," News.Com, Aug. 26, 1999, <http://new.com.com/Intel+expected+to+unveil+new+networking+chip/2100-1001_3230315.html> (accessed on Aug. 23, 2005), pp. 1-5.|
|6||Agarwal et al., "April: A Processor Architecture for Multiprocessing", Laboratory for Computer Science, MIT, 1990 IEEE, pp. 104-114.|
|7||Beckerle, M.J., "Overview of the START (*T) multithreaded computer" (abstract only), Publication Date: Feb. 22-26, 1993.|
|8||Byrd et al., "Multithread Processor Architectures," IEEE Spectrum, 32(8):38-46, New York, Aug. 1995.|
|9||Chandranmenon, G.P., et al., "Trading Packet Headers for Packet Processing" IEEE/ACM Transactions on Networking, 4(2):141-152, Apr. 1996.|
|10||Chappell et al., "Simultaneous Subordinate Microthreading (SSMT)", 1999 IEEE, pp. 186-195.|
|11||Dictionary of Computer Words: An A to Z Guide to Today's Computers, Revised Edition, Houghton Mifflin Company: Boston, Massachusetts, pp. 220, (1995).|
|12||Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller, Hardware Reference Manual, Digital Equipment Corporation, pp. i-x, 1-1 through 1-5, 2-1 throught 2-12, 3-1 through 3-38, 4-31 through 5-2, 6-1 through 6-24, (Mar. 1998).|
|13||Doyle et al., Microsoft Press Computer Dictionary, 2nd ed., Microsoft Press, Redmond, Washington, USA, p. 326, (1994).|
|14||Farrens et al., "Strategies for Achieving Improved Processor Throughput," 1991 ACM, pp. 362-369.|
|15||Fillo et al., "The M-Machine Multicomputer," IEEE Proceedings of MICRO-28, pp. 146-156, (1995).|
|16||Frazier, Howard, "Gigabit Ethernet: From 100 to 1,000 Mbps", IEEE Internet Computing, pp. 24-31, (1999).|
|17||Frazier, Howard, "The 802.3z Gigabit Ethernet: Standard", IEEE Network, pp. 6-7, (1998).|
|18||Giroux, N., et al., "Queuing and Scheduling: Quality of Service in ATM Networks, Chapter 5", Quality of Service in ATM Networks: State-of-the-Art Traffic Management, pp. 96-121 (1998).|
|19||Gomez et al., "Efficient Multithreaded User-Space Transport for Network Computing: Design and Test of the TRAP Protocol," Journal of Parallel and Distributed Computing, Academic Press, Duluth, Minnesota, USA, 40(1):103-117, Jan. 1997.|
|20||Haug et al., "Reconfigurable hardware as shared resource for parallel threads," IEEE Symposium on FPGAs for Custom Computing Machines, 2 pages, (1998).|
|21||Hauser et al., "Garp: a MIPS processor with a reconfigurable coprocessor," Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 12-21, (1997).|
|22||Hyde, R., "Overview of Memory Management," Byte, 13(4):219-225, (1988).|
|23||Ippoliti, A., et al., "Parallel Media Access Controller for Packet Communications at Gb/s Rates", IEEE, pp. 991-996, (1990).|
|24||Jenks, S., et al., "Nomadic Threads: A migrating multithread approach to remote memory accesses in multiprocessors" (abstract only), Publication Date: Oct. 20-23, 1996.|
|25||Kaiserswerth, M., "The parallel Protocol Engine", IEEE/ACM Transactions on Networking, 1(6):650-663, Dec. 1993.|
|26||Khailany, B., et al., "Imagine: Media Processing with Streams," IEEE Micro, Mar.-Apr. 2001, pp. 35-46.|
|27||Leon-Garcia, A., Communication Networks: Fundamental Concepts and Key Architectures, McGraw-Hill Higher Education, Copyright 2000, pp. 195-198, 215-219, & 380-385.|
|28||Lim, A., et al., "Improving Performance of Adaptive Media Access Control Protocols for High-Density Wireless Networks", Proceedings of the 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 'pp) , pp. 316-321, Jun. 1999.|
|29||Litch et al., "StrongARMing Portable Communications," IEEE Micro, 18(2):48-55, Mar. 1998.|
|30||Mollenauer, J.F., et al., "An Efficient Media Access Control Protocol for Broadband Wireless Access Systems" IEEE Standard, IEEE 802.16 Broadband Wireless Access Working Group, 19 pages, Oct. 1999.|
|31||Ocheltree, K.B., et al., "A Comparison of fibre channel and 802 MAC services", Proceedings of 18th Conference on Local Computer Networks, abstract only, 1 page, Sep. 1993.|
|32||Schmidt et al., "The Performance of Alternative Threading Architectures for Parallel Communication Subsystems," Internet Document, Online!, Nov. 13, 1998, pp. 1-19.|
|33||Shaw, M.C., et al., UNIX Internals: A Systems Operations Handbook, Windcrest Books, pp. 30-37, 1987.|
|34||Thistle et al., "A Processor Architecture for Horizon," IEEE Proc. Supercomputing '88, pp. 35-41, Nov. 1988.|
|35||Todorova, P., et al., "Quality-of-Service-Oriented Media Access Control for Advanced Mobile Multimedia Satellite Systems", Proceedings of the 36th Annual Hawaii International Conference on System Sciences (HICSS'03), 8 pages, Jan. 2003.|
|36||Tremblay et al., "A Three Dimensional Register File for Superscalar Processors," IEEE Proceedings of the 28th Annual Hawaii International Conference on System Sciences, pp. 191-201, (1995).|
|37||Trimberger et al, "A time-multiplexed FPGA," Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 22-28, (1997).|
|38||Turner et al., "Design of a High Performance Active Router," Internet Document, Online!, 20 pages, Mar. 18, 1999.|
|39||U.S. Appl. No. 09/473,571, filed Dec. 28, 1999, Wolrich et al.|
|40||U.S. Appl. No. 09/475,614, filed Dec. 30, 1999, Wolrich et al.|
|41||Vibhatavanij et al., "Simultaneous Multithreading-Based Routers," Proceedings of the 2000 International Conference of Parallel Processing, Toronto, Ontario, Canada, Aug. 21-24, 2000, pp. 362-369.|
|42||Vuppala, V., et al., "Layer-3 switching using virtual network ports", IEEE Proc. Computer Communications and Networks, pp. 642-648, 1999.|
|43||Wazlowski et al., "PRSIM-II computer and architecture," IEEE Proceedings, Workshop on FPGAs for Custom Computing Machines, pp. 9-16, (1993).|
|44||Wikipedia entry, "Media Access Control", retrieved from http://en.wikipedia.org/wiki/Media_access_control, 2 pages, Jul. 31, 2007.|
| Brevet citant|| Date de dépôt|| Date de publication|| Déposant|| Titre|
|US20100211955 *||7 sept. 2007||19 août 2010||Cwi||Controlling 32/64-bit parallel thread execution within a microsoft operating system utility program|
|14 mai 2014||AS||Assignment|
Effective date: 20140402
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:032893/0199
Owner name: SONY CORPORATION OF AMERICA, NEW YORK
|1 juil. 2011||SULP||Surcharge for late payment|
Year of fee payment: 7
|1 juil. 2011||FPAY||Fee payment|
Year of fee payment: 8
|7 févr. 2011||REMI||Maintenance fee reminder mailed|
|11 juil. 2008||AS||Assignment|
Effective date: 20000320
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WOLRICH, GILBERT;BERNSTEIN, DEBRA;ADILETTA, MATTHEW J.;AND OTHERS;REEL/FRAME:021217/0529