USRE42228E1 - Method and apparatus for using data protection code for data integrity in on-chip memory - Google Patents
Method and apparatus for using data protection code for data integrity in on-chip memory Download PDFInfo
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- USRE42228E1 USRE42228E1 US10/723,963 US72396303A USRE42228E US RE42228 E1 USRE42228 E1 US RE42228E1 US 72396303 A US72396303 A US 72396303A US RE42228 E USRE42228 E US RE42228E
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
- G06F3/0676—Magnetic disk device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0689—Disk arrays, e.g. RAID, JBOD
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/245—Testing correct operation by using the properties of transmission codes
- H04L1/246—Testing correct operation by using the properties of transmission codes two-level transmission codes, e.g. binary
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/02—Topology update or discovery
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/12—Shortest path evaluation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/48—Routing tree calculation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9031—Wraparound memory, e.g. overrun or underrun detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9063—Intermediate storage in different physical parts of a node or terminal
- H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
- H04L49/9073—Early interruption upon arrival of a fraction of a packet
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
- G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0038—System on Chip
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/012—Recording on, or reproducing or erasing from, magnetic disks
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Small-Scale Networks (AREA)
- Information Transfer Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Multi Processors (AREA)
- Computer And Data Communications (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
Description
Fibre Channel FC-PH | X3T11/Project 755D/Rev. 4.3 | ||
Physical & Signalling Interface | |||
Fibre Channel FC-AL | X3T11/Project 960D/Rev. 4.5 | ||
Arbitrated Loop | |||
Fibre Channel FC-AL2 | X3T11/Project 1133D/Rev. 6.3 | ||
Arbitrated Loop | |||
Fibre Channel FCP | X3T10/ Rev. 012 | ||
Protocol for SCSI | X3.2 | ||
69-199X | |||
-
- a request from
microprocessor 112 to transmit a frame with xmit port enable, - the transmitting port is in the Monitoring state,
- transfer-length count not zero,
- no request from
microprocessor 112 to pause a transfer, and - (non-data transfer, or data-write transfer with transfer-ready not yet transmitted with data threshold met, or data-read transfer with data threshold met and data-frame buffer threshold met).
- a request from
-
- data-
frame buffer 55 has data available - Buffer-to-Buffer Credit is available (R_RDY received)
- non-data transfer, or data-read transfer and transfer-length counter (in
block 609; seeFIG. 12 ) is non-zero
Conditions that cause theloop 1250 to be closed include: - no Buffer-to-Buffer Credit is available when entering the Opened state
- there are no outstanding R_DY's and no more BB_Credit is available when in Opened state
- a processor busy request is active when the port is in Opened state
- the transfer has completed
- data-read transfer operation and data are not available
- a CLS primitive is received and no more BB_Credit is available
- a microprocessor pause request is pending and the logic is between frames
- data-
-
- 1) how much receive space is available in off-
chip buffer 111 fordisc drive 100 - 2) how much receive space is available in receive-non-data-
frame buffer 53 and data-frame buffer 55 fordisc drive 100 - 3) whether, given the credit, the port with which drive 100 is opened could potentially send frames that could occupy the available space.
- 1) how much receive space is available in off-
-
- at least X-frames are available off-chip, and
- at least Y-words of data are available in the data-
frame buffer 55. In one such embodiment, the value of X (where X represents the number of frames which need to be available in the off-chip buffer 111 in order to keep theloop 1250 held open) and the value for Y (where Y represents the number of words which need to be available in the on-chip buffer in order to keep theloop 1250 held open) are each separately programmable (e.g., by firmware code via microprocessor 112). In another embodiment, theloop 1250 is held open when a predetermined amount of data (not necessarily specified as a number of frames) is available in the off-chip buffer 111 (in one such embodiment, the predetermined amount of data required to be available in the off-chip buffer 111 is programmable). In another embodiment, theloop 1250 is held open when a predetermined amount of data (not necessarily specified as a number of words) is available in the on-chip buffer 119 (in one such embodiment, the predetermined amount of data required to be available in the on-chip buffer 119 is programmable). In one embodiment, theloop 1250 is held open if the predetermined amount of data is available (at least one-half frame on-chip and at least one frame available off-chip), but the transfer of a frame will not start until an entire frame is available on-chip.
-
- (a) supporting a fibre-channel arbitrated-loop communications channel (1250) on each of a first port (116) and a second port (116) of a first channel node (1220);
- (b) receiving a frame from the communications channel (1250), the received frame including a cyclic-redundancy code that is based on other data in the received frame;
- (c) storing the received frame, including the cyclic-redundancy code, into a frame buffer (53 or 55);
- (d) moving the received frame to a memory (111) that is separate from the frame buffer (53 OR 55); and
- (e) checking the received frame for accuracy by verifying the cyclic-redundancy code (CRC) while moving the received frame to the separate memory (111).
In one embodiment, the method includes steps of: - (f) placing a frame that is to be transmitted into an on-chip frame buffer (55);
- (g) generating the cyclic-redundancy code based on data in the frame to be transmitted; and
- (h) transmitting the frame to be transmitted, including the cyclic-redundancy code, onto the communications channel (1250).
In one such embodiment of the method, the placing step (f) further includes steps of: - (f)(i) generating parity for data of the frame to be transmitted;
- (f)(ii) adding parity to the data of the frame to be transmitted; and the moving step (d) further includes a step of
- (d)(i) stripping away the cyclic-redundancy code while moving the received frame to the separate memory (111).
In another embodiment of the method, the receiving step (b) further includes a step of
- (d)(i) stripping away the cyclic-redundancy code while moving the received frame to the separate memory (111).
- (b)(i) checking the received frame for accuracy by verifying the cyclic-redundancy code while receiving the received frame from the communications channel (1250).
In one embodiment, the method further includes a step of - (i) transferring data through the fibre-channel arbitrated-loop communications channel (1250) between a magnetic-disc-storage drive (1256) that is operatively coupled to the first channel node (1220) and a computer system (1202) having a second channel node (1220), wherein the second channel node (1220) is operatively coupled to the first channel node (1220) by the communications channel (1250).
Claims (30)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/723,963 USRE42228E1 (en) | 1997-11-17 | 2003-11-26 | Method and apparatus for using data protection code for data integrity in on-chip memory |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US6591997P | 1997-11-17 | 1997-11-17 | |
US6592697P | 1997-11-17 | 1997-11-17 | |
US6592097P | 1997-11-17 | 1997-11-17 | |
US6721197P | 1997-12-01 | 1997-12-01 | |
US09/193,446 US6324669B1 (en) | 1997-11-17 | 1998-11-17 | Method and apparatus for using CRC for data integrity in on-chip memory |
US10/723,963 USRE42228E1 (en) | 1997-11-17 | 2003-11-26 | Method and apparatus for using data protection code for data integrity in on-chip memory |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/193,446 Reissue US6324669B1 (en) | 1997-11-17 | 1998-11-17 | Method and apparatus for using CRC for data integrity in on-chip memory |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE42228E1 true USRE42228E1 (en) | 2011-03-15 |
Family
ID=27490525
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/193,446 Ceased US6324669B1 (en) | 1997-11-17 | 1998-11-17 | Method and apparatus for using CRC for data integrity in on-chip memory |
US09/193,681 Expired - Lifetime US6279057B1 (en) | 1997-11-17 | 1998-11-17 | Communications system having dedicated frame buffers located in a channel node connected to two ports of the channel node for receiving frames |
US09/193,482 Ceased US6317800B1 (en) | 1997-11-17 | 1998-11-17 | System for reducing arbitrated-loop overhead by maintaining control of a communications channel as long as a predetermined amount of data is available within control of channel node |
US09/193,387 Expired - Lifetime US6502189B1 (en) | 1997-11-17 | 1998-11-17 | Method and dedicated frame buffer for loop initialization and responses |
US10/714,478 Expired - Lifetime USRE40034E1 (en) | 1997-11-17 | 2003-11-13 | Method and apparatus to reduce serial communications path connection overhead |
US10/723,963 Expired - Lifetime USRE42228E1 (en) | 1997-11-17 | 2003-11-26 | Method and apparatus for using data protection code for data integrity in on-chip memory |
Family Applications Before (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/193,446 Ceased US6324669B1 (en) | 1997-11-17 | 1998-11-17 | Method and apparatus for using CRC for data integrity in on-chip memory |
US09/193,681 Expired - Lifetime US6279057B1 (en) | 1997-11-17 | 1998-11-17 | Communications system having dedicated frame buffers located in a channel node connected to two ports of the channel node for receiving frames |
US09/193,482 Ceased US6317800B1 (en) | 1997-11-17 | 1998-11-17 | System for reducing arbitrated-loop overhead by maintaining control of a communications channel as long as a predetermined amount of data is available within control of channel node |
US09/193,387 Expired - Lifetime US6502189B1 (en) | 1997-11-17 | 1998-11-17 | Method and dedicated frame buffer for loop initialization and responses |
US10/714,478 Expired - Lifetime USRE40034E1 (en) | 1997-11-17 | 2003-11-13 | Method and apparatus to reduce serial communications path connection overhead |
Country Status (7)
Country | Link |
---|---|
US (6) | US6324669B1 (en) |
JP (4) | JP2001523861A (en) |
KR (3) | KR100650818B1 (en) |
CN (3) | CN1304520A (en) |
DE (3) | DE19882822T1 (en) |
GB (3) | GB2342021B (en) |
WO (3) | WO1999026137A1 (en) |
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- 1998-11-17 WO PCT/US1998/024558 patent/WO1999026152A2/en active IP Right Grant
- 1998-11-17 KR KR1020007005386A patent/KR100734649B1/en not_active IP Right Cessation
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- 1998-11-17 GB GB9928809A patent/GB2341526B/en not_active Expired - Fee Related
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2003
- 2003-11-13 US US10/714,478 patent/USRE40034E1/en not_active Expired - Lifetime
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