Images

Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
  • G01B11/00—Measuring arrangements characterised by the use of optical techniques
  • G01B11/26—Measuring arrangements characterised by the use of optical techniques for measuring angles or tapers; for testing the alignment of axes
  • G01B11/27—Measuring arrangements characterised by the use of optical techniques for measuring angles or tapers; for testing the alignment of axes for testing the alignment of axes
  • G01B11/272—Measuring arrangements characterised by the use of optical techniques for measuring angles or tapers; for testing the alignment of axes for testing the alignment of axes using photoelectric detection means
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
  • G03F7/70605—Workpiece metrology
  • G03F7/70616—Monitoring the printed patterns
  • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
  • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
  • G01N21/17—Systems in which incident light is modified in accordance with the properties of the material investigated
  • G01N21/47—Scattering, i.e. diffuse reflection
  • G01N21/4785—Standardising light scatter apparatus; Standards therefor
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
  • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
  • G01N21/84—Systems specially adapted for particular applications
  • G01N21/88—Investigating the presence of flaws or contamination
  • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
  • G01N21/9501—Semiconductor wafers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
  • H01L21/682—Mask-wafer alignment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/975—Substrate or mask aligning feature

Definitions

• the present invention relates generally to overlay measurement techniques, which are used in semiconductor manufacturing processes. More specifically, the present invention relates to techniques for measuring alignment error between different layers or different patterns on the same layer of a semiconductor wafer stack.
• overlay error between successive patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices.
• Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.
• overlay measurements are performed via test patterns that are printed together with layers of the wafer. The images of these test patterns are captured via an imaging tool and an analysis algorithm is used to calculate the relative displacement of the patterns from the captured images.
• the most commonly used overlay target pattern is the “Box-in-Box” target, which includes a pair of concentric squares (or boxes) that are formed on successive layers of the wafer.
• the overlay error is generally determined by comparing the position of one square relative to another square.
• FIG. 1 is a top view of a typical “Box-in-Box” target 10 .
• the target 10 includes an inner box 12 disposed within an open-centered outer box 14 .
• the inner box 12 is printed on the top layer of the wafer while the outer box 14 is printed on the layer directly below the top layer of the wafer.
• the overlay error between the two boxes, along the x-axis for example is determined by calculating the locations of the edges of lines c 1 and c 2 of the outer box 14 , and the edge locations of the lines c 3 and c 4 of the inner box 12 , and then comparing the average separation between lines c 1 and c 3 with the average separation between lines c 2 and c 4 .
• the overlay error (along the x-axis).
• the overlay error between the two boxes along the y-axis may also be determined using the above technique.
• This type of target has a same center of symmetry (COS) for both the x and y structures, as well as for the first and second layer structures.
• COS center of symmetry
• COS center of symmetry
• both the x and y structures and both the first and second layer structures have a same COS.
• these requirements may be too restrictive under certain conditions. For example, space may be limited on the wafer and a target having x and y structures (or first and second layer structures) with the same COS may not fit into the available space. Additionally, it may be desirable to use device structures for determining overlay, and device structures are not likely to meet this strict requirement.
• a target includes structures for measuring overlay error (or a shift) in both the x and y direction, wherein the x structures have a different center of symmetry (COS) than the y structures.
• COS center of symmetry
• one of the x and y structures is invariant with a 180° rotation and the other one of the x and y structures has a mirror symmetry.
• the x and y structures together are variant with a 180° rotation.
• a target for measuring overlay in the x and/or y direction includes structures on a first layer having a 180 symmetry and structures on a second layer having mirror symmetry.
• a target for determining overlay in the x and/or y direction includes structures on a first layer and structures on a second layer, wherein the structures on the first layer have a COS that is offset by a known amount from the COS of the structures on the second layer.
• any of the disclosed target embodiments may take the form of device structures.
• device structures that have an inherent 180° rotational symmetry or a mirror symmetry in each of the first and second layers are used to measure overlay in a first layer and a second layer.
• a semiconductor target for determining a relative shift between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate includes a plurality of first structures having a first center of symmetry (COS) or first line of symmetry (LOS) and being arranged to determine the relative shift in an x direction by analyzing an image of the first structures.
• This target further includes a plurality of second structures having a second COS or second LOS and being arranged to determine the relative shift in an x direction by analyzing an image of the second structures.
• the first COS or LOS has a different location than the second COS or LOS.
• the first structures have a first LOS about which the first structures have a mirror symmetry or the first structures have a 180° rotational symmetry with respect to the first COS
• the second structures have a first LOS about which the second structures have a mirror symmetry or the second structures have a 180° rotational symmetry with respect to the second COS
• the first and second structures are in the form of device structures.
• a one of the first or second structures has a 180° rotational symmetry with respect to its COS and the other one of the first or second structures' has a mirror symmetry with respect to its LOS.
• the first structures and the second structures together are variant with a 180° rotational asymmetry or together have a mirror asymmetry.
• a semiconductor target for determining an overlay error between two or more successive layers of a substrate comprises a plurality of first structures formed in a first semiconductor layer and having a first center of symmetry or first line of symmetry (LOS) and a plurality of second structures formed in a second semiconductor layer and having a second COS OR LOS.
• the first COS OR LOS is designed to have a known offset from the second COS or LOS so that the overlay error can be determined by acquiring an image of the first and second structures and then analyzing a shift between the first and second COS's or LOS's in the image and comparing the shift to the known offset.
• the first structures have a first LOS about which the first structures have a mirror symmetry or the first structures have a 180° rotational symmetry with respect to the first COS
• the second structures have a first LOS about which the second structures have a mirror symmetry or the second structures have a 180° rotational symmetry with respect to the second COS
• the first and second structures are in the form of device structures.
• a one of the first or second structures has a 180° rotational symmetry with respect to its COS and the other one of the first or second structures' has a mirror symmetry with respect to its LOS.
• the first structures and the second structures together are variant with a 180° rotational asymmetry or together have a mirror asymmetry.
• the invention pertains to a method for determining the relative shift between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate.
• a first image is acquired of a plurality of first structures having a first center of symmetry (COS) or first line of symmetry (LOS) and being arranged to determine the relative shift in an x direction by analyzing an image of the first structures.
• a first image is acquired of a plurality of second structures having a second COS or second LOS and being arranged to determine the relative shift in an x direction by analyzing an image of the second structures.
• the first COS or LOS has a different location than the second COS or LOS.
• the first image of the first structures' COS is analyzed to determine whether the first structures have a shift in the x direction that is out of specification, and the second image of the second structures' COS is analyzed determine whether the second structures have a shift in the y direction that is out of specification.
• the first and second images are acquired together in a same field of view.
• analyzing the first image comprises (i) when it is determined that the first structures fail to have a 180 rotational or mirror symmetry, determining that the first structures are out of specification; and (ii) when it is determined that the second structures fail to have a 180 rotational or mirror symmetry, determining that the second structures are out of specification.
• analyzing the first image and analyzing the second image each includes (i) using outside edges of each region of interest of the first or second image to determine a COS or LOS for a first set of substructures and a COS or LOS for a second set of substructures, and (ii) when the COS or LOS of the first set of substructures differs from the COS or LOS of the second set of substructures by more than a predetermined amount, determining that the corresponding structures are out of specification.
• the first set of substructures are formed from a first layer and the second set of substructures are formed from a second layer.
• analyzing the first image and analyzing the second image each includes (i) for a first set of substructures, selecting an initial COS or LOS between a plurality of regions of interest, (ii) for the first set of substructures, automatically placing its 180 degree or mirror counterpart based on the initial COS or LOS, respectively, for each of the first and second images, (iii), for the first set of substructures, continuing to move the initial COS or LOS until a best correlation is found between the first substructures and their counterpart, (iv) repeating operations (i) through (iii) for a second set of substructures, (v) when a best correlation is found for both the first and second substructures and when the COS or LOS of the first set of substructures differs from the COS or LOS of the second set of substructures by more than a predetermined amount, determining that the corresponding first structures are out of specification.
• the first set of substructures are formed from a first layer and the
• the overlay error between two or more successive layers of a substrate is determined.
• An image is acquired of a plurality of first structures formed in a first semiconductor layer and having a first center of symmetry (COS) or line of symmetry (LOS) and a plurality of second structures formed in a second semiconductor layer and having a second COS or LOS.
• the first COS or LOS is designed to have a known offset from the second COS or LOS so that the overlay error can be determined by acquiring an image of the first and second structures and then analyzing a shift between the first and second COS's or LOS's in the image and comparing the shift to the known offset.
• the image of the first and second structures' COS or LOS is analyzed to determine whether there is an overlay error between the first and second structures that is out of specification.
• the first structures have a first LOS about which the first structures have a mirror symmetry or the first structures have a 180° rotational symmetry with respect to the first COS
• the second structures have a first LOS about which the second structures have a mirror symmetry or the second structures have a 180° rotational symmetry with respect to the second COS
• the first and second structures are in the form of device structures.
• a one of the first or second structures has a 180° rotational symmetry with respect to its COS and the other one of the first or second structures' has a mirror symmetry with respect to its LOS.
• the first structures and the second structures together are variant with a 180° rotational asymmetry or together have a mirror asymmetry.
• the present invention is illustrated by way of example, and not by way of limitation.
• FIG. 1 is a top plan view of a box-in-box type overlay mark.
• FIG. 2 is a top plan view of overlay targets for measuring overlay error between two different process layers in both an x and y direction in accordance with one embodiment of the present invention.
• FIG. 3 is a diagrammatic top view an overlay target, wherein one of its x and y direction structures has a 180° rotational symmetry while the other of its x and y direction structures has a mirror symmetry, in accordance with an alternative embodiment of the present invention.
• FIG. 4A is a diagrammatic top view of an overlay target in accordance with a specific implementation of the present invention.
• FIG. 4B is a diagrammatic top view of an overlay target in accordance with an alternative implementation of the present invention.
• FIGS. 4C through 4E together illustrate a technique for forming combination dummy and overlay structures, as well as example structures, in accordance with specific implementations of the present invention.
• FIG. 5 is a flowchart illustrating a procedure for inspecting targets in accordance with techniques of the present invention.
• FIG. 6 is a flowchart illustrating the operation of FIG. 5 for determining whether a target is out of specification in accordance with a specific implementation of the present invention.
• the present invention provides semiconductor targets for determining an overlay error between two process layers or a shift between two sets of structures on the same layer, where the target structures are designed with a known relationship between their symmetry characteristics.
• the following target examples are shown to have structures on two layers for measuring overlay, it is readily apparent that each target may include two sets of structures on the same layer for determining a shift error between such set of structures.
• FIG. 2 is a top plan view of overlay targets for measuring overlay error between two different process layers in both an x and y direction in accordance with one embodiment of the present invention.
• a first target 202 is arranged for measuring an overlay error between a set of first structures 206 in a first layer and a set of second structures 208 in a second layer with respect to an x direction.
• a second target 204 is arranged for measuring an overlay error between a set of first structures 212 in a first layer and a set of second structures 214 in a second layer with respect to a y direction.
• each of the x and y targets are designed so that its first structures have a same 180° rotational center of symmetry as its second structures although the x direction target 202 is designed to have a center of symmetry (COS) 210 that has a different location than the y direction target 204 COS 214 .
• COS center of symmetry
• the x direction target 202 has first structures that are divided into two groups 206 a and 206 b that are positioned with respect to each other so that if they were rotated 180° about a center of symmetry 210 , the first structures would have a same appearance before and after such rotation.
• the x direction target 204 also includes second structures 208 that are divided into two groups 208 a and 208 b that are positioned with respect to each other so that if they were rotated 180° about a center of symmetry 210 , the first structures would have a same appearance before and after such rotation.
• the COS of the first structures is at the same position as the COS of the second structures.
• the COS of the first structures of such target is shifted from the COS of the second structures. This shift is called the overlay error.
• the overlay error in separate x and y targets may be determined based on a priori knowledge that each target is designed to have structures in each layer that have a 180° rotational symmetry about a same COS. Any shift between the COS's of the first and second layer structures may be imaged and measured as an overlay error.
• the x and/or y targets of FIG. 2 may be arranged so that the first and second structures have a COS with a known offset. In this case, if the shift does not match the known offset, the amount of variance corresponds to the overlay error.
• FIG. 3 is a diagrammatic top view an overlay target 300 , wherein one of its x and y direction structures has a 180° rotational symmetry while the other of its x and y direction structures has a mirror symmetry, in accordance with an alternative embodiment of the present invention.
• the target 300 includes x direction structures 306 and 308 and y direction structures 302 and 304 .
• the x direction structures include a first set of structures 306 a and 306 b on a first layer and a second set of structures 308 a and 308 b on a second layer.
• the y direction structures include a first set of structures 302 a and 302 b on a first layer and a single structure 304 on a second layer.
• the first and second structures of the x direction target are designed to have a 180° rotational symmetry with respect to a same center of symmetry (COS) 310
• the first and second structures of the y direction target are designed to have a mirror symmetry with respect to a same line of symmetry (LOS) 312
• a shift between either the COS's or LOS's of the first and second layer structures can be imaged and measured to determine an overlay error in the x or y direction, respectively.
• the x and/or y targets of FIG. 3 may be arranged so that the first and second structures have COS's or LOS's with a known offset. In this case, if the shift does not match the known offset, the amount of variance corresponds to the overlay error.
• Targets having flexible symmetry characteristics may be in the form of device structures.
• device structures which have inherent symmetrical properties, such as a 180 rotational symmetry and/or a mirror symmetry for structures in a first and second layer may be used. These structures may also have a known offset between their COS's or LOS's.
• Such devices may be identified by the designer and identified by tags in the design layout. Alternatively, such “target” devices may be located manually or automatically after fabrication.
• the target structures of the present invention may have any suitable shape and arrangement so as to provide flexible symmetry characteristics.
• FIGS. 4A and 4B illustrate various examples of target shapes and arrangements. Although the targets are shown as having structures on a first layer with a same COS as structures on a second layer, the first and second layer structures may easily be designed to have different COS's. These FIGS. 4A and 4B are merely meant to illustrate the different shapes that the targets of the present invention may take.
• FIG. 4A is a diagrammatic top view of an overlay target in accordance with a specific implementation of the present invention.
• Each set of target structures in each layer may include any number and shape of structures.
• a first set of structures in a first layer (shaded black) includes structure 402 a through 402 d which have a center of symmetry 410 .
• Structures 402 a and 402 c are 7 sided polygons, while structures 402 b and 402 d are triangles.
• a second set of structures in a second layer includes structure 404 a through 404 d which have the same center of symmetry 410 as the first set of structures in the first layer.
• Structures 404 a and 404 c are star shaped polygons, while structures 404 b and 404 d are cross shaped polygons.
• the center of symmetry of the first layer structures is offset from the center of symmetry of the second layer structures by a known distance (not shown).
• FIG. 4B is a diagrammatic top view of an overlay target in accordance with an alternative implementation of the present invention.
• each structure includes a plurality of horizontal or vertical lines in two different layers. A first layer is shaded black, while a second layer is shaded gray.
• Each horizontal and vertical line may also be formed from a plurality of segments (not shown).
• horizontal structures 452 a, 452 b, 452 e and 452 f and vertical structures 452 b, 452 c, 452 d, 452 g, and 452 h have a same center of symmetry 454 .
• the different layers of each set of vertical and horizontal structures are shown as having a same center of symmetry.
• the center of symmetry of the horizontal structures is offset from the center of symmetry vertical structures by a known distance (not shown).
• the center of symmetry of the first layer structures is offset from the center of symmetry of the second layer structures (from the horizontal and/or vertical structures) by a known distance (not shown).
• the target rules preferably include a requirement that the target be placed in a layer which is measurable or inspectable by a particular type of tool.
• the target may have to be on a top layer or be covered with only optically transparent layers so that the target may be inspected by an optical tool.
• the target may be required to be underneath an opaque layer so that the opaque layer's conformance to the underlying target may be inspected and/or measured.
• each inspection, review, or metrology tool typically has a size constraint as to the measured or inspected structure. That is, structures below a particular size cannot be seen. Therefore, the targets must be sized so that they can be measured or inspected by the relevant tool.
• targets of the present invention described herein may be placed in any suitable space on the wafer.
• the targets may be placed in the scribe line or within the dies themselves.
• the die layout may also be analyzed to determine whether particular portions or areas have a characteristic which negatively or positively affects metrology or inspection results, as compared with other areas of the die layout. For example, particular layout characteristics may result in more reliable or accurate metrology or inspection results.
• targets may be placed in areas which have characteristics that positively affect the metrology or inspection.
• a chemical mechanical polishing (CMP) procedure is typically tuned to achieve superior accuracy with a particular feature density range.
• targets such as overlay targets, may be placed in layout regions which are within the particular feature density range for an optimal CMP process.
• the circuit designer may be aware of feature locations in the die layout which are most susceptible to error or defects.
• the designer may communicate the position of such features to the target placement software or layout engineer so that targets may be placed proximate to such problem features. This placement technique would likely result in a higher incidence of defect capture and more reliable resulting products.
• the targets may also be placed within a dummy layer. It is common practice in semiconductor manufacturing today to include dummy structures in open areas of the circuit layout to ensure uniform pattern density. Dummy structures are generally used for optimal results in chemical mechanical polishing and other semiconductor manufacturing processes.
• a structure which has two components that serve both purposes of a dummy structure and a metrology (or inspection) target would efficiently utilize the open spaces of the die area to increase CMP uniformity (and other dummy requirements where applicable), as well as to provide a metrology or inspection target.
• a new type of metrology or inspection may be used with such combination marks. For example, a particular design pattern's fidelity may be monitored via such combination target. That is, a designer's intent regarding a particular pattern's function or structure may be verified with respect to the pattern being combined and measured or inspected in a dummy structure.
• a combination target and dummy structure can be achieved in a number of different ways.
• the structures can be designed on two masks such that they form interlaced periodic structures.
• Any suitable types of overlay structures may be altered to have flexible COS's or LOS's as described herein.
• Suitably modifiable overlay targets and techniques for determining overlay with same are described in the following U.S. patents and applications: (1) U.S. Pat. No. 6,462,818, issued 8 Oct. 2002, entitled “OVERLAY ALIGNMENT MARK DESIGN”, by Bareket, (2) U.S. Pat. No. 6,023,338, issued 8 Feb. 2000, entitled “OVERLAY ALIGNMENT MEASUREMENT OF WAFER”, by Bareket, (3) application Ser.
• An overlay type combination and dummy structure includes two components one on a first layer or mask and one on a second layer or mask. Each component preferably complies with the requirements for a dummy structure of the process step associated with that layer or mask.
• a further example may be a case where these periodic structures are aligned such that the component on a first mask is symmetrically positioned with respect to the component on a second mask when the masks are correctly aligned.
• the component on a first mask may be designed to fit into the open spaces within the component on a second mask and visa versa.
• the periodic component on the two masks could be identical but offset by half a unit cell of the periodic structure along both x and y axes.
• the component on a first mask may have a different structure than the component on a second mask but is still offset by half a unit cell of the component as above.
• Example overlay type combination targets are shown in FIG. 4C through 4E .
• Each component may also contain an additional coarse segmentation which is periodic and is designed to improve the contrast and information content for the metrology tool as further described in the above referenced U.S. application Ser. No. 10/367,124 by Mike Adel et al.
• FIGS. 4C through 4E together illustrate a technique for forming combination dummy and overlay structures, as well as example structures, in accordance with specific implementations of the present invention.
• An open space may be filled with any suitably sized and shaped combination dummy and target structures (referred to herein as targets).
• targets are formed within an open area.
• the targets include a first set of structures on a first layer (e.g., the “+” shaped structures) and a second set of structures on a second layer (e.g., the hexagon shaped structures).
• the first set of structures has a COS 410
• the second set of structures have a second COS 412 that is offset from the first COS 410 .
• an array of targets may be conceptually used to fill in around actual device structures.
• an array of hexagon shaped and “+” shaped structures are overlaid onto two device structures.
• one device structure is shaped like a star and is on a same layer as the hexagon target structures, while another device structure is shaped like an arrow and is on the same layer as the “+” shaped target structures.
• some of the target structures are removed to accommodate the device structures. That is, target structures on one layer are removed from an area encompassing the device structure on the same layer.
• the “+” shaped structures are removed from an area encompassing the arrow shaped device structure, and the hexagon shaped structures are removed from an area encompassing the star shaped device structure.
• the target structures are removed such that a COS of each layer is maintained.
• the first layer structures have a first COS 420 that differs from the second COS 422 of the second layer structures.
• both layers of targets are removed from an area encompassing the two overlapping device structures as illustrated in FIG. 4E .
• the target structures are also removed such that a COS of each layer is maintained.
• the first layer structures have a first COS 430 that differs from the second COS 432 of the second layer structures.
• a signal is detected from the field of views (FOV's) as represented in FIGS. 4C-4E .
• the center of symmetries of the first and second layers are determined.
• the center of symmetries are designed to be located at a known offset from each other so that a discrepancy can be translated into an overlay value.
• a first set of structures are used to measure overlay in an x direction and a set of second structures are used to measure overlay in a y direction.
• the x direction structures have a center of symmetry or line of symmetry that differs from the y direction structures.
• the FOV includes both targets and devices as in FIGS. 4D and 4E .
• the signal or image generated from such signal
• the signal is compared to a design file which identifies device structures and the device structures' contribution to the signal (or image) is subtracted from the signal (or image).
• the resulting signal (or image) corresponds to the target which may then be assessed as previously described.
• one may manually train the metrology tool to locate targets by manually moving the tool to known target locations and identifying the targets. These identified targets can then be used by the metrology tool to search for other targets with a similar appearance using standard pattern recognition techniques.
• a representative target in the design file may be used to train the metrology tool.
• the representative target may also be located in a easily found position, such as the scribe line.
• the dummy structure rules may require a particular pattern density or maximum open space size for ensuring a particular level of CMP uniformity.
• the particular metrology or inspection procedure rules for the targets are followed.
• overlay metrology technique the structures on two different layers are assessed to determine whether their centers of symmetry are where they should be (e.g., aligned or offset by a known distance) to thereby determine overlay.
• the structures are designed on two different layers and have a same center of symmetry or known offset centers of symmetry.
• FIG. 5 is a flowchart illustrating a procedure 500 for inspecting targets fabricated from a layout pattern generated in accordance with techniques of the present invention. Initially, each target is inspected or measured to determine whether a process is out of specification in operation 502 . It is then determined whether a process is out of specification in operation 503 . If a process is not out of specification, the inspection, review, or measurement procedure ends.
• a subsequent process may be adjusted to compensate for the process which is out of specification in operation 504 . For example, if it is determined that the photoresist pattern is misaligned in any portion, the photoresist may then be stripped and reapplied in a corrected pattern to eliminate the misalignment. The subsequent process is then performed so as to continue fabrication of the same die in operation 506 . For example, the wafer may be patterned.
• processing of the die may be halted in operation 508 . The die may then be discarded in operation 510 .
• the process which is out of specification may then be adjusted for subsequent die(s) in operation 512 .
• FIG. 6 is a flow chart illustrating the operation 503 of FIG. 5 for determining whether a target is out of specification in accordance with a specific implementation of the present invention.
• this procedure is described with respect to a target having structures with a 180° rotational COS, of course, this procedure may be easily modified for structures with mirror symmetry. This procedure may also be applied to determining an alignment error between two sets of structures on the same layer, rather than an overlay error on two different layers as illustrated.
• the center of either X or Y target structures are initially moved to the center of the FOV of the inspection tool in operation 602 .
• the region of interests (ROI's) of each layer are then determined in operation 604 .
• the x target structures of FIG. 2 will be used to illustrate the procedure of FIG. 6 .
• four ROI's may be formed for the x direction target structures 206 a, 206 b, 208 a and 208 b of FIG. 2 , as represented by the dotted lines.
• the dotted line 202 may represent the FOV of the inspection tool, while the cross 210 represents the center of the x target structures.
• the COS for each set of structures 206 and 208 from the first and second layers, respectively, may be determined using any suitable technique.
• an edge technique may be utilized to determine COS for the structures in each layer.
• the outside edges of each ROI of each layer are used to determine the COS for each layer in operation 606 .
• the outside edges of each ROI may be determined and then the edges are then used to find a center position between the outside edges of each set of structures (e.g., between structures 206 a and structures 206 b).
• the edge of each set of subresolution lines e.g., the first layer lines of set 452 a
• COS determination technique is referred to as the correlation technique.
• an initial COS position is estimated between the ROI's of the structures of each layer in operation 608 .
• an initial estimate of COS 210 may be positioned between structures 206 a and 206 b.
• Two linear arrays are then obtained by measuring across the two sets of structures at positions that are equal distances from the initial COS.
• the structures 206 a and 206 b will tend to each result in a periodic signal with three peak intensity values.
• the two obtained linear arrays are then flipped horizontally and vertically and matched and a metric of correlation such as the product is calculated.
• the arrays are moved with respect to one another and the metric is calculated for each offset.
• the metric is then plotted and the correct COS is located by finding the maximum of the correlation metric.
• Intelligent searching algorithms e.g., a binary search
• Intelligent searching algorithms may also be used to efficiently locate the correct COS position.
• the COS is found using any suitable technique, it is then determined whether the COS of the first layer structures differs from the COS of the second layer structures by more than a predetermined value in operation 614 . If they do not differ by more than the predetermined value, it is determined that the x or y target under analysis in not out of specification in operation 618 . However, if they do differ by more than the predetermined amount, it is determined that the x or y target under analysis is out of specification in operation 616 . The procedure for determining whether the target is out of specification then ends.
• the techniques of the present invention may be implemented in any suitable combination of software and/or hardware system. Regardless of the system's configuration, it may employ one or more memories or memory modules configured to store data, program instructions for the general-purpose inspection operations and/or the inventive techniques described herein.
• the program instructions may control the operation of an operating system and/or one or more applications, for example.
• the memory or memories may also be configured to store layout patterns, layout constraint rules and target rules.
• the present invention relates to machine readable media that include program instructions, state information, etc. for performing various operations described herein.
• machine-readable media include, but are not limited to, magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROM disks; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and perform program instructions, such as read-only memory devices (ROM) and random access memory (RAM).
• ROM read-only memory devices
• RAM random access memory
• the invention may also be embodied in a carrier wave traveling over an appropriate medium such as airwaves, optical lines, electric lines, etc.
• program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter.

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