USRE45286E1 - Embedded microelectromechanical systems (MEMS) semiconductor substrate and related method of forming - Google Patents
Embedded microelectromechanical systems (MEMS) semiconductor substrate and related method of forming Download PDFInfo
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- USRE45286E1 USRE45286E1 US13/890,668 US201313890668A USRE45286E US RE45286 E1 USRE45286 E1 US RE45286E1 US 201313890668 A US201313890668 A US 201313890668A US RE45286 E USRE45286 E US RE45286E
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0271—Resonators; ultrasonic resonators
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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Abstract
An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A silicon nitride capping layer is applied over the polysilicon protection layer. A polsilicon seed layer is applied over the polysilicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.
Description
The present invention relates to microelectromechanical systems (MEMS), and more particularly, the present invention is related to semiconductor manufacturing techniques and MEMS.
MEMS technologies could be classified in various technology families. One technology family is a pure MEMS and a second technology family is a MEMS plus integrated circuit (IC). New applications, needs and features for MEMS appear constantly. MEMS technology includes the nano-scale and nano-electromechanical systems and related nano technology. MEMS devices often are referred to as micromachines or micro system technology. Silicon is used to create not only the integrated circuits that might be used with MEMS devices, but silicon is also used for fabricating the MEMS devices themselves, since in single crystal form, silicon is an almost perfect Hookean material. When flexed, silicon has virtually no hysteresis and little energy dissipation, allowing repeatable motion of MEMS devices for multiple cycles. Different semiconductor layers are deposited and patterned using photolithography and etching techniques to produce the required MEMS shapes. Wet and dry etching are also often used.
Other technologies used when fabricating MEMS include Reactive Ion Etching (RIE) and Deep Reactive Ion Etching (DRIE) and various type of fluoride etching for releasing any metal and dielectric structures. Surface micro machining and high aspect ratio (HAR) micromachining are often used as MEMS fabrication techniques.
MEMS devices are often fabricated for inkjet printers that use piezoelectric or thermal bubble ejection, accelerometers, gyroscopes, silicon pressure sensors, displays, such as with DMD chips, optical switches and other switches and display technology applications.
Many of the MEMS applications use specific films, layers and sequences of processing that were developed for standard CMOS, BiCMOS, BCD (Bipolar-CMOS-DMOS) or NV (non-volatile) memory applications. Some of these applications are pure MEMS technologies where no active electronic devices, such as transistors or other integrated circuits are used. These technologies are the main areas of current MEMS systems. The other field of MEMS technologies is categorized as IC plus MEMS where active components are required. For MEMS and IC technologies, a challenge after the stand-alone MEMS technology has been validated is integration with active devices, for example, a circuit driver.
MEMS integration with a major supporting technology has been studied for over 20 years and some practical and proven solutions have been developed with commercial success, but are reaching limits with the main core of MEMS technology developments. Some industrially proven solutions can exist as two different categories such as 1) back end-of-line (BEOL) integration and 2) the IC processing and assembly as a dual flow system. In BEOL integration, standard IC processing as CMOS and/or BCD is applied and followed by back end-of-line MEMS processing. Typical applications can include printers and sensor arrays with various metal to chemical interactions, biometric sensors such as capacitance sensors and thermal sensors as non-limiting examples. In IC processing and assembly as a dual flow system, standard IC processing occurs typically followed by sawing and die preparation. MEMS processing and specific materials for a vacuum set up are applied where most mechanical related MEMS applications require vacuum and seeding. The dual die assembly can be arranged in a board or in stacked die solutions.
It would be advantageous to have MEMS preparation as a separate process flow and deliver an embedded MEMS substrate, such that MEMS wafers can be forwarded to other semiconductor fabricators for subsequent processing as a vendor wafer (or silicon wafer) with an embedded MEMS, allowing subsequent processing by an outside vendor. Thus, the MEMS substrate is a raw substrate for CMOS, BiCMOS, BCD or flash standard processing. The embedded MEMS substrate acts as a standard initial starting material for subsequent processing.
The embedded MEMS semiconductor substrate uses MEMS preparation and fabrication as a separate process flow. It includes MEMS release, vacuum realization and seeding followed by growing an epitaxial layer on the wafer such that an embedded MEMS substrate can be delivered ready for the standard processing as a standard initial material. MEMS processing can occur in various wafer sizes including 6, 8 and 12-inch wafer size as non-limiting examples with MEMS release and seeding and silicon capping. It is oxide released and vacuum compliant in a non-limiting example.
An embedded MEMS semiconductor substrate is used as a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate that includes at least one MEMS electrode and a buried silicon dioxide sacrificial layer used for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A silicon nitride capping layer is applied over the polysilicon protection layer. A polysilicon seed layer is applied over the silicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.
In one aspect, the semiconductor wafer processing comprises one of CMOS, BiCHOS, BCD and NV memory processing. The buried oxide sacrificial layer could be removed by using hydrofluoric acid releasing. The planarizing layer can be removed by etching. The planarizing layer can be formed as a TEOS and spin-on-glass layer. The capping layer can be formed as a silicon nitride insulating layer. The MEMS device in one aspect is a resonator.
An electrode anchor can be formed to support at least the one MEMS electrode. Vias can be formed within the protection, nitride capping and seed layers for use in subsequent releasing of the MEMS device and implanting MEMS device and MEMS electrode contacts. The MEMS device and MEMS electrode can be isolated using trench isolation. An anchor can be formed to support the MEMS device contacts.
Other objects, features and advantages of the present invention will become apparent from the detailed description of the invention which follows, when considered in light of the accompanying drawings in which:
FIG, 6 is a simplified cross-sectional view similar to FIGS. 1-5 , but showing a sixth stage of formation in accordance with a non-limiting example.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
The light flow adaptation shown in FIGS. 1-7 could include a 20 micrometer silicon layer on oxide structure and a polysilicon “filling” for electrodes followed by an oxide “filling” and a polysilicon protection layer for hydrofluoric (HF) acid release. A silicon nitride capping layer can be used as an etch stop for subsequent silicon etching. A polysilicon seed layer can be used for epitaxial growth and used for standard integrated circuit (IC) processing, thus, forming the embedded MEMS semiconductor substrate useful as a starting material for subsequent semiconductor device manufacturing. It forms an integrated circuit (IC) ready chip. There can be a following flow with a mix of spin-on-glass (SOG) and standard areas for the IC ready silicon.
At a wafer level, the example shown in FIGS. 1-7 could have a contact-to-input electrode, a contact-to-output electrode, and a contact-to-resonator anchor. In this example, the final product is a ready-to-IC process MEMS having in this example the form of a silicon resonator that can be used for a large amount of standard circuits to deliver to markets the various circuits with an embedded clock.
The area used in the wafer depends on the specific schematics of the stand-alone MEMS. The embedded MEMS area can be used for the processing on the product and depending on the electrical needs of any supporting circuit, the embedded MEMS area can be dedicated to interconnect and not active devices. There are some specific examples such as a CMOS circuit on top of the MEMS where all the wafer surface can be used. An example of a resonator on a precise analog technology can have the surface of the resonator of about 0.2 mm2 and a typical circuit surface area of about 10 mm2. The area used for the embedded MEMS can be increased to give more flexibility to supporting circuit layout by not using the connections.
The embedded MEMS technology as will be described allows the development and manufacturing of MEMS technologies as a specific activity and the reuse of standard technologies, only changing the starting material and design rules while allowing a new spectrum of applications on MEMS and IC capabilities. Significant alternatives to IC and MEMS emerging applications are generally developed with a post processing methodology at an assembly level. The embedded MEMS substrate can allow various business opportunities that have not heretofore been allowed compared to the SOI business applications. The embedded silicon resonator as described can be extended to embedded mechanical sensors and a large spectrum of new applications as non-limiting examples.
Referring now to FIG. 1 , there is shown the simplified cross-sectional view of an embedded MEMS semiconductor substrate in a first stage of processing when the MEMS device as a resonator has been formed in the semiconductor, silicon substrate 20 known to those skilled in the art. A buried silicon dioxide layer 22 is formed as a sacrificial layer and labelled as the buried oxide layer as illustrated. The MEMS device is shown at 24 as a resonator and formed in the silicon substrate 20 and shown only diagrammatically as a resonator. Many different types of MEMS devices could be formed in the silicon substrate, including the resonator as illustrated. Other examples of MEMS devices include piezoelectric and thermal bubble printer ejectors, accelerometers, gyroscopes, silicon pressure sensors, display devices, optical switches and other similar devices. An electrode anchor is illustrated at 30 and another anchor as a MEMS device anchor is shown at 32 and positioned over the buried sacrificial layer 22. A thermal oxide 40 has been formed in previously fabricated trenches 42 to form the boundary for the electrode anchor 30 and the MEMS device anchor 32. A polysilicon MEMS electrode is illustrated at 44 and supported by an oxide layer 46. A planarizing layer 48 has been formed over the substrate 20, MEMS device 24 and MEMS electrode 44 and formed as a TEOS (tetraethyl orthosilicate) with a combined spin-on-glass (SOG) and TEOS layer that can include processing with chemical mechanical planarization (polishing).
As illustrated, a polysilicon protection layer 50 is applied as a deposit over the planarizing layer 48, which is followed by the application of a silicon nitride capping layer 52 over the polysilicon protection layer 50. This is followed by a polysilicon seed layer 54 over the silicon nitride capping layer 52. This top polysilicon seed layer 54, in one non-limiting aspect, can be about 0.5 um plus have a selectivity to hydrofluoric acid release.
As shown in FIG. 2 , an openings (or vias) 60, 62 formed for oxide release and forming contacts. A fill/release material thickness corresponds to X and a contact/release dimension corresponds to Y. X can be less than Y if the release opening is going to be a contact opening and Y can be much less than X if the contact opening is done before the release opening.
Other applications for the process as described could be module integration by packaging including a MEMS microphone and IC amplifier adjacent to each other and a MEMS pressure sensor and IC amplifier with a membrane and air cavity with the MEMS integrated prior to the integrated circuit. Many other applications are possible. Typically, the process as described is not used with MEMS structures that require metal layers or precise implanted dopants because the thermal processing of IC's will require up to 100° C. processing temperature.
Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.
Claims (37)
1. A method of forming an embedded MEMS semiconductor substrate used as a starting material for subsequent semiconductor device processing, comprising:
forming a MEMS device in a semiconductor substrate that includes at least one MEMS electrode and a buried silicon dioxide sacrificial layer used for releasing the MEMS;
applying a planarizing layer over the substrate, MEMS device and MEMS electrode;
applying a polysilicon protection layer over the planarizing layer;
applying a silicon nitride capping layer over the polysilicon protection layer;
applying a polysilicon seed layer over the silicon nitride capping layer;
releasing the MEMS device by removing at least a portion of the buried silicon dioxide sacrificial layer; and
growing an epitaxial layer over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.
2. The method according to claim 1 , wherein the subsequent semiconductor wafer processing comprises one of CMOS, BiCMOS, BCD and NV memory processing.
3. The method according to claim 1 , which further comprises removing the buried oxide sacrificial layer using hydrofluoric acid releasing.
4. The method according to claim 1 , which further comprises removing the planarizing layer by etching.
5. The method according to claim 1 , which further comprises forming the planarizing layer as a TEOS and spin-on-glass layer.
6. The method according to claim 1 , which further comprises forming the capping layer us a silicon nitride insulating layer.
7. The method according to claim 1 , which further comprises forming the MEMS device as a resonator.
8. The method according to claim 1 , which further comprises forming an electrode anchor supporting the at least one MEMS electrode.
9. The method according to claim 8 , which further comprises forming an anchor to isolate the MEMS device.
10. The method according to claim 1 , which further comprises forming vias within the protection, nitride capping and seed layers for use in subsequent releasing of the MEMS device and implanting MEMS device and MEMS electrode contacts.
11. The method according to claim 1 , which further comprises isolating any MEMS device and MEMS electrode contacts using trench isolation.
12. The method according to claim 1 , which further comprises removing the planarizing layer before growing an epitaxial layer.
13. A method of forming an embedded MEMS semiconductor substrate used as a starting material for subsequent semiconductor device processing, comprising:
forming a MEMS device in a semiconductor substrate and at least one MEMS electrode and which includes a buried silicon dioxide sacrificial layer;
releasing the MEMS device by removing the buried sacrificial layer and applying a polysilicon seed layer and capping layer over the MEMS device and at least one MEMS electrode while also forming vias using photolithography and implanting deep contacts to the MEMS device and any MEMS electrodes and forming trench isolation of such deep contacts; and
growing an epitaxial layer over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.
14. The method according to claim 13 , wherein the subsequent semiconductor wafer processing comprises one of CMOS, BiCMOS, BCD and NV memory processing.
15. The method according to claim 14 , and further comprising the step of applying planarizing and capping layers over the substrate, MEMS device and MEMS electrode before releasing the MEMS device.
16. The method according to claim 15 , which further comprises forming the planarizing layer as a TEOS and spin-on-glass layer.
17. The method according to claim 13 , which further comprises removing the buried oxide sacrificial layer using hydrofluoric acid releasing.
18. The method according to claim 13 , which further comprises forming the MEMS device as a resonator.
19. The method according to claim 13 , which further comprises isolating any MEMS device and MEMS electrode contacts using trench isolation.
20. A method of forming an embedded MEMS semiconductor substrate to be used as a starting material for subsequent semiconductor device processing, comprising:
forming a MEMS device in a semiconductor substrate that includes at least one MEMS electrode and a buried sacrificial layer;
forming a planarizing layer over the semiconductor substrate and the MEMS device;
forming a protection layer over the planarizing layer;
forming a capping layer over the protection layer;
forming a seed layer over the capping layer;
releasing the at least one MEMS electrode by removing at least a portion of the buried sacrificial layer; and
growing a semiconductor layer over the seed layer to be used for subsequent semiconductor device processing.
21. The method according to claim 20, wherein the subsequent semiconductor device processing comprises one of CMOS, BiCMOS, BCD and NV memory processing.
22. The method according to claim 20, which further comprises removing the buried sacrificial layer using hydrofluoric acid releasing.
23. The method according to claim 20, which further comprises removing the planarizing layer by etching.
24. The method according to claim 20, which further comprises forming the planarizing layer as a TEOS and spin-on-glass layer.
25. The method according to claim 20, which further comprises forming the capping layer as a silicon nitride insulating layer.
26. The method according to claim 20, which further comprises forming the MEMS device as a resonator.
27. The method according to claim 20, which further comprises forming an electrode anchor supporting the at least one MEMS electrode.
28. The method according to claim 27, which further comprises forming an anchor to isolate the MEMS device.
29. The method according to claim 20, which further comprises forming vias within the protection, capping and seed layers for use in subsequent releasing of the at least one MEMS electrode and implanting MEMS device and MEMS electrode contacts.
30. The method according to claim 29, which further comprises isolating the MEMS device and MEMS electrode contacts using trench isolation.
31. The method according to claim 20, which further comprises removing the planarizing layer before growing a semiconductor layer.
32. A method of forming an embedded MEMS semiconductor substrate to be used as a starting material for subsequent semiconductor device processing, comprising:
forming a MEMS device in a semiconductor substrate that includes at least one MEMS electrode and a buried sacrificial layer;
releasing the at least one MEMS electrode by removing the buried sacrificial layer and applying a seed layer and capping layer over the MEMS device and at least one MEMS electrode;
forming trench isolated contacts to the MEMS device and any MEMS electrode; and
growing a semiconductor layer over the seed layer to be used for subsequent semiconductor device processing.
33. The method according to claim 32, wherein the subsequent semiconductor device processing comprises one of CMOS, BiCMOS, BCD and NV memory processing.
34. The method according to claim 33, and further comprising the step of applying planarizing and capping layers over the semiconductor substrate, MEMS device and at least one MEMS electrode before releasing the MEMS device.
35. The method according to claim 33, which further comprises forming the planarizing layer as a TEOS and spin-on-glass layer.
36. The method according to claim 32, which further comprises removing the buried sacrificial layer using hydrofluoric acid releasing.
37. The method according to claim 32, which further comprises forming the MEMS device as a resonator.
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US13/890,668 USRE45286E1 (en) | 2008-12-10 | 2013-05-09 | Embedded microelectromechanical systems (MEMS) semiconductor substrate and related method of forming |
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US12/331,521 US7943410B2 (en) | 2008-12-10 | 2008-12-10 | Embedded microelectromechanical systems (MEMS) semiconductor substrate and related method of forming |
US13/890,668 USRE45286E1 (en) | 2008-12-10 | 2013-05-09 | Embedded microelectromechanical systems (MEMS) semiconductor substrate and related method of forming |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8193595B2 (en) | 2009-12-31 | 2012-06-05 | Stmicroelectronics, Inc. | Method of forming a die having an IC region adjacent a MEMS region |
US8927312B2 (en) | 2012-10-16 | 2015-01-06 | International Business Machines Corporation | Method of fabricating MEMS transistors on far back end of line |
US9449867B2 (en) * | 2014-06-17 | 2016-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | VHF etch barrier for semiconductor integrated microsystem |
US10850976B2 (en) * | 2018-09-21 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making ohmic contact on low doped bulk silicon for optical alignment |
Citations (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5186745A (en) | 1991-02-04 | 1993-02-16 | Motorola, Inc. | Teos based spin-on-glass and processes for making and using the same |
US5645684A (en) * | 1994-03-07 | 1997-07-08 | The Regents Of The University Of California | Multilayer high vertical aspect ratio thin film structures |
US6027950A (en) | 1996-02-13 | 2000-02-22 | Vlsi Technology, Inc. | Method for achieving accurate SOG etchback selectivity |
US6069392A (en) * | 1997-04-11 | 2000-05-30 | California Institute Of Technology | Microbellows actuator |
US6448604B1 (en) * | 2000-09-12 | 2002-09-10 | Robert Bosch Gmbh | Integrated adjustable capacitor |
US6872319B2 (en) * | 2002-09-30 | 2005-03-29 | Rockwell Scientific Licensing, Llc | Process for high yield fabrication of MEMS devices |
US6958566B2 (en) * | 2001-08-16 | 2005-10-25 | The Regents Of The University Of Michigan | Mechanical resonator device having phenomena-dependent electrical stiffness |
US7023065B2 (en) | 2002-08-07 | 2006-04-04 | Georgia Tech Research Corporation | Capacitive resonators and methods of fabrication |
US7022542B2 (en) * | 2002-12-24 | 2006-04-04 | Stmicroelectronics S.R.L. | Manufacturing method of a microelectromechanical switch |
US20060234412A1 (en) | 2005-04-19 | 2006-10-19 | Hewlett-Packard Development Company, L.P. Intellectual Property Administration | MEMS release methods |
US20060278942A1 (en) * | 2005-06-14 | 2006-12-14 | Innovative Micro Technology | Antistiction MEMS substrate and method of manufacture |
US7202764B2 (en) * | 2003-07-08 | 2007-04-10 | International Business Machines Corporation | Noble metal contacts for micro-electromechanical switches |
US7230315B2 (en) * | 2000-02-29 | 2007-06-12 | Stmicroelectronics S.R.L. | Integrated chemical microreactor with large area channels and manufacturing process thereof |
US7256107B2 (en) | 2004-05-04 | 2007-08-14 | The Regents Of The University Of California | Damascene process for use in fabricating semiconductor structures having micro/nano gaps |
US20070236313A1 (en) * | 2005-08-26 | 2007-10-11 | Innovative Micro Technology | Dual substrate electrostatic MEMS switch with hermetic seal and method of manufacture |
US20070281381A1 (en) * | 2006-05-31 | 2007-12-06 | Georgia Tech Research Corporation | Method for sealing and backside releasing of microelectromechanical systems |
US20080054759A1 (en) * | 2006-08-11 | 2008-03-06 | Farrokh Ayazi | Wafer-level encapsulation and sealing of electrostatic transducers |
US20080099860A1 (en) * | 2006-11-01 | 2008-05-01 | Alida Wuertz | Semiconductor array and method for manufacturing a semiconductor array |
US20080164542A1 (en) * | 2007-01-05 | 2008-07-10 | Miradia Inc. | Methods and systems for wafer level packaging of mems structures |
US20090267166A1 (en) * | 2008-04-23 | 2009-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a device with a cavity |
US20090275163A1 (en) * | 2008-04-30 | 2009-11-05 | Joseph Damian Gordon Lacey | System and Method of Encapsulation |
US20100013031A1 (en) * | 2008-07-15 | 2010-01-21 | Florian Schoen | MEMS Substrates, Devices, and Methods of Manufacture Thereof |
US20100052081A1 (en) * | 2006-11-20 | 2010-03-04 | Nxp, B.V. | A sealing structure and method of manufacturing the same |
US20100116043A1 (en) * | 2008-11-10 | 2010-05-13 | Thorsten Pannek | Component and production method for a component |
US8323982B2 (en) * | 2007-01-11 | 2012-12-04 | Valencell, Inc. | Photoelectrocatalytic fluid analyte sensors and methods of fabricating and using same |
US20130102101A1 (en) * | 2010-09-10 | 2013-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer Level Packaging |
-
2008
- 2008-12-10 US US12/331,521 patent/US7943410B2/en not_active Ceased
-
2013
- 2013-05-09 US US13/890,668 patent/USRE45286E1/en active Active
Patent Citations (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5186745A (en) | 1991-02-04 | 1993-02-16 | Motorola, Inc. | Teos based spin-on-glass and processes for making and using the same |
US5645684A (en) * | 1994-03-07 | 1997-07-08 | The Regents Of The University Of California | Multilayer high vertical aspect ratio thin film structures |
US6027950A (en) | 1996-02-13 | 2000-02-22 | Vlsi Technology, Inc. | Method for achieving accurate SOG etchback selectivity |
US6069392A (en) * | 1997-04-11 | 2000-05-30 | California Institute Of Technology | Microbellows actuator |
US7230315B2 (en) * | 2000-02-29 | 2007-06-12 | Stmicroelectronics S.R.L. | Integrated chemical microreactor with large area channels and manufacturing process thereof |
US6448604B1 (en) * | 2000-09-12 | 2002-09-10 | Robert Bosch Gmbh | Integrated adjustable capacitor |
US6958566B2 (en) * | 2001-08-16 | 2005-10-25 | The Regents Of The University Of Michigan | Mechanical resonator device having phenomena-dependent electrical stiffness |
US7023065B2 (en) | 2002-08-07 | 2006-04-04 | Georgia Tech Research Corporation | Capacitive resonators and methods of fabrication |
US6872319B2 (en) * | 2002-09-30 | 2005-03-29 | Rockwell Scientific Licensing, Llc | Process for high yield fabrication of MEMS devices |
US7022542B2 (en) * | 2002-12-24 | 2006-04-04 | Stmicroelectronics S.R.L. | Manufacturing method of a microelectromechanical switch |
US7202764B2 (en) * | 2003-07-08 | 2007-04-10 | International Business Machines Corporation | Noble metal contacts for micro-electromechanical switches |
US7256107B2 (en) | 2004-05-04 | 2007-08-14 | The Regents Of The University Of California | Damascene process for use in fabricating semiconductor structures having micro/nano gaps |
US20060234412A1 (en) | 2005-04-19 | 2006-10-19 | Hewlett-Packard Development Company, L.P. Intellectual Property Administration | MEMS release methods |
US20060278942A1 (en) * | 2005-06-14 | 2006-12-14 | Innovative Micro Technology | Antistiction MEMS substrate and method of manufacture |
US20070236313A1 (en) * | 2005-08-26 | 2007-10-11 | Innovative Micro Technology | Dual substrate electrostatic MEMS switch with hermetic seal and method of manufacture |
US20070281381A1 (en) * | 2006-05-31 | 2007-12-06 | Georgia Tech Research Corporation | Method for sealing and backside releasing of microelectromechanical systems |
US20080054759A1 (en) * | 2006-08-11 | 2008-03-06 | Farrokh Ayazi | Wafer-level encapsulation and sealing of electrostatic transducers |
US20080099860A1 (en) * | 2006-11-01 | 2008-05-01 | Alida Wuertz | Semiconductor array and method for manufacturing a semiconductor array |
US20100052081A1 (en) * | 2006-11-20 | 2010-03-04 | Nxp, B.V. | A sealing structure and method of manufacturing the same |
US20080164542A1 (en) * | 2007-01-05 | 2008-07-10 | Miradia Inc. | Methods and systems for wafer level packaging of mems structures |
US8323982B2 (en) * | 2007-01-11 | 2012-12-04 | Valencell, Inc. | Photoelectrocatalytic fluid analyte sensors and methods of fabricating and using same |
US20090267166A1 (en) * | 2008-04-23 | 2009-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a device with a cavity |
US20090275163A1 (en) * | 2008-04-30 | 2009-11-05 | Joseph Damian Gordon Lacey | System and Method of Encapsulation |
US20100013031A1 (en) * | 2008-07-15 | 2010-01-21 | Florian Schoen | MEMS Substrates, Devices, and Methods of Manufacture Thereof |
US20100116043A1 (en) * | 2008-11-10 | 2010-05-13 | Thorsten Pannek | Component and production method for a component |
US20130102101A1 (en) * | 2010-09-10 | 2013-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer Level Packaging |
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US7943410B2 (en) | 2011-05-17 |
US20100140724A1 (en) | 2010-06-10 |
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