USRE46005E1 - Method and apparatus for enabling a timing synchronization circuit - Google Patents
Method and apparatus for enabling a timing synchronization circuit Download PDFInfo
- Publication number
- USRE46005E1 USRE46005E1 US11/800,520 US80052007A USRE46005E US RE46005 E1 USRE46005 E1 US RE46005E1 US 80052007 A US80052007 A US 80052007A US RE46005 E USRE46005 E US RE46005E
- Authority
- US
- United States
- Prior art keywords
- clock signal
- signal
- input clock
- responsive
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
Abstract
Description
Claims (63)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/800,520 USRE46005E1 (en) | 2002-06-11 | 2007-05-04 | Method and apparatus for enabling a timing synchronization circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/167,195 US6891415B2 (en) | 2002-06-11 | 2002-06-11 | Method and apparatus for enabling a timing synchronization circuit |
US11/800,520 USRE46005E1 (en) | 2002-06-11 | 2007-05-04 | Method and apparatus for enabling a timing synchronization circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/167,195 Reissue US6891415B2 (en) | 2002-06-11 | 2002-06-11 | Method and apparatus for enabling a timing synchronization circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE46005E1 true USRE46005E1 (en) | 2016-05-17 |
Family
ID=29710839
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/167,195 Ceased US6891415B2 (en) | 2002-06-11 | 2002-06-11 | Method and apparatus for enabling a timing synchronization circuit |
US11/800,520 Expired - Lifetime USRE46005E1 (en) | 2002-06-11 | 2007-05-04 | Method and apparatus for enabling a timing synchronization circuit |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/167,195 Ceased US6891415B2 (en) | 2002-06-11 | 2002-06-11 | Method and apparatus for enabling a timing synchronization circuit |
Country Status (1)
Country | Link |
---|---|
US (2) | US6891415B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10447493B2 (en) | 2016-07-26 | 2019-10-15 | Honeywell International Inc. | MAC and physical layer techniques for enabling communications on shared physical medium with multi-drop capability |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7084686B2 (en) * | 2004-05-25 | 2006-08-01 | Micron Technology, Inc. | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal |
US7216247B2 (en) * | 2004-08-05 | 2007-05-08 | Texas Instruments Incorporated | Methods and systems to reduce data skew in FIFOs |
US7221201B2 (en) * | 2004-08-11 | 2007-05-22 | Micron Technology, Inc. | Fast-locking digital phase locked loop |
US7078951B2 (en) * | 2004-08-27 | 2006-07-18 | Micron Technology, Inc. | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal |
US7428284B2 (en) * | 2005-03-14 | 2008-09-23 | Micron Technology, Inc. | Phase detector and method providing rapid locking of delay-lock loops |
US7212053B2 (en) * | 2005-05-12 | 2007-05-01 | Micron Technology, Inc. | Measure-initialized delay locked loop with live measurement |
US7620839B2 (en) * | 2005-12-13 | 2009-11-17 | Lattice Semiconductor Corporation | Jitter tolerant delay-locked loop circuit |
US7936789B2 (en) * | 2006-03-31 | 2011-05-03 | Intel Corporation | Disparate clock domain synchronization |
US7277357B1 (en) | 2006-06-05 | 2007-10-02 | Micron Technology, Inc. | Method and apparatus for reducing oscillation in synchronous circuits |
US7864625B2 (en) * | 2008-10-02 | 2011-01-04 | International Business Machines Corporation | Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator |
US8555124B2 (en) * | 2010-06-07 | 2013-10-08 | Arm Limited | Apparatus and method for detecting an approaching error condition |
US20220358026A1 (en) * | 2019-07-12 | 2022-11-10 | Sony Group Corporation | Information processing device, information processing method, and program |
Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5068628A (en) | 1990-11-13 | 1991-11-26 | Level One Communications, Inc. | Digitally controlled timing recovery loop |
US5386159A (en) | 1993-06-30 | 1995-01-31 | Harris Corporation | Glitch suppressor circuit and method |
US5771264A (en) * | 1996-08-29 | 1998-06-23 | Altera Corporation | Digital delay lock loop for clock signal frequency multiplication |
US5935257A (en) | 1997-05-16 | 1999-08-10 | Fujitsu Limited | Skew-reduction circuit and semiconductor device |
US20010044888A1 (en) * | 1999-07-19 | 2001-11-22 | Micron Technology, Inc. | Memory device with synchronized output path |
US20020000851A1 (en) | 1998-09-04 | 2002-01-03 | Hitachi, Ltd. | Timing-control circuit device and clock distribution system |
US6337590B1 (en) * | 1997-04-30 | 2002-01-08 | Mosaid Technologies Incorporated | Digital delay locked loop |
US6448756B1 (en) * | 2000-08-30 | 2002-09-10 | Micron Technology, Inc. | Delay line tap setting override for delay locked loop (DLL) testability |
US20020140471A1 (en) * | 2001-03-30 | 2002-10-03 | Fiscus Timothy E. | Pre-divider architecture for low power in a digital delay locked loop |
US6539072B1 (en) * | 1997-02-06 | 2003-03-25 | Rambus, Inc. | Delay locked loop circuitry for clock delay adjustment |
US6549041B2 (en) * | 2000-08-28 | 2003-04-15 | Micron Technology, Inc. | Scheme for delay locked loop reset protection |
US6556643B2 (en) * | 2001-08-27 | 2003-04-29 | Micron Technology, Inc. | Majority filter counter circuit |
US6593786B2 (en) * | 2001-06-30 | 2003-07-15 | Hynix Semiconductor Inc. | Register controlled DLL reducing current consumption |
US6605969B2 (en) * | 2001-10-09 | 2003-08-12 | Micron Technology, Inc. | Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers |
US6621315B2 (en) * | 2001-11-07 | 2003-09-16 | Samsung Electronics Co., Ltd. | Delay locked loop circuit and method having adjustable locking resolution |
US6774687B2 (en) * | 2002-03-11 | 2004-08-10 | Micron Technology, Inc. | Method and apparatus for characterizing a delay locked loop |
US6779126B1 (en) * | 2000-08-31 | 2004-08-17 | Micron Technology, Inc. | Phase detector for all-digital phase locked and delay locked loops |
US20050001662A1 (en) * | 2002-03-22 | 2005-01-06 | Kizer Jade M. | System with phase jumping locked loop circuit |
US20050206419A1 (en) * | 2002-03-22 | 2005-09-22 | Kizer Jade M | Locked loop with dual rail regulation |
US7035366B2 (en) * | 2001-07-12 | 2006-04-25 | Renesas Technology Corp. | Delay locked loop circuit and its control method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5068528A (en) * | 1990-08-28 | 1991-11-26 | The Boeing Company | Encoded surface position sensor with multiple wavelengths and reference beam |
US5910740A (en) * | 1997-06-18 | 1999-06-08 | Raytheon Company | Phase locked loop having memory |
-
2002
- 2002-06-11 US US10/167,195 patent/US6891415B2/en not_active Ceased
-
2007
- 2007-05-04 US US11/800,520 patent/USRE46005E1/en not_active Expired - Lifetime
Patent Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5068628A (en) | 1990-11-13 | 1991-11-26 | Level One Communications, Inc. | Digitally controlled timing recovery loop |
US5386159A (en) | 1993-06-30 | 1995-01-31 | Harris Corporation | Glitch suppressor circuit and method |
US5771264A (en) * | 1996-08-29 | 1998-06-23 | Altera Corporation | Digital delay lock loop for clock signal frequency multiplication |
US6539072B1 (en) * | 1997-02-06 | 2003-03-25 | Rambus, Inc. | Delay locked loop circuitry for clock delay adjustment |
US6337590B1 (en) * | 1997-04-30 | 2002-01-08 | Mosaid Technologies Incorporated | Digital delay locked loop |
US5935257A (en) | 1997-05-16 | 1999-08-10 | Fujitsu Limited | Skew-reduction circuit and semiconductor device |
US20020000851A1 (en) | 1998-09-04 | 2002-01-03 | Hitachi, Ltd. | Timing-control circuit device and clock distribution system |
US20010044888A1 (en) * | 1999-07-19 | 2001-11-22 | Micron Technology, Inc. | Memory device with synchronized output path |
US6549041B2 (en) * | 2000-08-28 | 2003-04-15 | Micron Technology, Inc. | Scheme for delay locked loop reset protection |
US6448756B1 (en) * | 2000-08-30 | 2002-09-10 | Micron Technology, Inc. | Delay line tap setting override for delay locked loop (DLL) testability |
US6779126B1 (en) * | 2000-08-31 | 2004-08-17 | Micron Technology, Inc. | Phase detector for all-digital phase locked and delay locked loops |
US20020140471A1 (en) * | 2001-03-30 | 2002-10-03 | Fiscus Timothy E. | Pre-divider architecture for low power in a digital delay locked loop |
US6593786B2 (en) * | 2001-06-30 | 2003-07-15 | Hynix Semiconductor Inc. | Register controlled DLL reducing current consumption |
US7035366B2 (en) * | 2001-07-12 | 2006-04-25 | Renesas Technology Corp. | Delay locked loop circuit and its control method |
US6556643B2 (en) * | 2001-08-27 | 2003-04-29 | Micron Technology, Inc. | Majority filter counter circuit |
US6605969B2 (en) * | 2001-10-09 | 2003-08-12 | Micron Technology, Inc. | Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers |
US6621315B2 (en) * | 2001-11-07 | 2003-09-16 | Samsung Electronics Co., Ltd. | Delay locked loop circuit and method having adjustable locking resolution |
US6774687B2 (en) * | 2002-03-11 | 2004-08-10 | Micron Technology, Inc. | Method and apparatus for characterizing a delay locked loop |
US20040232962A1 (en) * | 2002-03-11 | 2004-11-25 | Gomm Tyler J. | Method and apparatus for characterizing a delay locked loop |
US20050001662A1 (en) * | 2002-03-22 | 2005-01-06 | Kizer Jade M. | System with phase jumping locked loop circuit |
US20050206419A1 (en) * | 2002-03-22 | 2005-09-22 | Kizer Jade M | Locked loop with dual rail regulation |
US20110156776A1 (en) * | 2002-03-22 | 2011-06-30 | Rambus Inc. | Locked Loop Circuit With Clock Hold Function |
Non-Patent Citations (2)
Title |
---|
Gomm, Tyler, "Design of a Delay-Locked Loop With a DAC-Controlled Analaog Delay Line", Mar. 2001. * |
Miyazaki et al.; Timing-Control Circuit Device and Clock distribution System, U.S. Pat. Appl. Publication No. US2002/0000851 A1, Publication Date: Jan. 3, 2002, 39 pages. |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10447493B2 (en) | 2016-07-26 | 2019-10-15 | Honeywell International Inc. | MAC and physical layer techniques for enabling communications on shared physical medium with multi-drop capability |
Also Published As
Publication number | Publication date |
---|---|
US20030227305A1 (en) | 2003-12-11 |
US6891415B2 (en) | 2005-05-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 |
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FPAY | Fee payment |
Year of fee payment: 12 |
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AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 |
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AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 |
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AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001 Effective date: 20180629 |
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AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001 Effective date: 20190731 |
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AS | Assignment |
Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 |