UST943001I4 - - Google Patents
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- Publication number
- UST943001I4 UST943001I4 US47907474A UST943001I4 US T943001 I4 UST943001 I4 US T943001I4 US 47907474 A US47907474 A US 47907474A US T943001 I4 UST943001 I4 US T943001I4
- Authority
- US
- United States
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US47907474 UST943001I4 (en) | 1974-06-13 | 1974-06-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US47907474 UST943001I4 (en) | 1974-06-13 | 1974-06-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UST943001I4 true UST943001I4 (en) | 1976-02-03 |
Family
ID=23902563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US47907474 Pending UST943001I4 (en) | 1974-06-13 | 1974-06-13 |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | UST943001I4 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4263651A (en) | 1979-05-21 | 1981-04-21 | International Business Machines Corporation | Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks |
| US5229953A (en) * | 1989-10-13 | 1993-07-20 | Hitachi, Ltd. | Method of and apparatus for assigning logic gates to a plurality of hardware components |
| US5416717A (en) * | 1989-09-06 | 1995-05-16 | Hitachi, Ltd. | Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern |
| US5461577A (en) * | 1987-08-04 | 1995-10-24 | Texas Instruments Incorporated | Comprehensive logic circuit layout system |
| US5617573A (en) * | 1994-05-23 | 1997-04-01 | Xilinx, Inc. | State splitting for level reduction |
| US5629859A (en) * | 1992-10-21 | 1997-05-13 | Texas Instruments Incorporated | Method for timing-directed circuit optimizations |
| US6345378B1 (en) * | 1995-03-23 | 2002-02-05 | Lsi Logic Corporation | Synthesis shell generation and use in ASIC design |
-
1974
- 1974-06-13 US US47907474 patent/UST943001I4/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4263651A (en) | 1979-05-21 | 1981-04-21 | International Business Machines Corporation | Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks |
| US5461577A (en) * | 1987-08-04 | 1995-10-24 | Texas Instruments Incorporated | Comprehensive logic circuit layout system |
| US5416717A (en) * | 1989-09-06 | 1995-05-16 | Hitachi, Ltd. | Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern |
| US5229953A (en) * | 1989-10-13 | 1993-07-20 | Hitachi, Ltd. | Method of and apparatus for assigning logic gates to a plurality of hardware components |
| US5629859A (en) * | 1992-10-21 | 1997-05-13 | Texas Instruments Incorporated | Method for timing-directed circuit optimizations |
| US5617573A (en) * | 1994-05-23 | 1997-04-01 | Xilinx, Inc. | State splitting for level reduction |
| US6345378B1 (en) * | 1995-03-23 | 2002-02-05 | Lsi Logic Corporation | Synthesis shell generation and use in ASIC design |