WO1981003396A1 - Integrated circuit package with multi-contact pins - Google Patents

Integrated circuit package with multi-contact pins Download PDF

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Publication number
WO1981003396A1
WO1981003396A1 PCT/US1981/000610 US8100610W WO8103396A1 WO 1981003396 A1 WO1981003396 A1 WO 1981003396A1 US 8100610 W US8100610 W US 8100610W WO 8103396 A1 WO8103396 A1 WO 8103396A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
conductors
pins
circuit package
housing
Prior art date
Application number
PCT/US1981/000610
Other languages
French (fr)
Inventor
R Zakhariya
Original Assignee
Ncr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Co filed Critical Ncr Co
Priority to AU71766/81A priority Critical patent/AU7176681A/en
Publication of WO1981003396A1 publication Critical patent/WO1981003396A1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1015—Plug-in assemblages of components, e.g. IC sockets having exterior leads
    • H05K7/103—Plug-in assemblages of components, e.g. IC sockets having exterior leads co-operating by sliding, e.g. DIP carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Definitions

  • This invention relates to integrated circuit packages of the kind having a plurality of pins for providing external electrical connections.
  • an integrated circuit package of the kind specified characterized in that at least one of said pins includes a plurality of conductors so that a plurality of external electrical connections are made at said one of said pins.
  • Fig. 1 is a perspective view of one embodiment of the present invention, including an integrated circuit package and external connectors for engaging each pin on the integrated circuit package.
  • Fig. 2 is the same view as Fig. 1, with the external connectors removed and with portions of the integrated circuit package broken away to expose details thereof.
  • Fig. 3 is a sectional view taken along the line III-III of Fig. 2.
  • Fig. 4 is a perspective view illustrating a • second embodiment of the present invention, including a portion of an integrated circuit package and a connector for engaging a pin on the integrated circuit package.
  • Fig. 5 is a perspective view illustrating a third embodiment of the present invention, including a portion of an integrated circuit package and a connector for engaging a pin on the integrated circuit package.
  • Fig. 6 is a sectional view taken along the line VI-VI of Fig. 5.
  • the integrated circuit package 10 includes a body or housing 12 and a plurality of pins 14 depending from the sides of the housing.
  • the housing 12 supports and encloses a semi ⁇ conductor or integrated circuit chip (not shown in Fig. 1) that can have a large number of circuit components fabricated thereon for performing logic, processing, memory or other functions.
  • a semi ⁇ conductor or integrated circuit chip (not shown in Fig. 1) that can have a large number of circuit components fabricated thereon for performing logic, processing, memory or other functions.
  • the present invention is not concerned with the nature of the integrated circuit chip itself, it being understood that such a chip could be ma"de in any one of many con ⁇ ventional techniques for performing any one of many conventional functions.
  • the integrated circuit package could be used in a computer or any other type of electronic or electrical system.
  • the housing 12 in Fig. 1 has three package layers, including a cap or top layer 20, a thin middle - layer 22, and a bottom or support layer 24. As can be seen, the middle layer 22 overlies the bottom layer 24, and the top layer 20, in turn, overlies the middle layer 22.
  • the pins 14 generally depend from the housing 12 at the middle layer 22, and are each constructed so as to have an elongate insulating member or substrate 30 with conductive material located to form two conductors' 32 and 34, the conductors spaced apart with one on each of two opposing sides of the insulating member 30. As will be described in greater detail later with reference to Fig. 2, the insulating member 30 of each pin 14 may be integral with the layer 22 of the housing 12.
  • pin conductors 32 and 34 may be integral with conductive patterns or leads 40 (shown only in Fig. 2) that are located on each side of * the package layer 22 and that permit access to the in ⁇ tegrated circuit chip- within the housing 12 for purposes of transferring or carrying signals to and from the in ⁇ tegrated circuit chip.
  • a connector assembly 0 for use with the integrated circuit package 10 includes a plurality of connectors 42 that are positioned or aligned so as to each receive one of the pins 14.
  • Each connector 42 includes two opposing contacts 46 and 48, with each of the contacts 46 and 48 having an arcuate pin-engaging end 50 for making electrical contact with one of the conductors 32 and 34 on each pin 14.
  • Each of the contacts 46 and 48 may be connected to external power, data, address or other signal lines (not shown) .
  • Figs. 2 and 3 there is shown in greater detail the construction of the integrated circuit package 10.
  • each of the pin conductors 32 and 34 is formed integrally with and, hence, electrically connected to one of the previously- mentioned conductive leads 40 that are positioned on each side of the package layer 22.
  • the conductive leads 40 all converge to an opened center portion 56 (Fig. 3) . of the housing 12 formed by the middle package layer 22 and enclosed by the top and bottom package layers 20 and 24.
  • An integrated circuit chip 60 is mounted on layer 24 at the opened portion 56 so that, as conven ⁇ tional, connecting wires 62 may electrically connect each conductive lead 40 to an electrode or pad on the chip 60.
  • the package layers 20, 22 and 24 may be formed in a conventional fashion from ceramic, plastic or other insulating or dielectric material.
  • the conductive leads 40 may likewise be formed in a conventional fashion, for example, by being stamped from a conductive sheet as a lead frame and then suitably bent and milled to form each one of the leads 40 and conductors 32 and 34.
  • other suitable forms of constructing the inte- grated circuit package 10 could be employed, such as molding the entire housing 12 about the chip 60 as a single piece.
  • the leads 40 in the conductive layers 32 and 34 could be formed using a printed circuit board process, by starting with a relatively thin (.1 mm) dielectric base, as the layer 22, and then depositing* conductive material on both sides of the base to form the leads 40 and conductors 32 and 34.
  • the base could be then milled to form projections having the conductors 32 and 34 thereon, and the projections could be heated and bent to form the pins 14.
  • the chip could then be mounted and electrically connected, and then the package capped or encapsulated in plastic to form the finished integrated circuit package 10.
  • Figs. 1, 2 and 3 is able to provide twice as many exter ⁇ nal electrical connections as there are pins 14. More particularly, as seen best in Figs. 1 and 2, by spacing the conductors 32 and 34 at each pin 14 in a direction that is generally perpendicular to the direction in which the pins are spaced along each side of the housing 12, the integrated circuit package 10 is made to occupy no more area than a conventional integrated circuit package having the same number of pins but only half as many external connections.
  • the number of electrical connections could be an even higher multiple of the number of pins than that illustrated in Figs. 1, 2 and 3, by increasing the number of conductors at each pin by, for example, employing the structure to be described in greater detail below with reference to the embodiments illustrated in Figs. 4 and 5.
  • the integrated circuit package 10 is shown as being in the form of a dual-in-line package (DIP), the present invention is, of course, not so limited.
  • the pins 14 could be constructed as shown in Figs. 1, 2 and 3, but depend from a single- in-line package (SIP), or depend on all four sides of an integrated circuit housing.
  • the integrated circuit 110 includes a housing 112 having depending pins, with only one pin 114 shown in Fig. 4.
  • the pin 114 includes three overlying, elongate insulating members or substrates, comprised of an inner insulating member 130B and two outer insulating members 130A and 130C.
  • The- pin 114 further includes four con- ductors 131, 132, 133, and 134, that are separated by the insulating members.
  • Conductor 131 is located on the outside surface of member 130A
  • conductor 132 is located between the inside surface of member 130A and the con ⁇ fronting surface of member 13OB
  • conductor 133 is located between the inside surface of member 130C and the con ⁇ fronting surface of member 130B
  • conductor 134 is located on the outside surface of member 130C.
  • Insula ⁇ ting member 130B has a portion extending beyond the in ⁇ sulating members 130A and 130B, so that conductors 132 and 133 are exposed at the end of the pin.
  • the pin 114 on the integrated circuit package 110 provides four external electrical connections to the integrated circuit chip (not shown in Fig. 4) within the housing 112.
  • a connector 142 for engaging the pin 114 is shown, in Fig. 4 as having four contacts, including two inner contacts 145 and 146, and two outer contacts 147 and 148.
  • Each of the contacts 145, 146, 147 and 148 has an arcuate pin engaging end 150, with the ends 150 of contacts 145 and 146 recessed so that they engage the exposed portions of conductors 132 and 133, and so that the ends 150 of contacts 147 and 148 will engage the conductors 131 and 134.
  • Figs. 5 and 6 there is shown a portion of an integrated circuit package 210, illustrating yet a further embodiment of the present invention.
  • the inte ⁇ grated circuit package 210 includes a housing 212 having depending pins, with only one pin 214 shown in Fig. 5.
  • the pin 214 includes an insulating member or substrate 230 having a substantially square cross-sectional shape, as seen best in Fig. 6.
  • Four conductors 231, 232, 233 and 234 are formed respectively on the four sides of the insulating member 230, so that the pin 214 can provide four external electrical connections.
  • a connector 242 for engaging the pin 214 is also shown in Fig. 5, and includes four contacts 245, 246, 247 and 248. Each of the contacts 245, 246, 247 and 248 has an arcuate pin engaging end 250 for engaging one of the conductors 231, 232, 233 and 234.

Abstract

The invention is concerned with the problem of the package density which can be achieved using integrated circuit packages. An integrated circuit package (10) includes a plurality of contact pins (14) having a plurality of conductors (32, 34) thereon. In one embodiment, each pin (14) includes an insulating substrate (30) and a conductor (32, 34) on each of two opposing sides of the substrate (30). An external connector (42) for each pin (14) has two contacts (46, 48), one contact for engaging each of the two conductors (32, 34) on the pin (14). In other embodiments, each pin (114, 214) includes four conductors. An external connector (142, 242) for each pin (114, 214) has four contacts, one contact for engaging each of the four conductors on the pin (114, 214).

Description

INTEGRATEDCIRCUITPACKAGEWITHMULTI-CONTACTPINS
Technical Field This invention relates to integrated circuit packages of the kind having a plurality of pins for providing external electrical connections.
Background Art
The increased circuit density of integrated circuit chips achieved by LSI (large scale integration) and VLSI (very large scale integration) technology permits many of the circuit functions that previously were required to be performed by pluralities of integra¬ ted circuits to now be performed by a single integrated circuit. This had led to a significant reduction in the total physical size of computers and other electronic systems that employ such circuits.
As the circuit density and the number of func¬ tions of an integrated circuit chip increase, there must normally be a corresponding increase in the number of pins on the integrated circuit package that provide the electrical connections to external power, data, address and other signal lines. It is now common for some types of integrated circuit packages to have forty or more pins. Because of the physical structure of the pins and their lead connections to the integrated circuit chip, however, the increase in the number of pins tends to increase the size of the housing that encloses the integrated circuit chip. Thus, the savings in space achieved by reducing the chip size is in many cases offset by an increased size of the housing.
This problem is especially critical in large computer systems, where a large number of integrated circuits are typically mounted on each of a plurality of circuit boards. The number of electrical pins and the physical dimensions of the housing of each integrated circuit often determine the size of each circuit board and the number of such circuit boards needed in the system. Thus it will be appreciated that a known integrated circuit package has the disadvantage that the density of circuit packages which can be achieved using the known packages is restricted.
Disclosure of the Invention It is an object of the present invention to provide an integrated circuit package of the kind speci¬ fied, wherein the aforementioned disadvantage is alle- viated.
Therefore, according to the present invention there is provided an integrated circuit package of the kind specified, characterized in that at least one of said pins includes a plurality of conductors so that a plurality of external electrical connections are made at said one of said pins.
Brief Description of the Drawings
Fig. 1 is a perspective view of one embodiment of the present invention, including an integrated circuit package and external connectors for engaging each pin on the integrated circuit package. Fig. 2 is the same view as Fig. 1, with the external connectors removed and with portions of the integrated circuit package broken away to expose details thereof.
Fig. 3 is a sectional view taken along the line III-III of Fig. 2.
Fig. 4 is a perspective view illustrating a • second embodiment of the present invention, including a portion of an integrated circuit package and a connector for engaging a pin on the integrated circuit package. Fig. 5 is a perspective view illustrating a third embodiment of the present invention, including a portion of an integrated circuit package and a connector for engaging a pin on the integrated circuit package. Fig. 6 is a sectional view taken along the line VI-VI of Fig. 5.
Description of the Preferred Embodiment
Referring now to Fig. 1, there is shown an integrated circuit package 10 in accordance with the present invention. As can be seen, the integrated circuit package 10 includes a body or housing 12 and a plurality of pins 14 depending from the sides of the housing. The housing 12 supports and encloses a semi¬ conductor or integrated circuit chip (not shown in Fig. 1) that can have a large number of circuit components fabricated thereon for performing logic, processing, memory or other functions. It should be noted that the present invention is not concerned with the nature of the integrated circuit chip itself, it being understood that such a chip could be ma"de in any one of many con¬ ventional techniques for performing any one of many conventional functions. Depending on the functions per¬ formed by the chip, the integrated circuit package could be used in a computer or any other type of electronic or electrical system.
The housing 12 in Fig. 1 has three package layers, including a cap or top layer 20, a thin middle - layer 22, and a bottom or support layer 24. As can be seen, the middle layer 22 overlies the bottom layer 24, and the top layer 20, in turn, overlies the middle layer 22. The pins 14 generally depend from the housing 12 at the middle layer 22, and are each constructed so as to have an elongate insulating member or substrate 30 with conductive material located to form two conductors' 32 and 34, the conductors spaced apart with one on each of two opposing sides of the insulating member 30. As will be described in greater detail later with reference to Fig. 2, the insulating member 30 of each pin 14 may be integral with the layer 22 of the housing 12. Furthermore, the pin conductors 32 and 34 may be integral with conductive patterns or leads 40 (shown only in Fig. 2) that are located on each side of * the package layer 22 and that permit access to the in¬ tegrated circuit chip- within the housing 12 for purposes of transferring or carrying signals to and from the in¬ tegrated circuit chip.
As also seen in Fig. 1, a connector assembly 0 for use with the integrated circuit package 10 includes a plurality of connectors 42 that are positioned or aligned so as to each receive one of the pins 14. Each connector 42 includes two opposing contacts 46 and 48, with each of the contacts 46 and 48 having an arcuate pin-engaging end 50 for making electrical contact with one of the conductors 32 and 34 on each pin 14. Each of the contacts 46 and 48 may be connected to external power, data, address or other signal lines (not shown) . Turning now to Figs. 2 and 3, there is shown in greater detail the construction of the integrated circuit package 10. As can be seen, each of the pin conductors 32 and 34 is formed integrally with and, hence, electrically connected to one of the previously- mentioned conductive leads 40 that are positioned on each side of the package layer 22. The conductive leads 40 all converge to an opened center portion 56 (Fig. 3) . of the housing 12 formed by the middle package layer 22 and enclosed by the top and bottom package layers 20 and 24. An integrated circuit chip 60 is mounted on layer 24 at the opened portion 56 so that, as conven¬ tional, connecting wires 62 may electrically connect each conductive lead 40 to an electrode or pad on the chip 60.
The package layers 20, 22 and 24 may be formed in a conventional fashion from ceramic, plastic or other insulating or dielectric material. The conductive leads 40 may likewise be formed in a conventional fashion, for example, by being stamped from a conductive sheet as a lead frame and then suitably bent and milled to form each one of the leads 40 and conductors 32 and 34. Of course, other suitable forms of constructing the inte- grated circuit package 10 could be employed, such as molding the entire housing 12 about the chip 60 as a single piece. Also, the leads 40 in the conductive layers 32 and 34 could be formed using a printed circuit board process, by starting with a relatively thin (.1 mm) dielectric base, as the layer 22, and then depositing* conductive material on both sides of the base to form the leads 40 and conductors 32 and 34. The base could be then milled to form projections having the conductors 32 and 34 thereon, and the projections could be heated and bent to form the pins 14. The chip could then be mounted and electrically connected, and then the package capped or encapsulated in plastic to form the finished integrated circuit package 10.
It should be apparent from the foregoing description that the integrated circuit package 10 in
Figs. 1, 2 and 3 is able to provide twice as many exter¬ nal electrical connections as there are pins 14. More particularly, as seen best in Figs. 1 and 2, by spacing the conductors 32 and 34 at each pin 14 in a direction that is generally perpendicular to the direction in which the pins are spaced along each side of the housing 12, the integrated circuit package 10 is made to occupy no more area than a conventional integrated circuit package having the same number of pins but only half as many external connections. Of course, the number of electrical connections could be an even higher multiple of the number of pins than that illustrated in Figs. 1, 2 and 3, by increasing the number of conductors at each pin by, for example, employing the structure to be described in greater detail below with reference to the embodiments illustrated in Figs. 4 and 5.
While the integrated circuit package 10 is shown as being in the form of a dual-in-line package (DIP), the present invention is, of course, not so limited. For example, the pins 14 could be constructed as shown in Figs. 1, 2 and 3, but depend from a single- in-line package (SIP), or depend on all four sides of an integrated circuit housing.
In Fig. 4, there is shown a portion of an integrated circuit package 110, illustrating an alter¬ nate embodiment of the present invention. As can be seen, the integrated circuit 110 includes a housing 112 having depending pins, with only one pin 114 shown in Fig. 4. The pin 114 includes three overlying, elongate insulating members or substrates, comprised of an inner insulating member 130B and two outer insulating members 130A and 130C. The- pin 114 further includes four con- ductors 131, 132, 133, and 134, that are separated by the insulating members. Conductor 131 is located on the outside surface of member 130A, conductor 132 is located between the inside surface of member 130A and the con¬ fronting surface of member 13OB, conductor 133 is located between the inside surface of member 130C and the con¬ fronting surface of member 130B, and conductor 134 is located on the outside surface of member 130C. Insula¬ ting member 130B has a portion extending beyond the in¬ sulating members 130A and 130B, so that conductors 132 and 133 are exposed at the end of the pin.
The pin 114 on the integrated circuit package 110 provides four external electrical connections to the integrated circuit chip (not shown in Fig. 4) within the housing 112. A connector 142 for engaging the pin 114 is shown, in Fig. 4 as having four contacts, including two inner contacts 145 and 146, and two outer contacts 147 and 148. Each of the contacts 145, 146, 147 and 148 has an arcuate pin engaging end 150, with the ends 150 of contacts 145 and 146 recessed so that they engage the exposed portions of conductors 132 and 133, and so that the ends 150 of contacts 147 and 148 will engage the conductors 131 and 134. In Figs. 5 and 6, there is shown a portion of an integrated circuit package 210, illustrating yet a further embodiment of the present invention. The inte¬ grated circuit package 210 includes a housing 212 having depending pins, with only one pin 214 shown in Fig. 5. The pin 214 includes an insulating member or substrate 230 having a substantially square cross-sectional shape, as seen best in Fig. 6. Four conductors 231, 232, 233 and 234 are formed respectively on the four sides of the insulating member 230, so that the pin 214 can provide four external electrical connections. A connector 242 for engaging the pin 214 is also shown in Fig. 5, and includes four contacts 245, 246, 247 and 248. Each of the contacts 245, 246, 247 and 248 has an arcuate pin engaging end 250 for engaging one of the conductors 231, 232, 233 and 234.
While the embodiment shown in Fig. 4 and the embodiment shown in Figs. 5 and 6 both provide only four external electrical connections at each pin, it should be apparent that by increasing the number of insulating members and conductors at each pin, a larger number of external connections is possible.
OMPI

Claims

CLAIMS :
1. An integrated circuit package (10) having a plurality of pins (14) for providing external electri¬ cal connections, characterized in that at least one of said pins (14) includes a plurality of conductors (32, 34) so that a plurality of external electrical connec¬ tions are made at said one of said pins (14).
2. - An integrated circuit package according to claim 1, characterized by at least one of said pins (14) including an insulating member (30) upon which said conductors (32, 34) are located in spaced-apart relation.
3. An integrated circuit package according to claim 2, characterized by a housing (12), a semiconductor chip (60) enclosed by said housing (12), and conductive leads (40) electrically connecting each of said conduc¬ tors (32, 34) to said semiconductor chip (60).
4. An integrated circuit package according to claim 3, characterized in that said pins (14) are spaced apart in a direction along at least one side of said housing (12), and in that said conductors (32, 34) of said at least one of said pins (14) are spaced apart in a direction generally perpendicular to the direction in which said pins (14) are spaced apart along said one side of said housing (12).
5. An integrated circuit package according to claim 4, characterized in that said housing (12) in¬ cludes a bottom layer (24), a middle layer (22) and a top layer (20), and in that said conductive leads (40) are located between said middle layer (22) and each of said bottom and top layers (24, 20).
6. An integrated circuit package according to claim 4, characterized in that a first one (32) of said 6 . ( concluded ) conductors (32, 34) is located on one side of said insulating member (30) and a second one (34) of said conductors (32, 34) is located on an opposite side of said insulating member (30).
7. An integrated circuit package according to claim 2 or claim 3, characterized in that said in¬ sulating member (230) has a generally square cross- sectional shape, and in that said conductors (231, 232, 233, 234) are located one along each of the four sides of said insulating member (230).
8. An integrated circuit package according to claim 1, characterized in that at least one of said pins (114) comprises three elongate insulating members (130A, 130B, 130C), including an inner insulating member (130B) and two outer insulating members (130A, 130C), and four conductors (131, 132, 133, 134), in that two of said four conductors (131, 132, 133, 134) are located between respective inside surfaces of said outer in¬ sulating members (130A, 130C) and respective confronting surfaces of said inner insulating member (130B), and one of said four conductors (131, 132, 133, 134) is located on an outside surface of each of said outer insulating members (130A, 130C), and in that said inner insulating member (130B) includes a portion extending beyond said outer insulating members (130A, 130C) so that each of said conductors (132, 133) between said outer insulating layers (130A, 130C) and said inner insulating layer (130B) is exposed at said extending portion.
9. In an electronic system, the combination* of an integrated circuit package (10) and a connector assembly for use with said package (10), characterized in that said package (10) includes a housing (12) en¬ closing an integrated circuit chip (60) and a plurality 9 . ( concluded ) of pins (14) extending from said housing (12) and adapted to engage said connector assembly for carrying signals between said integrated circuit chip (60) and said con¬ nector assembly, each of said pins (14) including a plurality of conductors (32, 34) and an insulating sub¬ strate (30) upon which said conductors (32, 34) are located in spaced-apart relation, and in that said con¬ nector assembly comprises a plurality of connectors (42) for engaging respective ones of said plurality of pins (14), said connectors (42) having a plurality of contacts (46, 48) positioned so that said contacts (46, 48) en¬ gage respective ones of said conductors (32, 34).
O
O
PCT/US1981/000610 1980-05-12 1981-05-04 Integrated circuit package with multi-contact pins WO1981003396A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU71766/81A AU7176681A (en) 1980-05-12 1981-05-04 Integrated circuit package having a plurality of pins for providing external electrical connections

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14861380A 1980-05-12 1980-05-12
US148613 1980-05-12

Publications (1)

Publication Number Publication Date
WO1981003396A1 true WO1981003396A1 (en) 1981-11-26

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PCT/US1981/000610 WO1981003396A1 (en) 1980-05-12 1981-05-04 Integrated circuit package with multi-contact pins

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EP (1) EP0051666A1 (en)
BE (1) BE888756A (en)
WO (1) WO1981003396A1 (en)
ZA (1) ZA812893B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985004522A1 (en) * 1984-03-22 1985-10-10 Mostek Corporation Impedance-matched leads
US4682207A (en) * 1982-03-17 1987-07-21 Fujitsu Limited Semiconductor device including leadless packages and a base plate for mounting the leadless packages
US4796078A (en) * 1987-06-15 1989-01-03 International Business Machines Corporation Peripheral/area wire bonding technique
US5021866A (en) * 1987-09-28 1991-06-04 Kabushiki Kaisha Toshiba Semiconductor integrated circuit apparatus
EP0650064A2 (en) * 1993-10-26 1995-04-26 Hewlett-Packard Company Method of coupling test equipment to an electrical component
US6815959B2 (en) * 2001-04-09 2004-11-09 Kla-Tencor Technologies Corp. Systems and methods for measuring properties of conductive layers
JP2017055031A (en) * 2015-09-11 2017-03-16 トヨタ自動車株式会社 Wire connection method and terminal

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3368114A (en) * 1965-07-06 1968-02-06 Radiation Inc Microelectronic circuit packages with improved connection structure
US3628105A (en) * 1968-03-04 1971-12-14 Hitachi Ltd High-frequency integrated circuit device providing impedance matching through its external leads
JPS54132166A (en) * 1978-04-05 1979-10-13 Nec Corp Socket for semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3368114A (en) * 1965-07-06 1968-02-06 Radiation Inc Microelectronic circuit packages with improved connection structure
US3628105A (en) * 1968-03-04 1971-12-14 Hitachi Ltd High-frequency integrated circuit device providing impedance matching through its external leads
JPS54132166A (en) * 1978-04-05 1979-10-13 Nec Corp Socket for semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682207A (en) * 1982-03-17 1987-07-21 Fujitsu Limited Semiconductor device including leadless packages and a base plate for mounting the leadless packages
WO1985004522A1 (en) * 1984-03-22 1985-10-10 Mostek Corporation Impedance-matched leads
US4796078A (en) * 1987-06-15 1989-01-03 International Business Machines Corporation Peripheral/area wire bonding technique
US5021866A (en) * 1987-09-28 1991-06-04 Kabushiki Kaisha Toshiba Semiconductor integrated circuit apparatus
EP0650064A2 (en) * 1993-10-26 1995-04-26 Hewlett-Packard Company Method of coupling test equipment to an electrical component
EP0650064A3 (en) * 1993-10-26 1996-01-03 Hewlett Packard Co Method of coupling test equipment to an electrical component.
US6815959B2 (en) * 2001-04-09 2004-11-09 Kla-Tencor Technologies Corp. Systems and methods for measuring properties of conductive layers
JP2017055031A (en) * 2015-09-11 2017-03-16 トヨタ自動車株式会社 Wire connection method and terminal

Also Published As

Publication number Publication date
ZA812893B (en) 1982-05-26
BE888756A (en) 1981-08-28
EP0051666A1 (en) 1982-05-19

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