WO1982002457A1 - Die attachment exhibiting enhanced quality and reliability - Google Patents

Die attachment exhibiting enhanced quality and reliability Download PDF

Info

Publication number
WO1982002457A1
WO1982002457A1 PCT/US1980/001746 US8001746W WO8202457A1 WO 1982002457 A1 WO1982002457 A1 WO 1982002457A1 US 8001746 W US8001746 W US 8001746W WO 8202457 A1 WO8202457 A1 WO 8202457A1
Authority
WO
WIPO (PCT)
Prior art keywords
preform
die
substrate
tin
antimony
Prior art date
Application number
PCT/US1980/001746
Other languages
French (fr)
Inventor
Corp Mostek
Original Assignee
Finn John B
Palermo Robert F
Dycus Dale W
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Finn John B, Palermo Robert F, Dycus Dale W filed Critical Finn John B
Priority to EP81901580A priority Critical patent/EP0067993A1/en
Priority to PCT/US1980/001746 priority patent/WO1982002457A1/en
Publication of WO1982002457A1 publication Critical patent/WO1982002457A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates generally to the fabrication of semiconductor devices , and more particularly to an improved technique for attaching a die or integrated circuit (IC) chip to a metal or ceramic substrate .
  • IC integrated circuit
  • Attachment of silicon IC chips to metal lead frames or to metallized ceramic bases comprises an important step in the fabrication of semiconductor devices. Typically, after testing, the chips are individually attached to the central portions of metal or metallized ceramic bases from which extend multiple external lead pins for connecting each chip to a circuit board. The terminals of each chip are then wired to the leads of its corresponding base before the chip and central base portion are encased in plastic or hermetically sealed with a ceramic or metal lid for protection. In the industry, such chips are commonly referred to as “dice” with the metal bases being such as “lead frames” and the metallized ceramics known as cer-dip bases.
  • the prior techniques for attaching dice to lead frames or other bases have been characterized by the use of rare metals at relatively high temperatures.
  • the usual practice has been to use an uncoated die or to coat the backside of a die with a thin layer of pure gold, and then use a small piece of gold alloy for bonding the die to a heated lead frame or other base.
  • Such small pieces of gold alloy which are usually comprised of pure gold, gold and silicon, or gold and germanium, are commonly known as "preforms" in the industry.
  • the preform is placed on the central portion thereof until it melts, after which the die is placed on the preform and gently rubbed or "scrubbed in” until wetting of the die by the molten alloy is accomplished, followed by cooling of the lead frame or other base to form a bond and complete attachment.
  • a pure gold preform is employed for die attachment, the gold does not melt until the silicon die is "scrubbed in”. The intimate contact provided by scrubbing permits interdiffusion between the pure gold and the silicon.
  • the silicon content in the gold preform reaches approximately 3..4%, by weight, the alloy melts at approximately 363°C. This is referred to as eutectic melting and die attachment accomplished by this method is known as eutectic die attachment.
  • Another technique has involved the use of epoxy or other organic resin materials filled with a metal powder such as silver.
  • the present invention comprises a method of attaching a die to a substrate which overcomes the foregoing and other difficulties associated with the prior art.
  • an improved die-attach technique which does not require expensive gold or gold alloys and which can be carried out at relatively lower temperatures, thereby avoiding the thermal stress-related problems of the prior art and achieving a connection of greater strength and reliability.
  • an illustrated embodiment of the invention provides a method of attaching a silicon IC chip or die to a metal substrate wherein a barrier coating of chromium is first provided on the back side of the die followed by a coating of silver, gold, tin, antimony or alloys thereof over the chromium coating.
  • the base or substrate is heated to an appropriate temperature of between about 250°C and 400°C.
  • a preform comprised primarily of tin with a small amount of antimony and a trace of aluminum is then placed on the heated substrate until it melts, followed by placement of the die on the melted preform, scrubbing-in the die and cooling to provide a reliable joint between the die and substrate.
  • FIGURE 1 is a perspective view of dice being attached to a lead frame
  • FIGURE 2 is an exploded view of the die-attach technique of the prior art.
  • FIGURE 3 is an exploded view of the die-attach method of the invention.
  • FIGURES 1 illustrates attachment of silicon IC chips or dice 10 onto bases or substrates 12, each of which comprises a central pad portion interconnected by supports to a lead frame 14.
  • the die attach technique herein is described and shown with specific reference to metal lead frames for purposes of illustration, however, it will be understood that the invention can also be utilized with metalized ceramic bases or substrates.
  • Lead frame 14 rests on a heated block 16 and is guided for movement thereacross between a pair of guides 18.
  • An adjustable heating element, temperature sensor and thermometer ⁇ not shown) are associated with block 16 for controlling the temperature thereof.
  • a blank frame 14 is inserted between guides 18 and advanced to position a substrate 12 on block 16 for heating. After substrate 12 has reached the desired temperature, a preform 20 is positioned thereon until it melts, after which die 10 is positioned on the melted preform material and scrubbed-in until wetted by the molten solder. Frame 14 is then advanced to allow the junction between die 10 and substrate 12 to cool while simultaneously positioning the next following substrate in place for heating.
  • a tube 22 discharging a stream of inert or non-oxidizing gas, such as nitrogen, or reducing, such as hydrogen, across frame 14 is preferably associated with heater block 16 to reduce oxidation during the die-attach process.
  • the operation of advancing frame 14 and positioning preform 20 and die 10 thereon can be carried out on an automatic basis or on a manual basis by an operator looking through a microscope and manipulating tweezers.
  • FIGURE 2 illustrates the die-attach technique of the prior art, wherein the underside of the silicon die 10 is first provided with a thin coating of pure gold, typically about 1000 to 2000 Angstroms thick.
  • the coating 24 is usually applied by sputtering, a technique which involves vaporizing the gold and depositing it onto the backside of a die 10 or a wafer of dice under partial vacuum conditions.
  • the metal or metallized ceramic substrate 12 is typically heated to a temperature of about 460°C before the preform 20 of gold alloy is positioned thereon until it melts.
  • Substrate 12 typically has been comprised of silver plated nickel/iron alloy (commonly known as Alloy 42) or silver metallized ceramic material.
  • the materials of preform 20 typically have been comprised of gold or gold alloys, such as gold and silicon or gold and germanium.
  • the die 10 is then lowered into contact with the material of preform 20 and scrubbed in until the die is wetted by the molten preform material, after which substrate 12 is removed from heater block 16 to allow cooling of the junction between the die and substrate.
  • this technique requires expensive materials having d ifferent rates of thermal expansion and brittle characteristics when alloyed with silicon which can result in thermal stress-related difficulties and low reliability in the finished semiconductor package.
  • FIGURE 3 illustrates the die-attach method 30 incorporating the present invention.
  • the underside of the silicon die 10 is provided with two thin coatings.
  • a thin coating 32 of barrier material In the preferred embodiment, substantially pure chromium is used for coating 32; however, it is believed that titanium, zirconium, hafnium, molybdenum, tungsten, vanadium, tantalum and niobium (columbium) would also be effective.
  • a coating 34 of silver, tin, antimony or a tin-antimony alloy is then provided over coating 32. If desired, gold may be used for the second coating 34.
  • Each coating 32 and 34 is approximately 1000 Angstroms thick and can be applied by means of sputtering or other suitable methods of deposition.
  • the preform 36 is preferably comprised of primarily tin with a small amount of antimony and a trace of aluminum. Inclusion of a trace of aluminum is advantageous because it serves to inhibit oxidation, however, the aluminum can be omitted under some conditions if desired. Other combinations of elements which bond with those of coatings 32 and 34 may also be used to fabricate preform 36.
  • the substrate 38 shown in the form of a lead frame comprises metal Carpenter 42 alloy, which is comprised essentially of 0.10% carbon maximum, 0.80% manganese maximum, 0.30% silicon maximum, 0.25% chromium maximum, 40-43% nickel and the balance iron.
  • Substrate 38 may also be comprised of other suitable metal alloys, ceramics, or metallized ceramics and it will be understood that the substrate need not necessarily be in the form of a lead frame to practice the present invention.
  • the steps involved in the die-attach method 30 of the invention also require heating substrate 38 to a temperature of about 250° to 400°C sufficient to melt the preform 36. It has been found in experimentation that a temperature range of 275° to 290°C works well.
  • Preform 36 is then positioned on the heated substrate 38 until the preform melts, followed by placement of die 10 onto the melted material of the preform and scrubbing it in until it is wetted by the molten preform.
  • the chromium of coating 32 acts as a barrier to protect the silicon of die 10, while simultaneously reacting to a limited degree with the alley of preform 36.
  • the molten preform 36 dissolves the material of coating 34 to react with coating 32, and also reacts with the material of substrate 38 to form a bond of enhanced strength and reliability between the die 10 and substrate.
  • tin and antimony which have been found suitable for use as preform 36 are set out below.
  • a trace amount of about 0.06 to 0.08% aluminum is preferablyincluded to inhibit oxidation.
  • the present invention comprises an improved method of attaching a silicon IC chip to a metal substrate or to a metallized ceramic substrate.
  • the method herein is carried out with less expensive materials at less elevated temperatures to avoid the brittleness and stress-related problems of the prior art.
  • Other advantages will be evident to those skilled in the art.

Abstract

A method of attaching a silicon IC chip (10) to a metal or ceramic substrate (38) includes coating the underside of the die with a barrier material (32), such as chromium, and then coating the first layer with another material (34) selected from the group consisting of silver, gold, tin, antimony, or alloys thereof. A preform (36) of material selected from the group consisting of tin, tin with a relatively small amount of antimony, or tin with a relatively small amount of antimony and a trace of aluminum is then placed on the heated substrate (38) followed by the die (10) to effect attachment.

Description

DI E ATTACHMENT EXHIB ITING ENHANCED QUALITY AND RELIABILITY
TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices , and more particularly to an improved technique for attaching a die or integrated circuit ( IC) chip to a metal or ceramic substrate .
BACKGROUND ART
Attachment of silicon IC chips to metal lead frames or to metallized ceramic bases comprises an important step in the fabrication of semiconductor devices. Typically, after testing, the chips are individually attached to the central portions of metal or metallized ceramic bases from which extend multiple external lead pins for connecting each chip to a circuit board. The terminals of each chip are then wired to the leads of its corresponding base before the chip and central base portion are encased in plastic or hermetically sealed with a ceramic or metal lid for protection. In the industry, such chips are commonly referred to as "dice" with the metal bases being such as "lead frames" and the metallized ceramics known as cer-dip bases.
The prior techniques for attaching dice to lead frames or other bases have been characterized by the use of rare metals at relatively high temperatures. For example, the usual practice has been to use an uncoated die or to coat the backside of a die with a thin layer of pure gold, and then use a small piece of gold alloy for bonding the die to a heated lead frame or other base. Such small pieces of gold alloy, which are usually comprised of pure gold, gold and silicon, or gold and germanium, are commonly known as "preforms" in the industry. After the lead frame or other base has been heated to a sufficiently high temperature, such as 460°C, the preform is placed on the central portion thereof until it melts, after which the die is placed on the preform and gently rubbed or "scrubbed in" until wetting of the die by the molten alloy is accomplished, followed by cooling of the lead frame or other base to form a bond and complete attachment. When a pure gold preform is employed for die attachment, the gold does not melt until the silicon die is "scrubbed in". The intimate contact provided by scrubbing permits interdiffusion between the pure gold and the silicon. When the silicon content in the gold preform reaches approximately 3..4%, by weight, the alloy melts at approximately 363°C. This is referred to as eutectic melting and die attachment accomplished by this method is known as eutectic die attachment. Another technique has involved the use of epoxy or other organic resin materials filled with a metal powder such as silver.
Difficulties, however, attend the die-attach techniques of the prior art. The different thermal expansion rates of the materials involved can cause breakage, failure, low reliability and other problems resulting from thermal stress. The eutectic alloys of gold with silicon, germanium and tin are hard and brittle. Since the silicon is also brittle, the thermal stresses attendant upon the widely disparate thermal expansion coefficients of the silicon die and the eutectic alloy are virtually certain to cause fracturing to relieve such stresses. If cracking does not occur spontaneously, it will often occur when the assembly is subjected to minor shocks and impacts during routine subsequent handling and testing. This cracking compromises the reliability of the assembly. In addition, gold and other rare metals are becoming increasingly scarce and expensive. The epoxy or other organic resin bonding techniques have not provided the strength or thermal durability necessary in some applications.
A need has thus existed for an improved technique for attaching a die to a lead frame or other base in order to enhance reliability of the completed semiconductor device while avoiding the use of rare metals at excessively elevated temperatures. SUMMARY OF INVENTION
The present invention comprises a method of attaching a die to a substrate which overcomes the foregoing and other difficulties associated with the prior art. In accordance with the invention, there is provided an improved die-attach technique which does not require expensive gold or gold alloys and which can be carried out at relatively lower temperatures, thereby avoiding the thermal stress-related problems of the prior art and achieving a connection of greater strength and reliability.
More particularly, an illustrated embodiment of the invention provides a method of attaching a silicon IC chip or die to a metal substrate wherein a barrier coating of chromium is first provided on the back side of the die followed by a coating of silver, gold, tin, antimony or alloys thereof over the chromium coating. The base or substrate is heated to an appropriate temperature of between about 250°C and 400°C. A preform comprised primarily of tin with a small amount of antimony and a trace of aluminum is then placed on the heated substrate until it melts, followed by placement of the die on the melted preform, scrubbing-in the die and cooling to provide a reliable joint between the die and substrate.
BRIEF DESCRIPTION OF DRAWINGS
A more complete understanding of the invention can be had by reference to the following Detailed Description together with the accompanying Drawings, wherein: FIGURE 1 is a perspective view of dice being attached to a lead frame;
FIGURE 2 is an exploded view of the die-attach technique of the prior art; and
FIGURE 3 is an exploded view of the die-attach method of the invention.
DETAILED DESCRIPTION
Referring now to the Drawings, wherein like reference numerals designate corresponding elements throughout the views, FIGURES 1 illustrates attachment of silicon IC chips or dice 10 onto bases or substrates 12, each of which comprises a central pad portion interconnected by supports to a lead frame 14. The die attach technique herein is described and shown with specific reference to metal lead frames for purposes of illustration, however, it will be understood that the invention can also be utilized with metalized ceramic bases or substrates.
Lead frame 14 rests on a heated block 16 and is guided for movement thereacross between a pair of guides 18. An adjustable heating element, temperature sensor and thermometer {not shown) are associated with block 16 for controlling the temperature thereof. In general, a blank frame 14 is inserted between guides 18 and advanced to position a substrate 12 on block 16 for heating. After substrate 12 has reached the desired temperature, a preform 20 is positioned thereon until it melts, after which die 10 is positioned on the melted preform material and scrubbed-in until wetted by the molten solder. Frame 14 is then advanced to allow the junction between die 10 and substrate 12 to cool while simultaneously positioning the next following substrate in place for heating.
A tube 22 discharging a stream of inert or non-oxidizing gas, such as nitrogen, or reducing, such as hydrogen, across frame 14 is preferably associated with heater block 16 to reduce oxidation during the die-attach process. The operation of advancing frame 14 and positioning preform 20 and die 10 thereon can be carried out on an automatic basis or on a manual basis by an operator looking through a microscope and manipulating tweezers. FIGURE 2 illustrates the die-attach technique of the prior art, wherein the underside of the silicon die 10 is first provided with a thin coating of pure gold, typically about 1000 to 2000 Angstroms thick. The coating 24 is usually applied by sputtering, a technique which involves vaporizing the gold and depositing it onto the backside of a die 10 or a wafer of dice under partial vacuum conditions. The metal or metallized ceramic substrate 12 is typically heated to a temperature of about 460°C before the preform 20 of gold alloy is positioned thereon until it melts. Substrate 12 typically has been comprised of silver plated nickel/iron alloy (commonly known as Alloy 42) or silver metallized ceramic material. The materials of preform 20 typically have been comprised of gold or gold alloys, such as gold and silicon or gold and germanium. The die 10 is then lowered into contact with the material of preform 20 and scrubbed in until the die is wetted by the molten preform material, after which substrate 12 is removed from heater block 16 to allow cooling of the junction between the die and substrate. As discussed above, however, this technique requires expensive materials having d ifferent rates of thermal expansion and brittle characteristics when alloyed with silicon which can result in thermal stress-related difficulties and low reliability in the finished semiconductor package.
FIGURE 3 illustrates the die-attach method 30 incorporating the present invention. In accordance with the invention, the underside of the silicon die 10 is provided with two thin coatings. First provided is a thin coating 32 of barrier material. In the preferred embodiment, substantially pure chromium is used for coating 32; however, it is believed that titanium, zirconium, hafnium, molybdenum, tungsten, vanadium, tantalum and niobium (columbium) would also be effective. A coating 34 of silver, tin, antimony or a tin-antimony alloy is then provided over coating 32. If desired, gold may be used for the second coating 34. Each coating 32 and 34 is approximately 1000 Angstroms thick and can be applied by means of sputtering or other suitable methods of deposition.
The preform 36 is preferably comprised of primarily tin with a small amount of antimony and a trace of aluminum. Inclusion of a trace of aluminum is advantageous because it serves to inhibit oxidation, however, the aluminum can be omitted under some conditions if desired. Other combinations of elements which bond with those of coatings 32 and 34 may also be used to fabricate preform 36.
The substrate 38 shown in the form of a lead frame comprises metal Carpenter 42 alloy, which is comprised essentially of 0.10% carbon maximum, 0.80% manganese maximum, 0.30% silicon maximum, 0.25% chromium maximum, 40-43% nickel and the balance iron. Substrate 38, however, may also be comprised of other suitable metal alloys, ceramics, or metallized ceramics and it will be understood that the substrate need not necessarily be in the form of a lead frame to practice the present invention.
The steps involved in the die-attach method 30 of the invention also require heating substrate 38 to a temperature of about 250° to 400°C sufficient to melt the preform 36. It has been found in experimentation that a temperature range of 275° to 290°C works well. Preform 36 is then positioned on the heated substrate 38 until the preform melts, followed by placement of die 10 onto the melted material of the preform and scrubbing it in until it is wetted by the molten preform. The chromium of coating 32 acts as a barrier to protect the silicon of die 10, while simultaneously reacting to a limited degree with the alley of preform 36. The molten preform 36 dissolves the material of coating 34 to react with coating 32, and also reacts with the material of substrate 38 to form a bond of enhanced strength and reliability between the die 10 and substrate.
By way of example, the relative proportions of tin and antimony which have been found suitable for use as preform 36 are set out below. In each case, a trace amount of about 0.06 to 0.08% aluminum is preferablyincluded to inhibit oxidation.
TIN (SN) ANTIMONY (SB) 100% 0%
99.5% 0.5%
98% 2%
97% 3%
96% 4% 95% 5%
94% 6%
90% 10%
80% 20%
From the foregoing, it will be apparent that the present invention comprises an improved method of attaching a silicon IC chip to a metal substrate or to a metallized ceramic substrate. The method herein is carried out with less expensive materials at less elevated temperatures to avoid the brittleness and stress-related problems of the prior art. Other advantages will be evident to those skilled in the art.
Although particular embodiments of the invention have been illustrated in the accompanying Drawing and described in the foregoing Detailed Description, the invention is not limited only to the embodiments disclosed, but is intended to embrace any alternatives, equivalents, modifications and rearrangements of elements falling within the scope of the invention as defined by the following Claims.

Claims

CLAIMS :
1. In a method of attaching a silicon die to a metal or metallized ceramic substrate of the type wherein the underside of the die is coated with a first coating and the substrate is heated before a solder preform and the die are positioned on the substrate to effect attachment, the improvement comprising: said first coating on the underside of said die comprising a material selected from the group consisting of chromium, titanium, zirconium, hafnium, molybdenum, tungsten, vanadium, tantalum and niobium; forming second coating of predetermined material over said first coating; and said preform being comprised of a material including tin.
2. The method of Claim 1, wherein said second coating is comprised of a material selected from the group consisting of silver, gold, tin, antimony, or alloys thereof.
3. The method of Claim 1, wherein said preform is comprised of substantially pure tin.
4. The method of Claim 1, wherein said preform is comprised of primarily tin with a relatively small amount of antimony.
5. The method of Claim 1, wherein said preform is comprised of primarily tin with a relatively small amount of antimony and a trace of aluminum.
6. The die attachment formed according to the method of Claim 1.
7. A method of attaching a silicon die to a substrate, comprising the steps of:
(a) forming a first layer of chromium on the underside of the die; (b) forming a second layer of predetermined material over said first layer;
(c) providing a preform of material selected from the group consisting of tin, primarily tin with a relatively small amount of antimony, and primarily tin with a relatively small amount of antimony and a trace of aluminum;
(d) heating said substrate to a temperature sufficient to melt said preform;
(e) placing said preform on the heated substrate to melt said preform;
(f) placing the die on the melted preform on the heated substrate such that the die is wetted by the molten preform; and
(g) allowing the substrate and melted preform to cool and form an attachment between the die and substrate.
8. The method of Claim 7, wherein the predetermined material of the second layer in step (b) is comprised of a material selected from the group consisting of silver, gold, tin, antimony, and alloys thereof.
9. The method of Claim 7, wherein said preform is comprised of pure tin.
10. The method of Claim 7, wherein said preform of step (c) is comprised of primarily tin with a relatively small amount of antimony.
11. The method of Claim 7, wherein said preform of step (c) is comprised of primarily tin with a relatively small amount of antimony and a trace of aluminum.
12. The method of Claim 7, where in step (d) the substrate is heated to a temperature of between about 250° and 400°C.
13. The method of Claim 7, wherein said first and second layers are each approximately 1000 Angstroms thick.
14. The die attachment formed according to the method of Claim 7.
15. A method of forming a bond between a silicon die and a substrate, comprising the steps of :
( a ) forming a f irst layer of chromium on the underside of the die; (b) forming over said first layer a second layer of material selected from the group consisting of silver, gold, tin, antimony, and alloys thereof;
(c) providing a preform of material selected from the group consisting of tin, tin with a relatively small amount of antimony, and tin with a relatively small amount of antimony and a trace of aluminum;
(d) heating the substrate to a temperature sufficient to melt said preform;
(e) placing said preform on the heated substrate to melt said preform;
(f) placing the die on the melted preform on the heated substrate such that the die is wetted by the molten preform; and
(g) allowing the substrate and melted preform to cool and form a bond between the die and substrate.
16. The method of Claim 15, wherein in steps (a) and (b) each of said first and second layers is approximately 1000 Angstroms thick.
17. The method of Claim 15, where in step (d) the substrate is heated to a temperature of about 250° to 400°C.
18. The bond formed according to the method of Claim 15.
PCT/US1980/001746 1980-12-30 1980-12-30 Die attachment exhibiting enhanced quality and reliability WO1982002457A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP81901580A EP0067993A1 (en) 1980-12-30 1980-12-30 Die attachment exhibiting enhanced quality and reliability
PCT/US1980/001746 WO1982002457A1 (en) 1980-12-30 1980-12-30 Die attachment exhibiting enhanced quality and reliability

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/US1980/001746 WO1982002457A1 (en) 1980-12-30 1980-12-30 Die attachment exhibiting enhanced quality and reliability
WOUS80/01746801230 1980-12-30

Publications (1)

Publication Number Publication Date
WO1982002457A1 true WO1982002457A1 (en) 1982-07-22

Family

ID=22154711

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1980/001746 WO1982002457A1 (en) 1980-12-30 1980-12-30 Die attachment exhibiting enhanced quality and reliability

Country Status (2)

Country Link
EP (1) EP0067993A1 (en)
WO (1) WO1982002457A1 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2560438A1 (en) * 1984-02-23 1985-08-30 Ates Componenti Elettron PROCESS FOR WELDING SEMICONDUCTOR WAFERS TO A METAL SUPPORT IN THE AUTOMATIC ASSEMBLY OF SEMICONDUCTOR DEVICES
DE3442537A1 (en) * 1984-11-22 1986-05-22 BBC Aktiengesellschaft Brown, Boveri & Cie., Baden, Aargau METHOD FOR BUBBLE-FREE CONNECTING A LARGE SEMICONDUCTOR COMPONENT TO A SUBSTRATE COMPONENT BY SOLDERING
EP0186411A2 (en) * 1984-12-28 1986-07-02 Kabushiki Kaisha Toshiba Semiconductor device in which a semiconductor chip is fixed to a base
EP0186585A2 (en) * 1984-12-19 1986-07-02 Fairchild Semiconductor Corporation Die bonding process
US4659006A (en) * 1985-09-26 1987-04-21 Rca Corporation Method of bonding a die to a substrate
EP0231937A2 (en) * 1986-02-06 1987-08-12 Hitachi Maxell Ltd. An arrangement of a semiconductor device for use in a card
US4772935A (en) * 1984-12-19 1988-09-20 Fairchild Semiconductor Corporation Die bonding process
US4808769A (en) * 1986-09-25 1989-02-28 Kabushiki Kaisha Toshiba Film carrier and bonding method using the film carrier
US4875617A (en) * 1987-01-20 1989-10-24 Citowsky Elya L Gold-tin eutectic lead bonding method and structure
US5027997A (en) * 1990-04-05 1991-07-02 Hughes Aircraft Company Silicon chip metallization system
US5198695A (en) * 1990-12-10 1993-03-30 Westinghouse Electric Corp. Semiconductor wafer with circuits bonded to a substrate
US5296074A (en) * 1987-03-30 1994-03-22 E. I. Du Pont De Nemours And Company Method for bonding small electronic components
US5380598A (en) * 1992-03-05 1995-01-10 Westinghouse Brake & Signal Holdings Ltd. Solder joint
EP0833384A2 (en) * 1996-09-25 1998-04-01 Siemens Aktiengesellschaft Semiconductor body having a solder layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3650826A (en) * 1968-09-30 1972-03-21 Siemens Ag Method for producing metal contacts for mounting semiconductor components in housings
US3729807A (en) * 1970-10-30 1973-05-01 Matsushita Electronics Corp Method of making thermo-compression-bonded semiconductor device
US3942244A (en) * 1967-11-24 1976-03-09 Semikron Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Semiconductor element
US4023725A (en) * 1974-03-04 1977-05-17 U.S. Philips Corporation Semiconductor device manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3942244A (en) * 1967-11-24 1976-03-09 Semikron Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Semiconductor element
US3650826A (en) * 1968-09-30 1972-03-21 Siemens Ag Method for producing metal contacts for mounting semiconductor components in housings
US3729807A (en) * 1970-10-30 1973-05-01 Matsushita Electronics Corp Method of making thermo-compression-bonded semiconductor device
US4023725A (en) * 1974-03-04 1977-05-17 U.S. Philips Corporation Semiconductor device manufacture

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2560438A1 (en) * 1984-02-23 1985-08-30 Ates Componenti Elettron PROCESS FOR WELDING SEMICONDUCTOR WAFERS TO A METAL SUPPORT IN THE AUTOMATIC ASSEMBLY OF SEMICONDUCTOR DEVICES
DE3442537A1 (en) * 1984-11-22 1986-05-22 BBC Aktiengesellschaft Brown, Boveri & Cie., Baden, Aargau METHOD FOR BUBBLE-FREE CONNECTING A LARGE SEMICONDUCTOR COMPONENT TO A SUBSTRATE COMPONENT BY SOLDERING
EP0186585A2 (en) * 1984-12-19 1986-07-02 Fairchild Semiconductor Corporation Die bonding process
EP0186585A3 (en) * 1984-12-19 1987-03-11 Fairchild Camera & Instrument Corporation Die bonding process
US4772935A (en) * 1984-12-19 1988-09-20 Fairchild Semiconductor Corporation Die bonding process
EP0186411A2 (en) * 1984-12-28 1986-07-02 Kabushiki Kaisha Toshiba Semiconductor device in which a semiconductor chip is fixed to a base
EP0186411A3 (en) * 1984-12-28 1987-04-01 Kabushiki Kaisha Toshiba Semiconductor device in which a semiconductor chip is fixed to a base
US4954870A (en) * 1984-12-28 1990-09-04 Kabushiki Kaisha Toshiba Semiconductor device
US4659006A (en) * 1985-09-26 1987-04-21 Rca Corporation Method of bonding a die to a substrate
EP0231937A3 (en) * 1986-02-06 1989-03-22 Hitachi Maxell Ltd. An arrangement of a semiconductor device for use in a card
EP0231937A2 (en) * 1986-02-06 1987-08-12 Hitachi Maxell Ltd. An arrangement of a semiconductor device for use in a card
US4808769A (en) * 1986-09-25 1989-02-28 Kabushiki Kaisha Toshiba Film carrier and bonding method using the film carrier
US4857671A (en) * 1986-09-25 1989-08-15 Kabushiki Kaisha Toshiba Film carrier and bonding method using the film carrier
US4875617A (en) * 1987-01-20 1989-10-24 Citowsky Elya L Gold-tin eutectic lead bonding method and structure
US5296074A (en) * 1987-03-30 1994-03-22 E. I. Du Pont De Nemours And Company Method for bonding small electronic components
US5027997A (en) * 1990-04-05 1991-07-02 Hughes Aircraft Company Silicon chip metallization system
US5198695A (en) * 1990-12-10 1993-03-30 Westinghouse Electric Corp. Semiconductor wafer with circuits bonded to a substrate
US5380598A (en) * 1992-03-05 1995-01-10 Westinghouse Brake & Signal Holdings Ltd. Solder joint
EP0833384A2 (en) * 1996-09-25 1998-04-01 Siemens Aktiengesellschaft Semiconductor body having a solder layer
EP0833384A3 (en) * 1996-09-25 1999-10-13 Siemens Aktiengesellschaft Semiconductor body having a solder layer

Also Published As

Publication number Publication date
EP0067993A1 (en) 1983-01-05

Similar Documents

Publication Publication Date Title
US4875617A (en) Gold-tin eutectic lead bonding method and structure
EP1223613B1 (en) Electrode structure for semiconductor device, manufacturing method and apparatus for the same
US4661375A (en) Method for increasing the height of solder bumps
WO1982002457A1 (en) Die attachment exhibiting enhanced quality and reliability
KR100318818B1 (en) Protective film bonding to leadframe
JPS6187396A (en) Manufacture of electronic circuit device
JPS59155950A (en) Low melting-point glass seal type ceramic package for semiconductor device
KR920007121B1 (en) Electronic circuit device
US4096983A (en) Bonding copper leads to gold film coatings on alumina ceramic substrate
US4513905A (en) Integrated circuit metallization technique
US4995546A (en) Device mounting
EP0090566B1 (en) Semiconductor device package
JP3601722B2 (en) Die bond solder material
US5046656A (en) Vacuum die attach for integrated circuits
US4504849A (en) Semiconductor devices and a solder for use in such devices
JPS6153851B2 (en)
US4357162A (en) Solder composition
CA1201211A (en) Hermetically sealed semiconductor casing
JP2000195885A (en) Semiconductor device and manufacture thereof
JPH0146228B2 (en)
JPS61181136A (en) Die bonding
Zakel et al. Fluxless flip chip assembly on rigid and flexible polymer substrates using the Au-Sn metallurgy
JPH06338535A (en) Tape automated bonding method utilizing solder bupm
JP2003094194A (en) Fixing method for soldering material and member of electronic part
JPH0717976B2 (en) Semiconductor device

Legal Events

Date Code Title Description
AK Designated states

Designated state(s): JP US

AL Designated countries for regional patents

Designated state(s): AT CH DE FR GB LU NL SE