WO1984000220A1

WO1984000220A1 - Programmable priority arbitration system

Info

Publication number: WO1984000220A1
Application number: PCT/US1983/000094
Authority: WO
Inventors: C Murali Narayanan; Donald Richard Sloan; Benjamin Zee
Original assignee: Western Electric Co
Priority date: 1982-07-02
Filing date: 1983-01-24
Publication date: 1984-01-19

Abstract

A digital system has a resource, such as a communication bus (28), adapted for a access by a plurality of devices, a plurality of devices (0-15) adapted to access the resource, and an arbitrator (27) for arbitrating access to the resource by the devices. The arbitrator includes programmable means (24) for designating order of priority of the devices for accessing the resource, which means are reprogrammable to change the order. The means are further adapted to periodically redetermine the designated priority order in a specified manner, which manner can be changed by reprogramming the means. The priority determining manner may include a constant decreasing priority, a round-robin priority, or a combination of the two. Selecting means (70) responsive to the requesting devices and to the priority designating means select the highest priority requesting device for access to the resource, and access granting means (69) grant to the selected device access to the resource.

Description

PROGRAMMABLE PRIORITY ARBITRATION SYSTEM

Technical Field

This invention relates to the management of shared resources in digital control and processing systems, and in particular to schemes for controlling access to the shared resources in such systems. Background of the Invention

A digital control or processing system, such as a computer system, may include one or more parts, such as memory devices, communication buses, and input/output devices, which are utilizable by other devices of the system as resources for the execution of system tasks. For example, processors may utilize memory as a source of data and instructions and as a resource for storage of results; the processors may also utilize input/output devices as resources for communicating with the outside world, and may utilize buses as communication paths between themselves and the memory or the input/output devices. Memory devices may likewise utilize buses as resources for sending information to processors, while input/output devices may utilize the buses as resources for sending information to memory devices and to processors.

Simultaneous use by a plurality of system devices of the same resource is likely to produce errors. For example, a processor reading data from a memory module while an input/output device is sending data to the memory module may obtain incorrect data; the output of an input/output device may be garbled when two processors simultaneously supply it with output information; and communications passing along a bus may become scrambled and nonsensical when they collide with each other.

It is therefore necessary to provide means within the system to control concurrent access by devices to the shared resources, and to allow only one device at a time to access and make use of a resource. The prior art has generally concerned itself with controlling access to communication paths such as buses, and has provided preassigned fixed time slot allocation, and request arbitration techniques for this purpose.

Of these bus access control techniques, request arbitration has generally been the most efficient. Arbitration schemes require devices wishing to access a bus to request bus use from an arbitration mechanism, which mechanism then selects one from a set of simultaneous requests and grants bus use for a period or slot of time to the selected device. Bus arbitration schemes achieve bus use efficiency by granting time slots only to devices currently wishing to utilize the bus, unlike preassigned fixed time slot allocation schemes which grant time slots to devices irrespective of whether the devices have a need to utilize the bus at that time. Latency, or waiting time of units wishing to access the bus, is thus decreased in the arbitration schemes, and is further improved because using units wishing to use the bus can substantially immediately appraise the arbitration mechanism of this fact, without having to wait for a query from the arbitration mechanism. In contrast, a unit wishing to use the bus in a bus allocation system must wait until its predetermined allocated time slot arrives. Conventional bus arbitration schemes generally implement a fixed, unchanging priority scheme among the using devices. Non-programmable hardware logic generates bus use grant signals as a function of the incoming request signals and a fixed and unchanging priority structure. Such schemes are inflexible because the priority structure is built into the logic hardware and there is no way, short of redesigning the arbitration circuit, to accommodate different applications or changing system configurations and request loads.

The prior art has sought to alleviate these limitations by providing programmable arbitration mechanisms in which the relative priority ordering of the using devices is indicated by the contents of storage devices, such as registers, and hence may be changed by reprogramming the register contents. While providing programmability at one level, these mechanisms have not met the needs of multiprocessor computer systems and other bus-oriented digital systems that require flexible, programmable, class-oriented priority schemes. In such systems, using devices are commonly divided into classes, with each class having a different priority, while devices within a class have the same priority and are generally scheduled to access the bus in a round-robin, equal opportunity, manner. The prior art programmable arbitration mechanisms have traditionally not possessed the flexibility necessary to adapt to such a variety and combination of priority determining manners. Hence the prior art mechanisms have not been capable of meeting the changing needs of a variety of arbitrator applications, configurations of using devices, and device response time requirements. Summary of the Invention

This invention is directed to solving these and other disadvantages of the prior art.

According to this invention, a digital system includes apparatus for controlling access by devices to a resource, which apparatus comprises programmable means for designating order of priority of the devices for accessing the resource, which means are reprogrammable to change the order; the means are also adapted to redetermine the priority order in a specified manner, and the means are reprogrammable to change the manner. The access controlling means also include means responsive to the priority designating means for selecting a device - preferably the highest priority device - for access to the resource. Preferably, the selecting means select only a device wishing to access the resource. Advantageously, the priority designating means comprise a plurality of means, each representing a unique priority level, each for identifying the device currently having that level of priority. "Currently" herein indicates that the device designated for a given priority may change, advantageously up to as often as each time that the access to the shared resource is arbitrated.

Preferably, the priority designating means comprise counter means. The manner for changing the priority order advantageously includes constant decreasing priority, round-robin priority, or a combination of a plurality of manners. Constant decreasing priority herein refers to a fixed, static, priority ordering of the devices or classes of devices, which ordering changes only upon being reprogrammed. Unlike a round-robin priority ordering, for example, the constant decreasing priority is not changed when redetermined between reprogramming. While redetermining may occur as often as each time the shared resource is arbitrated, reprogramming generally occurs less frequently, for example at system initialization or reconfiguration, or at times of load shifts.

The above-described invention is well-suited for use in arbitration schemes, and thus it secures the advantages of high efficiency in time slot allocation and of low access latency for devices. By being reprogrammable in terms of both the order of priority among the devices and the manner of redetermining the priority order, the invention achieves flexibility which enables it to accommodate different applications, changing system configurations, changing request loads, and varying device response time requirements. The invention meets the requirements of class-oriented priority systems, as it is adapted to implement a manner of redetermining the priority order which manner is a combination of a plurality of manners, for example a constant decreasing priority manner among the classes and a round-robin manner among devices within a class. Furthermore, the use of priority order generating counter means aids in adapting the invention for efficient use in systems having relatively large numbers of using devices and for implementation in custom logic designs, particularly large scale and very large scale integrated designs.

These and other advantages of the present invention will become more apparent during the following description of an illustrative embodiment of the invention considered together with the drawing. Brief Description of the Drawing

FIG. 1 is a block diagram of a system embodying an illustrative example of the invention;

FIG. 2 diagrams in block form that portion of the arbitrator of FIG. 1 which is involved in arbitrating access by devices to the system bus of FIG. 1;

FIG. 3 is a block diagram of the permutation network of FIG. 2;

FIG. 4 is a block diagram of the device number selector of FIG. 2;

FIG. 5A is a block diagram of one embodiment of a programmable priority generator of FIG. 2;

FIG. 5B is a block diagram of a second embodiment of a priority generator of FIG. 2; FIG. 5C is a block diagram of the priority designator of FIG. 2 showing a third embodiment of the priority generator of FIG. 2;

FIG. 6 is a flowchart of the operation of the programmable priority generator of FIG. 5A; FIG. 7A diagrams in block form one embodiment of a portion of the arbitrator of FIG. 1, which reads and writes the registers of the programmable priority generators of the FIG. 5A embodiment; and

FIG. 7B diagrams in block form a second embodiment of a portion of the arbitrator of FIG. 1, which reads and writes the registers and counters of the programmable priority generators of the FIG. 5B embodiment. Detailed Description

While the present invention may be utilized in any suitable digital system for controlling access by any suitable number of devices to any suitable resource, for purposes of illustrating the invention FIG. 1 shows a particular system 20 embodying the invention. SYSTEM

The system 20 is a multiprocessor computer system in which a plurality of devices 0-15, such as processor units 0-12, I/O units 13-14, and a shared memory unit 15, communicate with each other across a system bus 28 which serves as a shared communication medium for the system 20. The system 20 further includes a system maintenance and initialization block 29 which is connected to the devices 0-15 by a maintenance bus 16. The block 29 performs conventional initialization and maintenance functions in the system 20.

In order to preserve the integrity of communications within the system 20, an arbitrator 27 is associated with the bus 28 and allows only a single device 0-15 to transmit on the bus 28 at any one time. The arbitrator 27 is connected to the maintenance bus 16 for initialization, as described further in conjunction with FIGS. 7A-7B.

Each of the devices 0-15 has a REQUEST line 31-46, respectively, and a GRANT line 51-66, respectively, connecting it to the arbitrator 27. The lines 31-46 and 51-66 provide signaling paths between the arbitrator 27 and the devices 0-15.

When a device 0-15 wishes to access the system bus 28 for purposes of sending a communication thereon, it asserts its associated REQUEST line 31-46 to request access to the bus 28 from the arbitrator 27. The arbitrator 27 receives the request from that, and any other, device 0-15 wishing to use the bus 28. When a plurality of devices 0-15 request use of the bus 28 substantially simultaneously, i.e., within the same predetermined period of time, or while the bus 28 is in use, the arbitrator 27 selects one of the requests according to some order of priority and signals the selected device 0-15 over the associated GRANT line 51-66 that it has been granted access to the bus 28.

Alternatively, the GRANT lines 51-66 may be replaced by a common GRANT bus (not shown) that is connected to all of the devices 0-15. In such a configuration, the arbitrator 27 generates identification (ID), such as the device number, of the selected device 0-15 and broadcasts it along the GRANT bus to all of the devices 0-15. Each device 0-15 has an ID decoder (not shown) associated therewith and adapted to recognize the ID of its associated device 0-15. The ID decoder of the selected device 0-15 recognizes the broadcast ID and signals the device 0-15 that it has been awarded the grant of access to the system bus 28. ARBITRATOR Turning now to FIG. 2, there is shown diagramed the portion of the arbitrator 27 which is involved in selecting a device 0-15 for access to the bus 28. Another portion, involved in programming the arbitrator 27 is shown in and discussed in conjunction with FIGS. 7A-B. As the system 20 includes 16 devices 0-15, the arbitrator 27 must distinguish 16 levels of priority to uniquely designate the priority level of each device 0-15. For this purpose, the arbitrator 27 includes a priority designator 24 whose outputs designate the current order of priority of the devices 0-15. The priority designator 24 of this illustrative embodiment comprises 16 programmable priority generators 71-86, each of which is associated with one priority level. The first generator 71 is associated with the highest priority level, the second generator 72 is associated with the second highest priority level, and so on, down to the generator 86 which is associated with the lowest priority level. Each generator 71-86 generates the identification, such as the device number, of the unique device 0-15 currently having that level of priority. The generators 71-86 are preferably all the same, and for illustrative purposes the generator 71 is discussed in further detail in conjunction with FIG. 4. Each generator 71-86 outputs the device number in binary form onto four DEVICE NO. leads which connect the generator 71-86 to control ports of a permutation network 67 and a device number selector 70. Thus the network 67 and the selector 70 each have 64 control inputs from the priority designator 24.

The REQUEST lines 31-46 from the devices 0-15, respectively, are connected to an input port of the permutation network 67. The permutation network 67 is a conventional logic network whose outputs are simply its inputs, possibly rearranged according to some predetermined order. The network 67 reorders the REQUEST lines 31-46 in the order of the priority of their associated devices 0-15, as specified by the inputs from the priority generators 71-86. The permutation network 67 is diagramed in FIG. 3.

As that figure shows, the network 67 is comprised of a set of 16 sixteen-to-one multiplexers 91-106. The 16 REQUEST lines 31-46 are connected to the input port of each multiplexer 91-106. The select (SEL) input port of each multiplexer 91-106 is connected to the four DEVICE NO. leads from the associated priority generator 71-86, respectively. Based on the input from the associated priority generator 71-86, each multiplexer 91-106 selects a single REQUEST line 31-46 for connection to its output lead. Thus the multiplexer 91 connects the REQUEST line of the highest priority device 0-15 to its output, the multiplexer 92 connects the REQUEST line of the second highest priority device 0-15 to its output, and so on down to the multiplexer 105 which connects the request line of the second lowest priority device 0-15 to its output, and the multiplexer 106 which connects the REQUEST line of the lowest priority device 0-15 to its output. The output leads of the multiplexers 91-106 are arranged sequentially such that the request lines at the output of the network 67, referred to as the PRIORITIZED REQUEST lines, are arranged in the order of priority of their associated device 0-15, with the leftmost line representing the highest priority device 0-15.

While FIG. 3 shows the permutation network 57 constructed from a single stage of multiplexers, it will be clear to those skilled in the art that other embodiments and configurations of devices to achieve the same functionality are possible.

Returning now to FIG. 2, the PRIORITIZED REQUEST lines at the outputs of the permutation network 67 are connected to an input port of a sixteen-to-four priority encoder 68. The encoder 68 is any suitable device or set of devices that finds the highest priority asserted REQUEST line from the PRIORITIZED REQUEST lines and encodes the number of that REQUEST line. Those skilled in the art can readily construct a sixteen-to-four priority encoder from commonly available eight-to-three or four-to-two priority encoder parts.

If devices 0-15 request access to the system bus 28 by asserting their REQUEST lines 31-46 low, (i.e., logic 0), and the PRIORITIZED REQUEST lines 31-46 are arranged at the output of the network 67 such that the leftmost REQUEST line is the highest priority REQUEST line, the priority encoder 68 is a conventional sixteen line "find leftmost zero" circuit. The number of the selected REQUEST line is a function of its position relative to the other REQUEST lines among the PRIORITIZED REQUEST lines. The leftmost position is REQUEST line number 0, while the rightmost position is REQUEST line number 15. In the above example, if the selected line were the one connecting to the output of the multiplexer 91 (see FIG. 3), the encoder 68 would identify it as the REQUEST line number 0, while if the selected line were the one connecting to the output of the multiplexer 106, the encoder 58 would identify it as the REQUEST line number 15. The encoder 68 has four PRIORITY LINE NO. output leads across which it outputs the number of the selected line. The priority encoder 68 has an additional output lead referred to as NO REQUEST lead, which it asserts when none of the REQUEST lines are asserted and hence no access to the bus 28 is granted.

The four PRIORITY LINE NO. leads are connected to a control input port of the device number selector 70. Other inputs to the selector 70 comprise the 64 DEVICE NO. leads from the priority designator 24. The selector 70 uses the DEVICE NO. inputs to convert the number of the line selected by the encoder 68 into the number of the corresponding selected device. The selector 70 is diagramed in FIG. 4.

As is shown by that figure, the selector 70 comprises four 16:1 multiplexers 126-129. Each multiplexer 126-129 has its input port connected to one DEVICE NO. line from each of the priority generators 71-86 of the priority designator 24. The 16 DEVICE NO. lines connected to one multiplexer 126-129 are all of the same order. For example, the multiplexer 126 is connected to the DEVICE NO. lines which specify the most significant binary digit of the device numbers generated by the generators 71-86, while the multiplexer 129 is connected to the DEVICE NO. lines which specify the least significant binary digit of the device numbers generated by those generators 71-86.

The four PRIORITY LINE NO. leads from the encoder 68 are connected to the select (SEL) input port of each of the multiplexers 126-129. As a function of the select inputs, each of the multiplexers 126-129 selects one of its 16 inputs from the generators 71-86 for connection to its output. The selected input is the input from the generator 71-85 whose priority level corresponds to the line number generated by the encoder 68. Thus, for example, if the PRIORITY LINE NO. leads specify the first line, the multiplexers 126-129 select the input leads from the first priority generator 71; if the second line is specified, the input leads from the second priority generator 72 are selected; and so on. The priority line number is thus converted by the selector 70 into the device number of the device selected for access to the bus 28. The device number of the selected device is output by the selector 70 onto four PRIORITY DEVICE NO. leads.

As shown in FIG. 2, the PRIORITY DEVICE NO. leads from the selector 70 are connected to a select (SEL) input port of a device decoder 69, while the NO REQUEST lead from the encoder 68 is connected to an enable (EN) input of the decoder 69. Outputs of the decoder 69 are connected to the 16 GRANT lines 51-66. The decoder 69 responds to the priority device number input from the selector 70 by asserting the GRANT line of that device 0- 15 to signal that device 0-15 that it has been granted access to the system bus 28. When no requests are present and the priority encoder 68 asserts the NO REQUEST lead, the decoder 69 is disabled from asserting any of the GRANT lines 51-66, and consequently none of the devices 0-15 become enabled to use the bus 28.

In the above-described alternative wherein GRANT lines dedicated to individual devices 0-15 are replaced by a GRANT bus connected to all of the devices 0-15, the decoder 69 is not used and the GRANT bus (not shown) is connected to the PRIORITY DEVICE NO. output leads of the selector 70 and to the NO REQUEST lead of the encoder 68. The decoding function of selecting the device whose number is output on the GRANT bus is then performed by the comparators (not shown) one of which is located at each device 0-15. Each comparator compares the GRANT bus contents with the device number of the associated device 0-15. When a comparator detects a match and when the NO REQUEST line is not asserted, the comparator outputs a signal to the associated device 0-15 to advise it that it has been granted access to the bus 29. PROGRAMMABLE PRIORITY GENERATORS

Returning now to a consideration of the programmable priority generators 71-86 of the priority designator 24, they are substantial duplicates of each other, and hence only one, the generator 71, need be considered in detail, it being understood that the discussion applies to the others as well.

One embodiment of the generator 71 is diagramed in FIG. 5A. The generator 71 is founded on a loadable 4- bit binary counter 111. The counter 111 generates the device number of the device 0-15 currently having the highest priority of access to the bus 28 and outputs the device number onto the four DEVICE NO. leads connecting the generator 71 to the permutation network 67 and to the device selector 70. In like manner, the counter 111 of the generator 72 generates the device number of the device 0-15 currently having the second highest priority, and so on down to the counter 111 of the generator 86 which generates the lowest priority device number. The counter 111 is a synchronous load counter.

Its clock (CLK) control input is connected to a CLOCK lead from a source of periodic timing signals, such as a system clock (not shown) that synchronizes the operation of the various portions of the system 20. Alternatively, the system clock may be gated (not shown) within the arbitrator 27 to produce a CLOCK pulse to update the counter 111 only if a request occurred, i.e., the NO REQUEST lead was not asserted, during the last system clock pulse time. The counter 111 also has a load (LD) control input at which the counter 111 receives commands directing it to be loaded. Both the count and load operations of the counter 111 are synchronous - occurring only when clocked. If the LD input is asserted and a timing pulse is received at the CLK input, the counter 111 is parallel loaded with a new value. If the LD input is not asserted and a timing pulse is received at the CLK input, the counter 111 increments its count its value by 1. When no timing pulse is received, the counter 111 retains its present value.

Associated with the clock 111 are a trio of 4- bit registers: an "initial" register 107, a "final" register 109, and a "restore" register 108. The four bit outputs of the registers 107 and 108 are connected to separate input ports of a quad 2:1 multiplexer 110. The four bit output port of the multiplexer 110 is connected to a loading input port of the counter 111. The select (SEL) control input of the multiplexer 110 is connected to an INITIALIZE line which forms a part of the maintenance bus 16. The INITIALIZE line is also connected through an OR gate 113 to the LD control input of the counter 111. The INITIALIZE line is asserted within the system 20 by the maintenance and initialization block 29 upon initialization of the system. The INITIALIZE line is synchronized with the system clock using a flip-flop (not shown), either within the maintenance and initialization block 29 or within the arbitrator 27. The LD control input of the counter 111 is also connected through the gate 113 to the output of a 4-bit comparator 112, whose inputs are the 4 bit outputs of the "final" register 107 and of the counter 111.

The "initial" register 107 holds the device number of the device 0-15 which is the first of the devices 0-15 to have the associated, in this case the first, priority of access to the system bus 28. When the INITIALIZE line is asserted upon initialization of the system 20, the multiplexer 110 responds by connecting its output port to the output of the "initial" register 107, thus conveying the contents of the register 107 to the loading input port of the counter 111. The assertion of the INITIALIZE line also asserts the LD input of the counter 111, and a subsequent timing pulse received at the CLK input therefore causes the counter 111 to be loaded with the device number contents of the register 107. The counter 111 places this device number on its outputs to the permutation network 67, the device selector 70 and the comparator 112. When the INITIALIZE line, and hence the LD input, cease to be asserted, the counter 111 begins to count from this number: upon every receipt of a clock signal at its CLK input it increments this number, causing its output to change accordingly.

At the comparator 112 the output of the counter 111 is compared with the contents of the "final" register 109, which holds the last, or maximum count, or device number, which the counter is allowed to reach. When the comparator 112 senses that the comparands are equal, i.e., that the output of the counter 111 has reached the contents of the "final" register 109, the comparator 112 asserts the LD input to the counter 111 to cause the counter 111 to be reloaded upon the receipt of the next timing pulse. However, the INITIALIZE line is no longer asserted, and hence the multiplexer 110 connects the loading inputs of the counter 111 to the output of the "restore" register 108, resulting in the loading of the counter 111 with the register 108 contents.

The register 108 contains the minimum count, or device number, which the counter 111 is allowed to reach. It is the number from which the counter 111 henceforth begins its count, except on reassertion of the INITIALIZE line. The counter 111 again places this device number on its outputs to the permutation network 67, the device selector 70, and the comparator 112, and begins to count up from this number.

The synchronous counter 111 utilized herein is of the master/slave or edge-triggered flip-flop type. It samples its inputs and changes its outputs at different times. Hence, there exists no "race" between the changing of the outputs of the counter 111 and the computing of its LD input. Such synchronous design techniques are known to those skilled in the art.

When the counter 111 again reaches the count equal to the contents of the "final" register 109, its count is once more reset to the contents of the "restore" register 108. Thus the counter 111 cycles repetitively through the count from the "restore" register 108 contents to the "final" register 109 contents. The above-described operation of the counter 111 is summarized by the flowchart of FIG. 6. One loop of those shown by FIG. 6 is performed once for each timing clock pulse received at the CLK input.

The initial condition affecting the operation of the counter 111 is whether or not the INITIALIZE lead has been asserted. Upon startup, the lead is asserted, causing the counter 111 to be loaded with the contents of the "initial" register 107, upon the receipt of a timing clock pulse. The counter 111 displays its contents at its output. Following initialization, the INITIALIZE lead ceases to be asserted.

Henceforth, the device number output of the counter 111 is compared with the contents of the "final" register 109. When the comparison does not indicate equality, the contents of the counter 111 are incremented by 1, upon the receipt of a clock pulse, and the comparison is repeated in the next loop.

When the count of the counter 111 does come to equal the contents of the "final" register 109, the counter 111 is loaded with the contents of the "restore" register 108, upon the receipt of a clock pulse.

In subsequent loops, the comparison is repeated and again the contents of the counter 111 are incremented by 1 upon the receipt of each clock pulse, until the counter 111 contents again equal the contents of the "final" register 109, causing the resetting of the counter 111 contents to the contents of the "restore" register 108. Thus the operation of the counter 111 can be seen to repeatedly follow a counting loop.

Should the INITIALIZE lead be reasserted at any time, the count of the counter 111 is again reset to the contents of the "initial" register 1 07, and the above-described operation is repeated.

As can be seen, the device number output of the programmable priority generators 71-86, and hence the order of priority and manner of determining the order of priority of the devices 0-15, is specified by the contents of the trio of registers 107-109 of each of the generators 71-86. By changing the contents of the registers 107—109 of the generators 71-85, the order of priority of the devices 0-15 and the manner of determining their priority order may be changed. To illustrate this condition, a few examples thereof are given below. EXAMPLE 1

Assume that it is desired to arrange the 16 devices 0-15 in a constant decreasing priority manner with the priority order of the devices being such that the device 0 has top priority, the device 1 has second highest priority, and so on, with the device 15 having the lowest priority. The contents of the registers 107-109 of each generator 71-86 that accomplish this result are presented in Table 1.

It will be noted that in this configuration, the device number output of each generator 71-86 is unchanging and thus the priority order of the devices 0-15 is constant and unchanging. EXAMPLE 2

Now assume that it is desired to change the Example 1 priority order of the devices 1, 7, 13, and 14 such that device 13 has second priority, device 1 has eighth priority, device 7 has 15th priority and device 14 has 14th priority. However, it is still desired to maintain the constant decreasing manner of determining priority. The contents of the generator registers 107-109 that accomplish this result are presented in Table 2.

As can be seen from Table 2, the change in priority is accomplished by changing the contents of the registers 107-109, and hence the output of the counters 111 of the priority generaters associated with the reassigned priority levels. EXAMPLE 3 Assume that it is desired to change the manner of determining device priority from the constantly decreasing priority manner of Example 1 to a round-robin manner. The registers 107-109 of each generator 71-86 are reprogrammed to accomplish this result with the contents presented in Table 3. -

P

It will be noted that in this configuration, the sequence of numbers output by each generator 71-86 is the same, as designated by the contents of the registers 108 and 109, but the outputs of the generators 71-86 are offset in time with respect to each other, as designated by the contents of the register 107. EXAMPLE 4

Now assume that it is desired to assign the following, essentially arbitrary, mixture of constant decreasing priorities by class, with devices within each class having round-robin priority: device 7 has top priority, devices 5 and 6 form a class having second highest priority, devices 1-4 form a class having third highest priority, device 0 has fourth highest priority, devices 8-13 form a class having lowest priority, and devices 14 and 15 are not scheduled to access the bus 28. To implement this priority scheme, the generator registers 107-109 are programmed with the contents shown in Table 4.

Since device numbers 14 and 15 do not appear in Table 4 and are not produced by any priority generator, devices 14 and 15 are never granted bus access.

When all possible device numbers are not assigned priorities and hence are not give bus access, the lowest priority generators are assigned arbitrary device numbers from the set of device numbers which have been assigned to higher priority generators, which devices have access to the bus. In the example of Table 4, since the two devices 14 and 15 do not have bus access, the two lowest priority generators 85 and 86 are assigned arbitrary values. Any other value from the set of devices assigned higher priorities, namely devices 0-13, could have been assigned to either of the lowest priority generators 85 and 86.

As long as the device number assigned to the lowest priority generators belong to the set of devices assigned to higher priority generators, the device numbers which they generate have no impact on the device which is granted access. The specific devices assigned to the lowest priority generators will be granted or not granted access based on their requests and highest assigned priorities and the requests and highest assigned priorities of all other devices.

The ability to not grant access to all possible device numbers in a system has advantages in partially equipped systems or in fault tolerant systems which need to isolate failed devices.

Leaving now the consideration of the examples and returning to the figures, FIG. 5B diagrams an alternative embodiment of the generator 71. This embodiment of the generator 71 reflects implementation of the arbitrator 27 in the IBM LSSD technique. This technique is known to the art and is described in the published technical literature, for example, by E. B. Eichelberger and T. W. Williams in "A Logic Design Structure for LSI Testability", Proceedings of the 14th

Design Automation Conference (New Orleans, LA, June 20-22, 1977), pp. 462-468, and by L. A. Stolte and N. C. Berglund in "Design for Testability of the IBM System/38", Digest of. Papers of the 1979 IEEE Test Conference, (Cherry Hill, NJ, October 23-25, 1979), pp. 29-36.

As FIG. 5B shows, the counter 111 of this embodiment is an LSSD synchronous binary counter with load. The counter 111 of FIG. 5B has the same inputs and outputs, serving the same functions, as the counter 111 of FIG. 5A. In addition, the counter 111 of FIG. 5B has a SCANIN input, a SCAN0UT output, and a SCAN CLOCK input. The counter 111 is connected in series to an LSSD scan loop via its SCANIN input and SCANOUT output. The SCAN CLOCK input is connected to an LSSD SCAN CLOCK line. The counter 111 is initialized via the LSSD scan loop using the LSSD serial scan-in procedure, by a scan shift chain of data bits which is shifted through and into the counter 111 under the control of the SCAN CLOCK input. Therefore, the "initial" register 107, the multiplexer 110, and the OR gate 113 of the embodiment of FIG. 5A are not needed in this implementation of the generator 71. In other respects, the generator 71 of

FIG. 5B is structured and functions in a manner equivalent to the generator 71 of FIG. 5A.

Those skilled in the art can construct alternative counter-based designs wherein the LOAD operation is asynchronous, rather than synchronous, with respect to the CLOCK. Such designs also fall within the ambit of the invention.

As an alternative to the counter-based design shown in FIGS. 5A and 5B, the priority generator 71 may be comprised of a memory unit, in which the contents of each memory word specify a device number, and an address generator which selects one of the memory words at any one time and causes its contents to be output onto the DEVICE NO. leads. In such an embodiment of the generator 71, all the generators 71-86 are preferably combined into a single unit priority designator 24 to avoid unnecessary duplication of circuitry.

Such an embodiment of the priority designator 24 is shown in FIG. 5C. The priority designator 24 is comprised of a programmable memory 200, such as a random access memory (RAM), and an address generator 201. The memory 200 is comprised of a plurality of words 202, each of which is 64 bits wide. The memory 200 is divided into 16 columns 211-226 each 4 bits wide. The bits of the 64 bit memory word may be distributed among several memory modules, depending on the width of the memory package used. Memory packages are typically 1 bit, 4 bit, 8 bits, or 9 bits wide. Each column 211-226 contains a 4 bits long segment 203 of each of the words 202. Each column 211-226 represents a single priority generator 71-86, respectively, and contains the data, the device numbers, that must be generated by the generator 71-86. Each word 202 contains the data, the device numbers, to specify a single particular priority ordering of the sixteen devices 0-15.

Thus, the column 211 specifies all of the devices 0-15 that will at any time have first priority, the column 212 specifies all of the devices 0-15 that will at any time have second priority, and so on down to the column 226, which specifies all of the devices 0-15 that will at any time have sixteenth priority. A segment 203 of the column 211 specifies a single device 0-15 that will have first priority at some period in time, while another segment 203 of the column 211 specifies a single device 0-15 that will have first priority at some other period in time. And a word 202 of the memory 200 specifies a particular order of priority of the devices 0-15, from first priority to last priority, that will exist at some period in time, while another word 202 specifies a particular priority order that will exist at some other period in time. To change the order of priority of the devices

0-15 and/or the manner of determining their priority, the contents of the words 202 of the memory 200 are changed by reprogramming the memory 200.

The words 202 have addresses associated with them, and the address generator 201 generates these addresses, one at a time. The address generator 201 has as inputs the INITIALIZE line from the system maintenance and initialization block 29, and the system CLOCK input. Upon initialization, in response to the INITIALIZE signal and the receipt of a CLOCK pulse, the address generator

201 generates a predetermined address of a word 202 of the memory 200, and thereafter upon the receipt of each CLOCK pulse, it generates a new address according to some predetermined scheme.

Address generators are well known to the art, and the address generator 201 may be any suitable unit. For example, the generator 201 may be a simple binary counter which upon initialization begins to count at 0 and for each received CLOCK pulse increments its output, up to the number of words 202 contained in the memory 200. Having counted to that number, the counter resets its count to 0 upon the receipt of the next CLOCK pulse and begins to cycle through the count again, performing the counting loop over and over again. Alternatively, the generator 201 may be a dynamically traffic-driven device, which monitors the contents of the word 202 that it is currently addressing (not shown) and generates a subsequent address as a function of these contents.

The memory 200 is connected to the DEVICE NO. lines; in particular, the column 211 is connected to the first priority DEVICE NO. lines, the column 212 is connected to the second priority DEVICE NO. lines, and so on down to the column 226, which is connected to the 16th priority DEVICE NO. lines.

Each address generated by the address generator 201 forms an input to the memory 200 where it selects a word 202 for connection to the DEVICE NO. lines. The contents of the word 202, which is currently being addressed, are transferred onto the DEVICE NO. lines and are conducted thereby to the permutation network 67 and to the device number selector 70 (see FIG. 2), as in the case of the embodiments of FIGS. 5A and 5B, to designate the current order of priority of the devices 0-15. PROGRAMMING THE GENERATORS

The registers 107-109 of the generators 71-86 which are implemented in the manner shown in FIG. 5A are initially loaded, or programmed, and thereafter changed, or reprogrammed, in the manner shown in FIG 7A. The generators 71-86 are advantageously implemented in large or very large scale integrated (LSI or VLSI) form. In 1000-gate LSI arrays, the generators are implemented four to a chip. In VLSI, the 16 generators 71-86 and the rest of the arbitrator 27 can be implemented on a single chip. Taking the LSI design as an example, the arbitrator 27 includes four chips 121-124, where chip 121 carries the generators 71-74, the chip 122 carries the generators 75-78, the chip 123 carries the generators 79-82, and the chip 124 carries the generators 83-86. The chips 121-124 also have distributed among them the rest of the circuitry of the arbitrator 27. As the chips 121-124 are the same, only the chip 121 will be discussed in more detail, with the understanding that the discussion applies to the other chips 122-124 as well. The registers 107-109 of the generators 71-86 are programmed and reprogrammed by the maintenance and initialization block 29 of FIG. 1. The block 29 may be implemented in any one of a number of conventional ways. For example, it may be a separate processor which is dedicated to the performance of maintenance and administrative functions. Alternatively, the block 29 may be a simple hardware unit responsible for basic system startup, with other maintenance and initialization functions being assigned to one or more of the devices 0- 15.

The block 29 communicates with the arbitrator 27 via the maintenance bus 16. During initialization of the system 20, the block 29 directly accesses the arbitrator 27 over the bus 16 in a conventional manner. Each of the registers 107-109 has a maintenance address associated therewith, and the block 29 addresses each register 107-109 and loads it with values across the maintenance bus 16. The maintenance bus 16 includes an address bus 21, a data bus 22, a read line 25, and a write line 23. To load a register 107-109, the block 29 outputs the address of that register 107-109 onto the address bus 21, outputs the value to be written into that register 107-109 onto the least significant four bits of the data bus 22, and drives the write line 23 high, then low. Similarly, to read out the value of a register 107- 109, the block 29 outputs the address of that register 107-109 onto the address bus 21 and drives the read line high, then low, causing the register contents to be output onto the data bus 22. The address of each register 107-109 comprises a chip address portion designated by the most significant bits of the address bus 21, which identifies the one of the four chips 121-124 which is being addressed, and a register address portion designated by the four least significant bits of the address bus 21, which identifies the particular one of the twelve registers 121-124 on a chip. In the arbitrator 27, the chip addressing portion of the address bus 21 is connected to an input port of an address decoder/chip selector 120, which decodes the address to identify the one, if any, of the chips 121-124 which is being addressed. The address decoder/chip selector 120 has outputs connected to CHIP SEL lines each one of which leads to one of the chips 121-124. The decoder/selector 120 signals the addressed chip 121-124 by asserting that chip's CHIP SEL line. Assuming that the chip 121 is addressed, the decoder/selector 120 asserts the CHIPO SELECT line.

At the chip 121, the CHIPO SEL line is connected to the enable (EN) control input of a 4:16 decoder 125. Assertion of the CHIPO SEL line enables the decoder 125 to operate and to select one of its 16 outputs. If the CHIPO SEL line is not asserted, none of the outputs of the decoder 125 are asserted. The four least significant bit lines of the address bus 21 lead to each of the chips 121-124, and at the chip 121 they are connected to a select (SEL) input port of the decoder 125. If enabled, the decoder 125 decodes the address appearing on those bit lines to identify the one of the twelve registers 107-109 that is being addressed on the chip 121.

The decoder 125 has 16 output leads, one for each address specifiable by the four bit lines connected to its input port. Four output leads are uniquely associated with each one of the generators 71-74 on the chip 121, and three of the four output leads at each generator 71-74 are connected to enable inputs of that generator's registers 107-109. The fourth lead at each generator 71-74 is unassigned. Upon identifying the register 107-109 that is being addressed, the decoder 125 raises the one of its output leads which connects to that register 107-109.

The four least significant bit lines of the data bus 22 and the read and write control lines 23 and 24 lead to each of the chips 121-124. During a write operation, at the selected register 107-109, the input from the decoder 125 enables the asserted write line 24 to write the selected register 107-109 with the value appearing on the four least significant bits of the data bus 22. Likewise, during a read operation, at the selected register 107-109 the input from the decoder 125 enables the asserted read line 23 to read the selected register's 107-109 value onto the four least significant bits of the data bus 22. Thus, the block 29 can sequentially read or write each of the registers 107-109 in the arbitrator 27. Alternative addressing and decoding schemes can simultaneously read or write a group of registers 107-109. Alternatively, if the arbitrator 27 is implemented via the above-mentioned IBM LSSD technique and hence its priority generators 71-86 take the form shown in FIG. 5B, the arbitrator 27 is programmed and reprogrammed in the manner shown in FIG. 7B. Analogously to the arbitrator 27 of FIG. 7A, the arbitrator 27 of FIG. 7B is constructed of four LSI chips 121-124. The chip 121 carries the generators 71-74, the chip 122 carries the generators 75-78, the chip 123 carries the generators 79- 82, and the chip 124 carries the generators 83-86. The chips 121-124 also have distributed among them the rest of the circuitry of the arbitrator 27. As in the example of FIG. 7A, the programming and reprogramming of the arbitrator 27 of FIG. 7B is done by the block 29 via the maintenance bus 16.

The maintenance bus 16 of FIG. 7B includes an LSSD SCANIN line 87, an LSSD SCANOUT line 88, and an LSSD SCAN CLOCK line 89. The SCANIN line 87 and the SCANOUT line 88 substantially form a loop in which all storage devices of the arbitrator 27 are interconnected in series. Thus, the SCANIN line 87 enters the 0th chip 121 of the arbitrator 27 and connects to a SCANIN input of the RESTORE register 108 of the 1st priority generator 71. A SCANOUT output of the register 108 is connected to a

SCANIN input of the FINAL register 109. A SCANOUT output of the register 109 connects to the SCANIN input of the counter 111, whose SCANOUT output leaves the 1st priority generator 71 and connects to the 2nd priority generator 72 to loop through its registers 108 and 109 and counter 111 in a similar manner. Following the 2nd priority generator 72, the loop extends through the storage devices of the 3rd priority generator 73 and then the 4th priority generator 74. The SCANOUT output of the counter 111 of the priority generator 74 leaves the 0th chip 121 and connects to the 1st chip 122 to loop therethrough in a similar manner. Following the chip 122, the chips 123 and 124 are also looped through, until finally the SCANOUT output of the counter 111 of the 16th priority generator 86 connects to the SCANOUT line 88 of the maintenance bus 16.

The SCAN CLOCK line 89 is connected, in parallel, to the SCAN CLOCK input of each storage device of the arbitrator 27. Preferably, the connection is made through buffers (not shown) to increase the fan-out current drive of the SCAN CLOCK line 89. Thus, the SCAN CLOCK line 89 connects to the SCAN CLOCK inputs of the restore register 108, the final register 109, and the counter 111 of the 1st priority generator 71. The line 89 connects to the other three generators 72-74 of the 0th chip 121 in a similar manner. The line 89 is likewise connected to the chips 122-124.

During initialization of the system 20, the block 29 outputs clock pulses onto the SCAN CLOCK line 89 and synchronously therewith outputs binary data pulses onto the SCANIN line 87. The data pulses output by the block 29 are a string of data representing the contents of all of the storage devices of the arbitrator 27. The data are output onto the SCANIN line 87 in the order of the arrangement of their corresponding storage devices in the scan loop, with the data contents of the last storage device in the loop being output first, and the data contents of the first storage device being output last. Thus, the data string begins with the contents of the last bit of the counter 111 of the priority generator 86 and ends with the contents of the first bit of the RESTORE register 108 of the priority generator 71.

Because each storage device is implicitly "addressed" by its position in the scan loop, no addressing and address decoding logic is needed. For every SCAN CLOCK pulse, the data string shifts, advances, by one bit position away from the SCANIN line 87 and toward the SCANOUT line 88 through the serial scan loop made up of the storage devices of the arbitrator 27, until all of the storage devices are loaded and the arbitrator 27 is initialized. The block 29 reads the contents of the storage devices of the arbitrator 27 in a similar manner: by outputting clock pulses onto the SCAN CLOCK line 89 to shift the data from the storage devices out onto the SCANOUT line 88. For a non-destructive read, the values read out via the SCANOUT output are simultaneously written back in through the SCANIN input. In reference to the embodiment of the priority generator 71-86 shown in FIG. 5C, the art is well acquainted with the programming and reprogramming of conventional memories; hence no discussion thereof is needed here.

Of course, it should be understood that various changes and modifications to the illustrative embodiment described above will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and the scope of the invention and without diminishing its attendant advantages. It is therefore intended that all such changes and modifications be covered by the following claims.

Claims

What is claimed is:

1. A digital system comprising:

(A) a resource

(B) a plurality of devices for accessing the resource;

(C) means for controlling access by the devices to the resource, the controlling means including

(1) programmable means for generating signals designating order of priority of the devices for accessing the resource, the priority designating means being reprogrammable to change the order, the priority designating means further adapted to redetermine the priority order in a specified manner, the priority designating means being reprogrammable to change the manner, and

(2) means responsive to the priority designating signals for selecting a device for access to the resource.

2. The system of claim 1 wherein the access controlling means further comprise means communicative with the plurality of devices for determining which devices wish to access the resource, and wherein the selecting means are further responsive to the determining means for selecting a wishing device for access to the resource.

3. The system of claim 1 further comprising means associated with each of the plurality of devices for providing signals requesting device access to the resource, and wherein the selecting means are further responsive to the requesting signals by selecting a requesting device for access to the resource.

4. The system of claim 1 or 2 or 3 wherein the selecting means are responsive to the priority designating signals by selecting the highest priority device of the selectable devices for access to the resource.

5. The system of claim 1 further comprising means for providing clocking signals to the priority designating means, and wherein the priority designating means are responsive to the clocking signals to redetermine the priority order.

6. The system of claim 1 wherein the priority designating means comprise counter means for generating the signals designating the priority order.

7. The system of claim 1 wherein the priority designating means comprise a plurality of means, each representing a unique priority level, each for generating signals identifying the device currently having that level of priority.

8. The system of claim 7 wherein the device designating means comprise counter means.

9. The system of claim 1 wherein the priority designating means comprise memory means for storing information defining the priority order.

10. The system of claim 1 wherein the priority designating means comprise: a plurality of addressable memory means, each for storing information defining a priority order; and addressing means for cyclically addressing the plurality of memory means.

11. The apparatus of claim 1 wherein the resource comprises a communication medium.

12. The apparatus of claim 11 wherein the medium comprises a communication bus.

13. A digital system comprising:

(A) a resource adapted to be shared by a plurality of devices;

(B) a plurality of devices for generating signals requesting access to the resource;

(C) means associated with the resource for arbitrating access by the devices to the resource, the arbitrating means including

(1) programmable means for generating signals designating order of priority of the devices for accessing the resource, the priority designating means being reprogrammable to change the order, the priority designating means further adapted to periodically redetermine the designated priority order in a specified manner, the priority designating means being reprogrammable to change the manner, and (2) means responsive to the request signals and to the priority designating signals for selecting the highest priority requesting device for access to the rasource; and

(D) means responsive to the selecting means for granting to the selected device access to the resource.

14. The system of claim 13 wherein the priority designating means comprise a plurality of means, each representing a unique priority level, and each for generating signals identifying the device currently having that level of priority.

15. The system of claim 14 wherein the plurality of device designating means comprise a plurality of counter means.

16. The system of claim 13 wherein the priority designating means include counter means for generating the priority designating signals according to the specified manner of redetermining the priority order.

17. The system of claim 13 wherein the priority designating means comprise memory means for storing information defining the priority order.

18. The system of claim 13 wherein the priority designating means comprise: a plurality of addressable memory means, each for storing information defining a priority order; and addressing means for cyclically addressing the plurality of memory means.

19. The system of claim 13 wherein the manner of redetermining the priority order is constant decreasing priority.

20. The system of claim 13 wherein the manner of redetermining the priority order is round-robin priority.