WO1984000223A1

WO1984000223A1 - Method and apparatus for decreasing characters presented on a display

Info

Publication number: WO1984000223A1
Application number: PCT/SE1983/000248
Authority: WO
Inventors: Lars Gunnar Lindstroem
Original assignee: Ericsson Telefon Ab L M
Priority date: 1982-06-23
Filing date: 1983-06-16
Publication date: 1984-01-19
Also published as: JPS59501180A; SE8203920D0; FI840702A0; SE8203920L; DK89884D0; DK89884A; NO840657L; FI840702A; SE431037B; EP0112362A1

Abstract

Method and apparatus, in presentation of characters on a display screen, for presenting these in reduced format in relation to a normal size. The apparatus contains a font memory (CM) for storing the characters in their normal size in a character matrix built up from a plurality of rows and columns and individually associated with each of the characters. Information as to the configuration of the character is also stored in the character matrix. Presentation on the display is controlled by a control unit (CU), in turn controlled by a microprocessor (CP). The principle is that a character can be formed on the display with the aid of juxtaposed dots, of which some are alight and some extinguished, depending on the configuration of the displayed character. A document memory (DM) chargeable from the processor (CP) is addressed from said processor in a reading-out step, and on indication from the control unit (CU) sends the character, determined by the address, in the form of a character- and position-determining binary code to the font memory (CM). Said binary code constitutes the address for the image dot information which is to be fed out from the font memory when the latter is addressed. A reduced character is generated by a plurality of lines and columns in the character matrix being jumped over in accordance with a desired degree of reduction, after indication in the font memory. For example, if halving of the character format is desired, then only alternate columns are read out from the font memory under control of a column address compression circuit (KA) which sends a supplementary address to the font memory, pointing out what columns in the respective character matrix are to be fed out from the memory, depending on the degree of reduction. For n times reduction every nth column is read out on generating the character. For halving in height, the information read out from the font memory is compressed with the aid of a gate network (OR). The result of the reducing operation, e.g. halving, will be that a character is presented on the display which is half as large as the one stored in the character matrix, and for division by n, a character is presented on the display which is reduced n times both in height and width.

Description

METHOD AND APPARATUS FOR DECREASING CHARACTERS PRESENTED ON A DISPLAY

TECHNICAL FIELD

The invention relates to a method and apparatus, in the presentation of alphanumerical or graphical characters on a display, for producing the charac¬ ters in a decreased format in relation to a given normal size.

BACKGROUND ART

The German Offenlegungsschriften nr 2715075 and 2727901 teach different methods for enlarging characters in their presentation on displays. It is also known to change the position and format of the characters on the display.

DISCLOSURE OF INVENTION

As mentioned, the method and apparatus in accordance with' the invention relate to the decrease in size of characters. The known methods are intended to enlarge characters and do not include decreasing their size.

The method and apparatus solving the problem in question are characterized by the claim, and include a symbol or character generator containing a font memory CM in which each character to be presented on a display is stored in a given normal size in a character matrix, consisting of a plurality of rows and columns, individually associated with each of the characters. The character matrix also stored the character configuration in the form of logical ones and zeros. Presentation on the display is controlled by a control unit, in turn activated by a microprocessor, both of which . are manufactured by MOTOROLA, the former denotred M6845 and the latter M68000. The principle is that characters can be formed on the display with the aid of closely lying dots, of which some are alight and some extinguished. The human eye integrates these dots into lines constituting the desired character image. To enable presentation the display unit is divided horizontally and vertically into a plurality of dots, which are lighted or extinguished in response to the configu- ration of the presented character. The information as to what dots (bits) are to be lit on the screen comes from said character generator. A document memory DM contains data as to what character is to be selected in the character generator, and the control circuit M6845 sends synchronizing signals such that the right character address is indicated and the right column selected. A decreased character is generated by the character generator when, after indication in the font memory, a plurality of rows and columns in the character matrix is jumped over according to the desired degree of reduction. For example, if it is desired to halve the character format, only alternate columns are read from the font memory. For a reduction of n times, every nth column is read out when the character is generated. The information read from the font memory CM is compressed in height for the halving process by a gate net OR. The result of the reducing operation will be that a character which is half as large as the one stored in the character matrix will be presented on the display for "halving", and for division by n, a character will be shown on the display which is reduced n times both in height and width.

The advantage of the method and apparatus in accordance with the invention is that, e.g. for halving, the display can be utilized to present twice as many rows and twice as many characters per row. Furthermore, the necessity of storing a bit pattern for the half-size format and increasing the memory capacity for storing the pattern is of course avoided.

BRIEF DESCRIPTION OF DRAWINGS

The method and apparatus in accordance with the invention is described in detail with the aid of an embodiment, and with reference to the accompanying drawings, on which

Figure 1 is a block diagram of the apparatus in accordance with the invention, Figure 2 illustrates examples of character structure for normal and halved character size, and

Figure 3 illustrates a combination of OR-circuits and shift registers in accordance with the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

As will be seen from Figure 1, the apparatus in accordance with the invention includes a control circuit CU for controlling the character configuration on a conventional display. The control circuit is made by MOTOROLA, type MC6845. The principle for controlling the presentation is, as already mentioned, that the character can be formed on a display with the aid of closely lying dots or points of light, of which some are alight and others are extinguished, and that the human eye integrates these light dots into lines constituting the desired character imaga. In the inventive application, these lines are created with the aid of columns, each of which normally contains 24 light dots. In the example, a place on the screen devoted to one character may include 12 such juxtaposed columns, although this number is not fixed at 12, and can be varied. Within this exemplified 24x12 matrix the desired character is created by appropriate light dots being alight or extinguished. The display has room for a total of 25 text rows in the presentation of the characters in their normal size. In the presentation of an image on the display, the electron beam is controlled such that the beam sweeps vertically, starting at the lower left hand corner of the screen. During the first line sweep, 25 columns appear one above the other, the first column in the lower left hand corner of the screen and the last column in the upper left hand corner. Each of the columns includes 24 dots. These are the first columns for each character row presented. After the first sweep, the beam returns to the lower edge of the display and the second sweep starts so that the second column in the character matrix appears. After a completed second sweep the second column in each character row appears on the display. In the example, when twelve such sweeps have been completed, the first character in each row on each of the 25 rows has been presented on the display.

As an example of decreasing a character in the apparatus according to the invention, a halving of the character has been selected for the sake of simplicity, although it is naturally possible to execute reduction by some other factor. By selecting alternate light dot bits from the font memory and alternate columns from the control circuit, the indicated character can be reduced to half its height and half its width. The selection of a character matrix consisting of 24x12 dots as against the normal 16x8 dots enables forming each character two dots thick. By lighting dots in pairs both in height and width there is thus obtained a character thickness which guarantees in said halving of the charac¬ ter format that at least one of the dots in the respective dot pair is lilt, i.e. the configuration of the character is retained. As is further apparent from Figure 1, outputs from the control circuit CU are connected to the inputs on a multiplexor Ml, type 74S157. To further inputs on the multiplexor Ml there are connected outputs from a microprocessor CP made by MOTOROLA, type M68000. In a charging step, character information in ASCII code is written, via the processor and a first bus switch BS1, type 74LS245 into a document memory DM from a keyboard TB connected to the processor. The memory is then charged with the information which is to be read out later and presented on the display. The processor CP analyzes the ASCII codes from the keyboard and distributes the characters to the right places in the document memory, which is a RAM buffer memory made by HITACHI, type MCM 6665-20. The document memory DM is addressed from the processor CP via the multiplexor Ml and further obtains an indicating signal from the control unit CU. In the memory DM there is thus selected what characters shall be presented on the display, and in what position the presentation shall take place. The memory positions thus contain the ASCII codes for the characters which are to be presented in the positions determined by the address. The bus switch BS1, connected to the outputs of the memory DM, has the task of controlling, as necessary, the direction of the data flow to, or from, the memory DM. A holding circuit L, type 74LS377, distributes the ASCII-coded address from the memory DM to a second multiplexor M2, type 74S157. This address information consists of eight bits, and is the ASCII code for the character which is to be presented in a given position on the display. These eight bits are supplied to the address inputs on a font memory CM, made by HITACHI, type MCM 6665-20, and indicate the dot presentation for a given character in the memory CM. Accordingly, what dots in the dot matrix of a character that are to be lit on the display are determined in the memory CM. The ASCII code indicates all of the 288 dots (24x12) in the dot matrix. However, the ASCII code is supplemented in the multiplexor M2 by a further code of 5 bits determining which of the 12 juxtaposed columns are addressed in the character matrix. This column address code is sent from the control unit CU to a column address compression circuit KA, type 74LS569, via said multiplexor M2 to further address inputs on the font memory CM. The circuit KA consists of a controllable shift register which normally givens the same address on its output as is received on its inputs when no reduction is desired. Accordingly, this means that in a normal case each of the columns is indicated in the character dot matrix. The ASCII code for a given character is fed out as an address from the document memory DM to the font memory CM, as many times as correspond to the number of columns in the character. For 12 columns, each character address is thus fed out 12 times. The information is read out from the outputs on the memory CM, in binary form for the selected dot pattern, to the inputs on a second bus switch BS2, type 74LS245, the task of which is to determine the data flow direction, i.e. from or to the memory CM. The information is fed from the outputs on the switch BS2 to the inputs on a gate network OR consisting of a plurality of OR circuits, type 74LS32. From the OR circuits the information is fed to the inputs on a plurality of shift registers SR, type 74LS377. The function of the OR circuits is to feed information to the register SR as to what dots are to be lit on the display under the control of signals El, E2, E3, which are applied from the processor CP to the inputs on the network OR, in response to whether each dot or alternate dots are to be Hit, i.e. whether the normal-sized character or reduced size character is desired. Figure 3 illustrates the combination of OR circuits according to the invention.

When no reduction is desired, the control input E2 is given a signal from the processor CP, which causes dot pattern for the selected character to be transferred unchanged to the screen. The control inputs El and E3 are activated in the decreasing process, but not E2, such that only alternate dots are lit in the vertical direction. The character is then presented at half its height in relation to the normal case. For obtaining half the characrer width as well, a control , input E4 on the compression circuit KA is activated, such as to function as a multiplier with the factor 2. A reduction sequence with the aid of the apparatus in accordance with the invention is performed in the following manner.

Let it be assumed that a character embracing 24x12 dots in the matrix is to be presented on the display matrix address 0 (zero), MA-0. Addresses supplied to the document memory DM via the multiplexor Ml indicate the cell in the memory which contains the ASCII code for the character which is to be presented in a given position on the display, which in the selected case is the lower left matrix (MA-0) on the display. The ASCII code is sent via the bus switch BS1 to the holding circuit L. The bus switch BS1 is set in a position such that data flows from the document memory DM to the holding circuit. The character address is distributed from the holding circuit outputs to the inputs on the multiplexor M2. This address, thus constituting the ASCII code for the character which is to be presented in position MA-0 on the display, consists of eight bits. These eight bits indicate a dot representation of a particular character in the font memory CM. As previously mentioned, a character matrix which is 24 dots high and 12 dots wide corresponds to this dot represen¬ tation. After feeding out from the multiplexor M2 to the font memory CM, the ASCII code indicates all 288 dots in the given matrix. If there are 12 columns in each character, then the ASCII code is fed out from the document memory DM to the address inputs on the font memory CM twelve times for each character.

In order to determine which of the 12 vertical columns in the matrix are to be activated, the ASCII code in the multiplexor M2 is extended by a further five bits, which, on reception in the font memory, define what column is to be read out. This supplementary address is obtained, as mentioned earlier, from the column address circuit KA, the inputs of which are fed from the control unit CU. In normal use of the display equipment, no reduction of the characters takes place. The control input E2 of the gate network OR is then acti¬ vated (Figure 3), the signals from the font memory CM via the bus switch BS2 to the inputs a-x on the gate network OR passing it without being affected. The shift register SR is thus supplied with a complete, unreduced column embracing 24 dots.

The column address compression circuit KA functions such that the control input E4 is not activated in normal operation. Each column in the character matrix is then pointed out from this circuit.

In decreasing e.g. halving, twice the number of rows and twice the number of characters per row are read out from the document memory DM under control of the control unit CU, as an address to the font memory CM. The halving order is triggered from the keyboard TB. The control input E4 is activated on the column compression circuit, and only alternate columns are pointed out in the font memory. In feeding out halfsized formats, the control input E2 to the gate network OR is deactivated, instead, it is activated during a column period (the time it takes for reading out a column from the font memory CM. The input E3 to the circuit OR is not activated in this position, and alternate bits of the font memory data are now fed out to the first half of the shift register SR. For the nest column time, the input E3 is activated and the input El deactivated such that alternate bits from this second column are fed to the other half of the shift register. The shift register SR is thus filled with compressed columns from two vertically juxtaposed characters. This information is fed conventionally from the shift register to a display dot memory \/OC for further feeding to the display. The memory VOC is a RAM memory, type MCM 6664-20, and is used as a buffer memory in which information from the shift register SR is written in at a low rate, and from which reading-out to the display takes place at a high rate. The memory sends refresh information, to the screen CRT. The column address compression circuit KA is activated, as mentioned, for feeding out halfsized formats so that when the first sweep line (address - 0) is fed out, and the control circuit CU sends the address information to the circuit KA for the second vertical line, this address is multiplied by 2, such that the third line (address - 2) is fed out from the font memory CM instead. This accordingly results in that alternate vertical columns are fed out to the shift register SR for presentation of the character image. A character which is reduced to half the normal size stored in the character matrix is thus displayed in the manner described.

All the clock signals are supplied by a clock signal unit CL common to the system, but unillustrated. "~

Reading and writing in the memories has not been described in detail, since this is known to the art.

With the. aid of the apparaus in accordance with the invention there is achieved great gain in space on the display, without deterioration of clarity in presen¬ tation.

OMPI

Claims

1. A method in the presentation on a display unit of characters generated by a character generator containing a front memory for storing characters in normal size in a character matrix built up from a plurality of rows and columns and individually associated with each of the characters, of presenting charac- ters in a format less than said normal size, c h a r a c t e r i z e d in that the characters stored in the font memory are caused to be fed to the display in the form of a partial quantity of the memory content for the corresponding character, and in that in the presentation of a given partial quantity it is arranged that juxtaposed dots on the display are lit in correspondence to said partial quantity, for n times reduction of the character format only every nth row and every nth column from said character matrix being presented on the display.

2. Method as claimed in claim 1, c h a r a c t e r i z e d in that for its normal size said character is disposed for presentation in the form of double dots.

3. Apparatus for carrying out the method as claimed in claim 1, in the presentation on a display unit of characters generated by a character generator containing a font memory for storing characters in normal size in a character matrix built up from a plurality of rows and columns and individually associated with each of the characters, of presenting characters in a format less than said normal size, c h a r a c t e r i z e d in that a document memory (DM), charge¬ able with characters from a processor (CP), is addressed on its address inputs from said processor via a first multiplexor (Ml), and that on indication from a control unit (CU) controlled by said processor the memory sends on its data outputs, via said first multiplexor, the indicated character stored in the memory (DM) and determined by the address, in the form of a character- and position determining binary code, to address inputs on a font memory (CM) via a first bus switch (BS1), a holding circuit (L) and a second multiplexer (M2), said

-binary code constituting the address for which image dot information shall be fed out from the font memory (CM) on addressing;

in that a compression circuit (KA) via a control input (E4); is addressed and controlled from the control unit. Said circuit being of the type which when unactivated sends the same address on its outputs as it received on its inputs, and when activated, said control input sends the supplied address in compressed form as a supplementary address to the font memory (CM) indicating what columns in the respective character matrix are to be fed out from the memory in response to the degree of reduction;

a controllable gate network (OR) _'is connected to the outputs of the font memory (CM) via a second bus switch (BS2), said network sending on its outputs, in response to activation of a plurality of control inputs (E1-E3), image dot information to a shift register (SR) saying what dots ϊn a vertical direction which, dependent on the degree of reduction, are to be presented on the display, the register information being written into an image dot memory (VOC) and read out to the display such that dots are lit on the display corresponding to the desired characters, positions and degree of reduction.