WO1984002580A1

WO1984002580A1 - Vlsi chip with integral testing circuit

Info

Publication number: WO1984002580A1
Application number: PCT/US1982/001819
Authority: WO
Inventors: John J Zasio
Original assignee: Storage Technology Partners
Priority date: 1982-12-27
Filing date: 1982-12-27
Publication date: 1984-07-05
Also published as: EP0130974A1

Abstract

A VLSI integrated circuit chip (10) includes integral test circuitry formed on the chip. The test circuitry includes a shift register (20) comprising a plurality of latches located adjacent the input/output pads (14) of the chip (10). Control circuitry (18) is included which causes test data to be serially entered into the shift register (20) and then clocked into the internal circuit (12) of the chip (10) in order to test the chip operation. The output signals generated by the internal circuit (12) in response to the test signals are transferred to the shift register (20). The contents of the shift register (20) are then serially shifted out of the device and may be compared with desired results in order to determine whether or not the chip (10) is operating properly. The inclusion of the circuitry greatly reduces the number of pads (14) which must be contacted to test the chip (10).

Description

VLSI CHIP WITH INTEGRAL BSTIHG CIRCUIT BACKGROUND OF THE INVENTION

1. Pield of the Invention

This invention relates to large scale and very large scale integrated circuits (LSI and VLSI) and more particularly to integrated circuit chips including CMOS logic circuitry. Still more particularly, the present invention relates to VLSI chips including integral test circuitry which is utilized to test the chip prior to packaging in an integrated circuit package.

As VLSI technology progresses, an increasing number of semiconductor devices can be formed on a single chip. As the number of devices, and therefore functions, of the chip increase the number of input/output (I/O) pads also increases. Recently developed chips have included as aany as 256 I/O pads. One reas for the development of chips containing so aany I/O pads is for use in high-speed computers in which it is desired to avoid time sharing of pads in order to maximize operating speed.

The yield in a chip manufacturing process (i.e., the number of properly operating chips obtained from each wafer) is often less than 10 percent. Therefore, chip testing is generally done while the chip is part of a wafer. The wafer is then separated into individual chips and properly operating chips are packaged integrated circuits. In order to test a chip, it is necessary t make electrical contact with some or all of the I/O pads. A faulty connection can result in a determination that the chip under test is defective, even though such aay not be the case. 2. Description of the Prior Art

The most common device for testing chips is a probe which physically contacts each one of the I/O pads of the chip. With smaller sized chips, contact is not difficult and this device is acceptable. As the number of pads increases, however, it become very difficult to produce a probe which can aake positive contac with each I/O pad. Slight angular rotation of the probe with respect to the chip will cause misalignment and aissed contact, thereby resulting in a determination that the chip is faulty. Probes of this type which are used to test large chips are extremely expensive due to the rigid aechanical tolerances which must be aaintained in order to insure that proper contact will be aade with the I/O pads. In order to reduce the number of connections which aust be aade by the test probe, and therefore increase the reliability of the electrical connection between the probe and the chip, an IC has been developed in which multiplexer circuitry is formed on the chip adjacent the main chip circuit. A multiplexer is provided on each of the four sides of the chip, and test signals are multiplexed into all of the I/O pads on each side. This system is described in ϋ. S. Patent No. 4,180,772 issued to John J. Sasio. Although this device reduces the number of I/O pad connections which must be made, alignment of the probe to the chip is still difficult. This is due to the fact that connections aust be made on all four sides of the chip. In order to properly align the probe to the chip it is necessary to view the I/O pads under relatively high magnification. However, as the magnification is increased to a suitable level, the field of view is often not large enough to encompass the entire chip and therefore all of the I/O pads. Simultaneous viewing of all of the I/O pads at the necessary magnification thus becomes impossible. Furthermore, the multiplexer test circuitry of the prior art device is designed to be removed from the chip after testing is accomplished, resulting in the waste of a significant amount of semiconductor material.

OMPI SUMMARY OF THE INVENTION

The present invention is directed to an improvement in the testing of integrated circuits containing a large number of I/O pads. In general, the invention includes an integrated circuit having integral test circuitry which includes a shift register having storage locations corresponding to some or all of the I/O pads. Test signals are serially entered into the shift register and subsequently transferred from the shift register into the internal circuit of the chip to thereby test the chip. Output signals which are generated by the internal circuit in response to the application of the test signals are transferred to the shift register and subsequently serially shifted out of the register. Control of the testing operation is provided by clock circuitry which requires a very small number of I/O pad connections. The shift register technique greatly reduces the number of I/O pads which must be contacted to perform a test on the chip. Furthermore, all of the I/O pads to which connection is required for testing may be located on a single side of the chip, thereby facilitating viewing of the connections under the necessary magnification. The chip may be designed so that the test circuitry remains a part of the chip and can be utilized after packaging in order to perform further tests. The integral test circuitry is especially useful when the chip is fabricated with CMOS devices, since CMOS has the characteristic of little or no power drain under DC conditions. When the test circuitry of the present invention is incorporated into the chip, the associated probe which is utilized to test the chip may be a very simple and inexpensive device. The cost of providing additional circuitry on the chip to facilitate testing is therefore outweighed by the fact that the cost of testing is greatly reduced.

OMPI BRIEF DESCRIPTION OF THE DRAWING

The invention will be described with reference to the accompanying drawings wherein:

FIGURE 1 is a diagra atic top plan view of the chip of the present invention.

FIGURE 2 is a top plan view of a corner of the chip showing control circuitry used in testing the chip.

FIGURE 3 is a schematic diagram of an input driver and associated latch.

FIGURE 4 is a schematic diagram of an output driven and associated latch.

FIGURE 5 is a block diagram showing the provision of complementary inputs to the control circuit.

FIGURE 6 is a schematic diagram of the input buffer of FIGUR 5.

FIGURE 7 is a schematic diagram of clock circuitry utilized to generate timing signals to control the testing of the chip.

FIGURE 8 is a timing diagram showing various operations of the test circuit.

FIGURE 9 is a schematic diagram of the output circuitry of the test circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The following description is of the best presently contemplated mode of carrying out the invention. This descriptio is not to be taken in a limiting sense but is made aerely for the purpose of describing the general principles of the invention. The scope of the invention should be determined with reference to the appended claims.

Referring to FIGURE 1, the present invention comprises an integrated circuit 10 which includes internal circuitry 12 connected to a plurality of I/O pads 14 via I/O drivers 16. The integrated circuit in the present embodiment employs very large scale integration (VSLI) and includes two hundred and fifty-six I/O pads 14. Seven of the I/O pads 14, designated DI, A, B, C, D E, and DO, are connected to clock control circuitry 18 which form part of the test circuitry used to test the internal circuit 12.

A shift register 20 including a plurality of individual latches is formed around the perimeter of the chip 10 adjacent th I/O pads 14. A single bit shift register or latch is connected t each pad 14, with the exception of dedicated pads utilized for ground or power supply connections (not shown) and the test pads. Test signals are provided at the input pad DI and are serially shifted into the latches until all of them are loaded. The loading is controlled by the control circuit 18. After all of th latches have been loaded, the test signals are transferred to the internal circuit 12 via the I/O drivers 16. upon receipt of the test signals, the internal circuit 12 generates output signals, the values of which indicate whether or not the circuit is operating properly. These output signals are transferred back into the latches through the I/O drivers 16. The contents of the latches are then serially shifted out of the chip at the DO, or data out, pad. These operations are all controlled by means of the control circuitry 18.

The chip 10 is typically formed by utilizing photolithographic techniques in which a number of aasking operations are performed to fora a plurality of transistor cells. In the present embodiment, the internal circuit 12 is derived fro blocks composed of four CMOS transistor pairs. The blocks are formed by a step and repeat operation so as to result in a regular array. In the present embodiment, the internal circuit includes 25 columns and 80 rows of blocks. Final steps in the foraation o the chip include the laying down of metallization patterns which interconnect the individual transistors so as to determine the function of each block. The functions of chips are thus customized by means of the metallization layers. The circuit functions which may be obtained vary from a simple inverter to complex latches or flip flops (which require interconnection of several blocks) .

The completed internal circuit is comprised of a number of registers and a large amount of combinatorial logic. In order to test the chip, the registers must all be preloaded to desired values. This may be accomplished by cycling signals from the input pads through the internal circuitry until the registers are loaded with the appropriate value. However, this may require the circuit to go through an excessively large number of cycles, thereby resulting in an unreasonably long test time. In order to avoid this problem, the internal circuit is designed so that all the registers may be serially connected and loaded directly, thus eliminating the need to cycle signals through the combinatorial logic. Such a structure is well known in the art and need not be described in detail here. After the registers have been loaded, the circuit is switched to connect the internal circuit so that it is in a normal run mode. Testing of the circuitry may then be initiated. In the present embodiment of the invention, both the internal registers and the external register 20 are loaded through the DI pad, with the control circuit 18 determining whether input signals at the DI pad are directed to the external shift register 20 or to the internal registers.

Referring now to FIGURE 2, the corner of the chip 10 containing the I/O pads used in conjunction with the test circuit is shown. Input signals from the DI pad and the clock pads A-E are applied to input buffers 22, which supply normal and inverted signals. One of the data in signals is connected to a first latch 20a and the clock signals are in turn coupled to clock driver circuitry 24 which provides clocking signals to control the operation of the testing circuitry. Output signals from the last latch 20b are applied to a data out circuit 26, which in turn supplies output signals to an output buffer 28 connected to the data out pad DO.

Referring now to FIGURES 3 and 4, the shift register and I/O driver circuitry for an individual pad is shown. FIGURE 3 shows driver circuitry which is utilised when a pad is employed as an input pad and FIGURE 4 shows driver circuitry utilized when >*_*» & l is employed as an output pad. In the present embodiment of the invention, the pads function either as input or output pads, although in certain instances a pad aay operate as both an input and output pad. The input driver circuitry includes an input buffer comprised of inverters 30 and 32, an input resistor 34 and diodes 36 and 38 which serve to protect against static discharge while handling the chip. The input circuit provides complementary outputs I and ϊ which are delivered to the internal circuit. The output driver circuitry includes inverters 40 and 42 which receive output signals from the internal circuit 12 and operate as an output buffer.

The latches utilized in the present embodiment of the invention are master-slave or A-B type latches. Each latch includes four inverters 44-50 and six transmission gates T1-T6. The operation of the master-slave latch is such that data will be entered into the A latch on a first clock pulse and transferred to the B latch on a second clock pulse, thus insuring that a data pulse does not mistakenly pass through a latch and to one or more subsequent latches on the same clock pulse. A first clock pulse causes data to be loaded into the A latch and a second, independent clock pulse causes data to be transferred from the A latch to the B latch. The use of an A-B lath and independent clock pulses reduces precision requirements with respect to the clock (i.e. rise time and pulse shape need not be tightly controlled) while maintaining precise shift register operation.

Referring now to FIGURE 5, the test circuitry input pads A-E and DI are each connected to an input buffer IB which provides complementary output signals. As shown in FIGURE 6, the input buffers include inverters 52 and 54, resistor 56 and protection diodes 58 and 60. The outputs of the buffers are utilized by the clock circuitry 24 to generate internal clock signals AΪ, BΪ and CX which are used to control the operation of the internal circuit 12 and external clock signals AB, AS, BE, BE, CE, CE, DE, DE and CS. The clock circuitry (FIGURE 7) includes HAND gates

OMPI 62-84 and inverters 86-108. In the present embodiment of the invention, the HAND gates are all formed in the regular array of the internal circuit 12. FIGURES 3 and 4 indicate which clock signals are used to control the transmission gates T1-T6. The transmission gates T1-T4 are clocked the same whether or not a latch is connected to an input driver or output driver. The gates T5 and T6, however, are driven differently depending upon whether the shift register is connected to an input driver or output driver.

Initially, test signals are loaded into the latches by controlling gates T1-T4 by means of clock signals A and B. During this time, the gate T5 is on. The control signals for this shifting operation are shown in FIGURE 8A. After the test signals have been loaded into all of the latches, the E clock signal is switched and test signals are loaded into the internal registers (shown in FIGURE 8B) • Susequently, the D clock signal is used to transfer the test signals from the latches to the internal circuit 12 via the input buffers to initiate a test. If a latch is connected to an input driver circuit (FIGURE 3} , the gate T5 will remain on and gate T6 will be turned _on thereby enabling test data to be transferred from latch 20c to the internal circuit 12 via the input buffer. If a latch is connected to an output buffer (FIGURE 4) then the gate T5 will be closed and T6 and Tl opened, thereby enabling the latch 20d to receive and store an output signal from the internal circuitry 12 via the output buffer. This operation is controlled by the signals CE and AE, as shown in FIGURE 8C. After the output signals from the internal circuitry 12 have been latched into the shift registers, the circuit can be put back into the shift mode (FIGURE 8A) to serially transfer the signals out of the chip through the DO pad. The output signals can then be compared with the desired output signals to deteraine if the circuit is properly operating.

Thus, the control of the testing of the integrated circuit 10 is shown in FIGURE 8. FIGURE 8A shows the- timing signals used to shift test signals through the external

OM shift register 20, while FIGURE 6B shows the timing signals used to shift data through the internal shift register_* To initiate the testing operation, test patterns are intially shifted into the external shift register 20 by the application of control signals shown in FIGURE 8A. Additional test signals are then shifted into the internal shift register by applying the clock signals shown in FIGURE 8B (clock signal E is shifted from 1 to 0) . An actual test is intiated by applying the signals shown in FIGURE 8C, which causes the signals in the external shift register to be applied to the combinatorial logic in the internal circuit 12. The output signals generated in response to the application of the test signals will appear almost immediately at the outputs of the internal circuits and will be loaded into the external shift register 20. The shift signals of FIGURE 8A are then reapplied to shift the results out of the external shift register. The shifted signals are transferred to the data output pad DO through the data output circuit 26 which is shown in greater detail in FIGURE 9. The signal DOE is the output of the last latch (20b in FIGURE 2) of the external shift register 20, and the signal DOI is the output of the last latch of the internal shift register in the internal circuit 12. These singals are applied to NAND gates 110 and 112, with the signal E determining which output is applied to a NOR gate 114. (The contents of the internal registers will be serially shifted out through the DO pad when new test signals are entered.) The output of the NOR gate 114 is connected to an inverter 116, which is in turn connected to the output buffer 28.

In the present embodiment, all of the circuitry on the chip 10 is comprised of CMOS devices. These devices have the characteristic that they consume little or no DC power. Therefore, the test circuitry can be left on the chip and packaged with the internal circuit without increasing power dissipation of the device. After the packaging, the test circuitry can be utilized to provide a functional test and a wiring check, i.e., to determine whether the connections between chips are faulty. This is accomplished simply by loading the values present at the I/O pads of a chip into the external shift register 20 and shifting the contents out of the chip. The contents can then be compared to then known value of the output from other chips- which are connected to corresponding I/O pads of the chip under test.

As previously mentioned, the chip 10 includes a number of dedicated ground and power supply pads. These pads do not require latches to be associated with them in order to test the internal circuit. However, latches are included which correspond to these pads and may be used to store information representing a part number for each chip. Each latch input adjacent to each ground and power supply pad can be selectively connected to either ground or voltage. In order to determine the part number, the voltage applied to the sampling wires are strobed into the latches. These values are then shifted out and the binary combination from the pads rep¬ resents the part number of the chip. This test may be accom¬ plished after the chip has been assembled onto a PC board, thereby enabling a tester to determine if the proper chip has been installed without having to look at the chip (which may be in an inaccessible location) .

In the present embodiment of the invention, the internal circuit 12 is fabricated from a regular array of transistors as previously described. The I/O drivers 16 and latches 20 could also be fabricated from this regular array. However, this would result in a relatively inefficient packaging arrangement. Since it is known that the external test circuitry will always be com¬ prised of latches, this circuitry is specifically configured so as to achieve maximum packing density. That is, the latches can be made more dense by specially designing their physical layout rather than employing the regular array to fabricate them. Similarly, the I/O drivers 16 may utilize a custom design apart from the regular array. This design may, however, be customized to operate in several different ways, i.e., as an input driver, output driver, ground connection or the like.

_OM As is the case with the regular array such customization would be accomplished by utilizing a specific metallization pattern to interconnect transistors of a regular array.

In summary, the present invention provides a VLSI chip which includes integral test circuitry which is designed to remain a permanent part of the chip. The test circuitry includes a shift register which surrounds the internal chip circuit and control circuitry for controlling testing operations. The provision of the test circuitry greatly reduces the number of pins which must be contacted in order to test the integrated circuit test. The pads which must be contacted may all be located on a single side of the chip, thereby simplifying the connection of a test probe. The test circuit may remain with the chip and be used to test wiring connections between chips. In addition, the test circuitry may be used to store a binary part number for each chip.

OMPI

Claims

I CLAIMS

1. An integrated circuit including integral test circuitry, comprising: an integrated circuit chip including an internal circuit; a plurality of input/output pads located near the periphery of the chip for providing input and output connections to the internal circuit; a shift register circuit formed on the chip for storing test signals; and a control circuit for a) serially entering test signals into the shift register, b) transferring the test signals into the internal circuit to thereby test the chip, c) transferring output signals from the internal circuit to the shift register circuit, and d) serially shifting the stored output signals out of the shift register circuit, whereby the number of external connections to the integrated circuit needed to test the chip is ainimized.

2. The integrated circuit of claim 1 wherein the shift register circuit is formed on the periphery of the chip adjacent the pads.

3. The integrated circuit of claim 2 wherein the shift register circuit comprises a plurality of latches, each latch being located near a pad.

4. The integrated circuit of claim 3 including input/output circuitry formed on the chip near the pads, wherein transfer of signals from the latches and pads to and from the internal circuit is accomplished via the input/output circuitry.

5. The integrated circuit of claim 4 wherein: the internal circuit is comprised of a plurality of transistor blocks arranged in a regular array and one or more metallization layers which interconnect the blocks in a specific configuration to determine the operation of the internal circuit; and the latches include components which are specifically configured to operate in a latch, thereby enabling the packing density of the latches to be aaxiaized.

OMPI

6. The integrated circuit of claim 5 wherein the input/output circuitry includes components which are specifica configured to operate in the input/output circuitry, thereby enabling the packing density of the input/output circuitry to maximized.

7. The integrated circuit of claim 1 wherein the interna circuit includes a plurality of data registers and the control circuit includes means for serially entering additional test signals into the data registers to thereby preload the data registers prior to a test.

8. The integrated circuit of claims 1 or 7 including a d input pad which is used to enter all of the test signals.

9. The integrated circuit of claim 8 including a data ou pad through which all of the stored output signals are shifted after a test has been performed.

10. The integrated circuit of claim 3 wherein each of the latches is a master-slave latch.

11. The integrated circuit of claims 3 or 10 wherein the control circuit includes: a plurality of switching circuits for controlling the connection of the latches to each other and to the internal circuit; and clock driver circuitry for controlling the operation of th switching, circuits.

12. The integrated circuit of claims 1 or 5 wherein the shift register circuit and control circuit are formed of CMOS devices, whereby when the shift register circuit is not being utilized power dissipation of the integrated circuit is ainimiz

13. The integrated circuit of claim 12 wherein the intern circuit is also formed of CMOS devices.

14. An integrated circuit including integral test circuitry, comprising: an integrated circuit chip including an internal circuit which is formed of a regular array of devices which are interconnected in a specific fashion to provide desired circuit operation; a plurality of input/output pads located on the perimeter of the chip; a plurality of input/output driver circuits formed in the chip near the pads, said driver circuits for transferring signals between the pads and the internal circuit; a plurality of serially connected latches formed in the chip near the pads, wherein each latch is connected to a driver circui and pad; and clock control circuitry for a) serially shifting test signal from an input pad through the latches to thereby load the latches b) transferring the signals from the latches into the internal circuit through the driver circuits to thereby test the chip, c) transferring output signals generated by the internal circuit bac to the latches through the driver circuits, and d) serially shifting the contents of the latches to an output pad, whereby th number of connections to the integrated circuit required for testing is minimized.

15. The integrated circuit of claim 14 wherein the integrated circuit is formed of CMOS devices, whereby power dissipation resulting from the inclusion of test circuitry on the chip is minimized.

16. The integrated circuit of claims 14 or 15 wherein the latches are formed of devices specifically configured to operate in a latch rather than being formed from a regular array of devices, thereby facilitating the formation of latches having aaxiaua packing density.

OMPI

17. The integrated circuit of claim 14 including means for storing a part number in each chip.

18. The integrated circuit of claim 17 including a second plurality of input/output pads used for power supply or ground connections, wherein the means for storing includes a plurality of additional latches connected to the second plurality of pads and serially connected to the other latches, wherein each of the second plurality of pads is selectively connectable to a power supply, whereby to determine the part number of a chip the second plurality of pads is connected to the power supply and the signals at the pads are entered into the additional latches and serially shifted through all of the latches to provide an output signal indicative of the part number of the chip.

19. The integrated circuit of claim 14 wherein the latches and clock control circuitry from a permanent part of the integrated circuit, thereby facilitating testing after the integrated circuit has been connected as part of a larger circuit.

20. A circuit comprising a plurality of interconnected integrated circuits as claimed in claim 1, whereby the shift register and control circuits can be used to test interconnections between the chips and function of the " interconnected chips.