WO1984003811A1

WO1984003811A1 - Compatible descrambler for television synchronization

Info

Publication number: WO1984003811A1
Application number: PCT/US1984/000402
Authority: WO
Inventors: Dennis W Deridder; Donald J Miller
Original assignee: Dennis W Deridder; Donald J Miller
Priority date: 1983-03-16
Filing date: 1984-03-16
Publication date: 1984-09-27

Abstract

A descrambling circuit for video signals which have been rendered secure against unauthorized use by suppression or elimination of the horizontal sync signals generates (29) a decoding signal at the receiving end by detection (18, 20) of an unmodified portion of the video signal occurring during the vertical blanking interval or by detection (40) of the 3.58 MHz color burst signal. In this way, descrambling can be accomplished without need for reference to a decoding signal with the scrambled video or a key inserted in the video signal at the transmission end. This also permits a single descrambling circuit to decode video signals which have been scrambled by different techniques.

Description

COMPAΗBLE DESCRAMBLER FOR TELEVISION SYNCHRONIZATION

Field of the Invention

The present invention relates in general to subscription television systems, and more particularly, to a method and apparatus for descrambling television signals which have been scrambled prior to transmission to prevent unauthorized reception and use by nonsubscribers. Background of the Invention

The need to provide security to prevent the unauthorized reception of television signals in cable and other types of subscription television systems has been recognized from the early days of television. Such security has been provided by various techniques for scrambling the transmitted television signal so that it produces at the receiving end an unrecog¬ nizable picture unless suitably descrambled in accordance with the selected scrambling technique.

By and large, the most common scrambling technique actually employed in practice, in spite of the many different and often complicated techniques proposed, is simply to suppress all or a substantial number of the horizontal sync pulses in each video frame, which are required to provide synchronization in the television receiver between the raster scan and the received video information. The result of this horizontal sync pulse suppression is a television picture in which the horizontal lines are no longer aligned with each other or properly located in the raster scan due to the receiver locking in on random peaks in the video portion of the signal in the absence of the horizontal sync pulses. This produces a totally unrecognizable picture to the unauthorized viewer.

In addition to horizontal sync signal suppression, a number of proposals for scrambling video signals involve the inversion of ^"video in selected horizontal lines, which also produces an unrecognizable picture in the absence of required descrambling at the receiving end. A combination of sync signal suppression and video inversion, along with other scrambling techniques, has also been proposed; however, a major disadvantage of all of these prior systems is that they require transmission of a decoding or descrambling signal which makes it possible at the receiver end for an authorized subscriber to decode the received video.

In the system disclosed in the Court U.S. Patent No. 3,729,576, an encoding process is employed in which the video is modulated with a sine wave having a phase and frequency selected so as to depress the synchronizing pulses and blanking information, while enhancing the video signal inbetween. This has the effect of drastically altering the normal amplitude relationship between the sync and video intelligence, so that amplitude separation of the sync by the television receiver is no longer possible. For decoding purposes, a decoding sine wave having the same frequency but opposite phase to the encoding sine wave modulation is superimposed on the audio carrier at the transmitting end, and the encoded signal at the receiving end is then modulated with this decoding signal to eliminate the scrambling. This same technique is utilized in the system disclosed in the Loughlin et al U.S. Patent No. 3,081,376. Other systems employ a separate communications channel, such as an out of band carrier or telephone line, to transmit the descrambling signal to the receiving end; however, such an arrangement clearly is undesirable since it requires a separate signal path for the decoding signal.

A further disadvantage of those systems which require the transmission of a decoding or descrambling signal on the audio carrier relates to the incompatibility of such a system with the soon-to-be-introduced stereo audio requirement for television transmission, which prohibits incorporation of scrambling information on the audio carrier. In this regard, when stereo is provided in the audio channel, the increase FM signal deviation thereon will tend to correct the decode intelligence through FM to AM conversion which will be inherent, to a certain extent, in the headend processing. In those systems where a descrambling sine wave, for example, is received on the audio carrier for decoding purposes, the descrarabler will utilize any audio modulation received in the audio channel, with the result that the incidental amplitude modulation generated as a result of the stereo in the audio channel will produce a bogus decode waveform component capable of causing an annoying pattern in the reproduced television picture.

In the system disclosed in the Thompson U.S. Patent No. 4,222,068, both horizontal sync signal suppression and randomly-inverted video coding is employed to provide a scrambling of the video signal, and decoding of the scrambled video is effected at the receiving end without the need for complex encoding signals superimposed on or transmitted with the encoded video. However, this system does require a modification of the video signal to place decoding information in the vertical blanking interval in the form of an inversion of the polarity of a line trace portion thereof. By detecting the inverted polarity of the line trace portion of the vertical blanking interval, it can be determined that the polarity of the video in the following field should be reinverted to descramble the signal. Reinsertion of the suppressed horizontal sync signals is achieved by detecting that the amplitude of the scrambled video signal during the initial portion of each horizontal blanking period is below a predetermined level. As can be seen, this scheme, while avoiding the need to superimpose a decoding signal on the audio channel, requires incorporation of decoding information into the vertical blanking interval to control the descrambling operation. In addition, it is a requirement of this system that normal horizontal sync signals be transmitted periodically, for example, every sixty frames, which is clearly undesirable.

Thus, while various schemes have been utilized^' in the prior art based on horizontal sync signal suppression for scrambling a video signal, no one technique for transmission of a descrambling signal or incorporation of decoding information into the scrambled video has been universally adopted. As a result, for the manufacturer of video converters, it is necessary to provide a variety, of products compatible with all of the various systems then in use. The economic disadvantage of such a constraint on manufacturing is apparent, not to mention the cost and complexity of the descrambling circuits required for some of the more involved schemes of descrambling encoded video signals.

It is therefore an object of the present invention to provide a descrambling circuit for subscription television systems, such as cable and satellite systems, in which the foregoing disadvantages of the prior art are entirely avoided.

It is another object of the present invention to provide a descrambling circuit of the type described which is compatible with a plurality of horizontal sync suppression scrambling systems using different schemes for descrambling of the received video signal. -fr¬

it is still another object of the present invention to provide a descrambling circuit of the type described which is capable of descrambling a television signal subjected to horizontal sync signal suppression without the need for a decoding signal to be transmitted with the scrambled video or for modification of the transmitted video signal to incorporate decoding information.

It is a further object of the present invention to provide a descrambling circuit of the type described which is not only of simple construction, but may be manufactured as a universal unit compatible with a plurality of different video transmission systems.

It is still a further object of the present invention to provide a descrambling circuit of the type described which provides for increased security in the transmission of video signals by permitting false decoding information to be incorporated into the video signal transmission without materially complicating the authorized decoding of these scrambled communications.

These and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the illustration of various exemplary embodiments as provided in the accompanying drawings. Summary of the Invention

The present invention is based upon the fact that, in virtually all scrambling techniques for video signals, the vertical blanking interval portion of the video signal is not in any way disturbed to the extent that the vertical or horizontal sync pulses therein are indistinguishable. That vertical blanking interval portion of the video signal includes a first equalizing pulse interval followed by a vertical sync ^• pulse interval, which is in turn followed by a second equalizing pulse interval. Since the vertical sync pulses will be consistently produced in every scrambled video signal and can be easily detected, it is "possible to generate the necessary horizontal sync pulses with correct timing by providing a crystal oscillator running at a frequency which is an integral number N times the horizontal line rate and by applying this high frequency signal to a divide by N counter which is reset at the frequency of the detected vertical sync, thereby to provide the necessary horizontal sync pulses to be used for decoding of the received scrambled video.

In accordance with another embodiment of the present invention, further use is made of the presence of horizontal sync pulses following the second equalization pulse interval in the vertical blanking interval. These twelve horizontal sync pulses which comprise the last portion of the vertical blanking interval represent the twelve blanked lines at the top of the raster at the start of the vertical trace downward. Even in a scrambled video signal, these twelve horizontal sync pulses are always available, are of the correct horizontal frequency and phase and are easily detectable, and therefore, these pulses can be applied to a circuit which locks onto the horizontal line frequency to produce the required horizontal sync pulses during the following frame for reinsertion into the blanking interval for each horizontal line of the frame. In the alternative, these pulses can be applied to reset a divide by N counter which is driven by a crystal oscillator to produce the desired decoding signal.

For scrambling systems utilizing sine wave suppression techniques, such as disclosed in the aforementioned Court et al patent, the pulses generated as a result of phase locking onto the horizontal sync pulses in the vertical blanking interval may be shaped to produce a descrambling sine wave waveform, which then may be multiplied back into the video with the proper out-of-phase relationship necessary to reproduce the descrambled video.

A further embodiment of the present invention makes use of another characteristic of a video signal which goes unchanged in all descrambling operations. As is known, the composite video signal includes a 3.58 MHz chrominance signal in the form of a color sync burst which is carried on the back porch of the horizontal blanking interval. Even in systems where encoding

OMPI of the video signal includes a suppression of the horizontal sync pulse during the horizontal blanking interval, the 3.58 MHz color subcarrier is never eliminated. Accordingly, it is possible to detect the color sync burst and lock onto it for purposes of regenerating the horizontal sync pulses which have been suppressed during the scrambling of the video signal prior to transmission.

In its most basic form, the present invention provides a ^■ circuit for extracting from a scrambled video signal information provided in the vertical interval or the 3.58 MHz color sync burst to produce a decoding signal which may be used as the basis for descrambling the received signal without regard to how it has been scrambled at the transmission end and without need for descrambling information to be transmitted with the signal apart from the video information typically provided. Such a circuit can be used to provide precise timing where the video has to be reinverted, when the scrambling includes inversion of horizontal lines of video. It can also be adapted for use as a horizontal sync sampler to determine if horizontal sync is present at a particular location in the video signal. Thus, the invention forms the heart of a universal descrambler for video signals. Brief Description of the Drawings

Figure 1 is a diagram of the portion of a composite television signal including the vertical blanking interval;

OMPI Figure 2 is a schematic block diagram of a descrambling circuit which forms one embodiment of the present invention;

Figures 3 and 4 are schematic block diagrams of respective modifications of the embodiment of Figure 2;

Figure 5 is a schematic circuit diagram of the horizontal sample generator 24 of Figure 4;

Figure 6 is a schematic circuit diagram of the square wave generator 65 of Figure 4;

Figure 7 is a schematic block diagram of a descrambling circuit which forms another embodiment of the present invention;

Figure 8 is a schematic block diagram of a modification of the descrambling circuit of Figure 7;

Figure 9 is a diagram of the portion of the composite television signal forming the horizontal blanking interval; and

Figure 10 is a schematic block diagram of a descrambling circuit forming a further embodiment of the present invention. Detailed Description of the Preferred Embodiments

The composite television signal includes as its basic parts a video signal portion corresponding to the desired picture information, synchronizing pulses to synchronize the transmitter and receiver scanning, and blanking pulses to make the retraces invisible. Thus, between each horizontal line traced, there is provided a horizontal blanking interval during which the video signal is brought up to the black level

OώH providing a pedestal on which the horizontal sync pulse is placed; and, between each frame, there is provided a vertical blanking interval during which the video signal amplitude is raised to the black level so that the scanning beam is blanked out during vertical retraces.

Figure 1 shows the details of a vertical blanking interval in a standard NTSC system. Starting at the left in the figure, the last four horizontal scanning lines at the bottom of the picture are shown with the required horizontal blanking and sync pulses. Immediately following the last visible horizontal line, the video signal is brought up to black level by the vertical blanking pulse in preparation for vertical retrace. The vertical blanking period begins with a group of six equalizing pulses, which are spaced at half-line intervals. Next is the serrated vertical sync pulse that actually produces vertical flyback in the scanning circuits. The serrations also occur at half-line intervals; therefore, the complete vertical sync pulse is three horizontal lines wide. Following the vertical sync pulse is another group of six equalizing pulses and a train of horizontal sync pulses. The serrated vertical sync pulse signals the start of the vertical retrace period; however, vertical flyback typically does not start until the leading edge of the third serration, so that the time of one horizontal line passes during vertical sync before vertical flyback starts. Since the six equalizing pulses preceding the

PI serrated vertical sync pulse are equal to three horizontal lines, four complete horizontal lines are blanked at the bottom of the picture. Thus, the start of vertical flyback is in synchronism with the occurrence of the horizontal sync pulses in the video signal and can be used to trigger the generation of horizontal sync pulses for decoding a video signal which has been subjected to sync signal suppression or elimination.

^• A typical vertical retrace time is five complete horizontal lines from the time vertical flyback begins. Thus, with four lines blanked at the bottom of the frame before flyback begins and five lines blanked during flyback, twelve lines remain of the total twenty-one horizontal lines which comprise the vertical blanking interval. Therefore, there will be in a typical case twelve horizontal sync pulses following the last equalizing pulse interval, which also can be used for the generation of horizontal sync pulses for decoding a video signal which has been subjected to sync signal suppression or elimination.

Before provision of a detailed description of the various preferred embodiments, which are based on the foregoing principles, it should be noted that the present invention assumes that the vertical interval of the video signal will remain untouched in any scrambling or coding technique utilized for security purposes, that is, that no extraneous pulses or pulse distortion has taken place to the point of rendering the

OMPI vertical sync pulses indistinguishable. Thus, in its most basic form, the invention uses only unmodified portions of the scrambled video for the decoding thereof, thereby obviating any need to transmit with the scrambled video or send by separate means a decoding signal to aid in the decoding process at the receiving end, or any need to modify the vertical interval at the transmission end to provide a key in the transmitted -signal for this same purpose.

Figure 2 shows one embodiment of' the present invention in which decoding of the scrambled video is based upon vertical sync detection. In this embodiment, an analog multiplier 10 receives on line 12 the scrambled video which has been subjected to some form of horizontal sync signal suppression and a decoding signal on line 14. The analog multiplier 10 multiplies the components of these two signals to produce a descrambled video signal on line 16.

For purposes of generating the required descrambling signal, a crystal oscillator 15 is provided which produces , output pulses at a frequency, for example, 8.5 MHz, which is an integral number N times the horizontal sync pulse frequency of the video signal, and the output of the crystal oscillator 15 is applied to a divide by N counter 22. The scrambled video received on line 12 is then applied to a vertical sync detector 20, of the type typically provided in a standard television set, so that an output pulse will be provided upon detection of the serrated vertical sync signal. This output pulses of the detector 20 is used to reset the counter 22, thereby synchronizing the counter 22 at the end of each frame of video. Thus, the output of counter 22 will be at the horizontal line rate and will be synchronized with the horizontal blanking intervals of the video signal.

The pulse output signal from counter 22 is filtered in a horizontal line rate filter 26 and applied to a wave shaper 27 to produce a signal which corresponds to the coding signal employed in the scrambling of the video at the transmission end. In this regard, if the coding technique involves sine wave sync signal suppression, the wave shaper 27 will respond to the output from the horizontal line rate filter 26 to produce a sine wave which is adjusted in the phase control 28 and amplitude control 29 to provide a descrambling signal which is the complement of the scrambling signal. If the transmitted video has been subjected to square wave sync signal suppres¬ sion, the sine wave is selectively applied through a slicer 32, which converts the sine wave to a square wave descrambling signal. In this regard, it is apparent that the slicer 32 may be optionally switched in and out of the circuit for selecting either sine wave or square wave sync signal descrambling.

In the descrambling of the received video, it is important to avoid any disturbance of the vertical interval which might result in sufficient distortion of the signal to cause picture roll and other irregularities. Accordingly, a vertical interval switch 30 is provided for preventing application of the descrambling signal to the analog multiplier 10 during the vertical blanking interval of the received video. For this purpose, the vertical interval switch is controlled by the output of a vertical interval detector 21 which is responsive to the pulse output of the vertical sync detector 20. The vertical interval detector 21 produces a gating pulse which corresponds to the vertical interval and applies this gating pulse to the vertical interval switch 30 so as to open the switch to prevent the descrambling signal from being applied on line 14 to the analog multiplier 10 during the vertical blanking interval.

In the embodiment of Figure 2 , it can be seen that a descrambling signal is generated solely in response to detection of the vertical sync signal using a standard vertical sync detector in combination with a crystal oscillator and a counter. Thus, the descrambling circuit in accordance with the present invention requires no decoding signal to be transmitted with the video or by separate means or a key to be provided in the transmitted video signal for controlling the descrambling operation. Descrambling is therefore accomplished in a very reliable and simple manner using basic components.

A variation of the embodiment of Figure 2 is illustrated in Figure 3, in which corresponding elements are identified by the same reference numerals. Like the embodiment of Figure 2, the descrambling signal is generated at the output of a divide by N counter 22 driven by a crystal oscillator 15, whose output frequency is an integral number N times the horizontal sync pulse frequency of the video signal. However, in this embodiment, the counter 22 is synchronized by the twelve horizontal sync pulses which appear at the end of the vertical interval.

As seen in Figure 3, the output of the vertical sync detector 20 is applied not only to the vertical interval detector 21 for controlling the vertical interval switch 30, as already described, but is also applied to a one-shot multivibrator 23 to generate a gating pulse having a timing and a width corresponding to the trailing portion of the vertical blanking interval containing the twelve horizontal sync pulses. The gating pulse at the output of one-shot 23 is applied to a gate 17, which then opens to allow the twelve horizontal sync pulses detected by horizontal sync detector 18 to pass to the reset input of divide by N counter 22.

Thus, unlike the embodiment of Figure 2 in which the counter 22 is reset by the vertical sync pulse itself, in the embodiment of Figure 3, the counter 22 is synchronized more accurately by the twelve horizontal sync pulses which appear in the vertical interval. By this means any loss of accuracy in the synchronization resulting from the fact that the vertical sync signal varies by half a line in alternate fields is eliminated.

The remaining elements in the circuit of Figure 3 operate in the same manner as already described to apply a descrambling signal to the analog multiplier 10 in response to the output of the counter 22. However, in either embodiment it will be apparent that the elements 26-29 need not necessarily be connected in the sequence illustrated in the drawings to achieve the desired operating results.

Another variation of the embodiment of Figure 2 is illustrated in Figure 4, in which corresponding elements are identified by the same reference numerals. In this variation, the synchronization of the divide by N counter 22 is effected by a single selected one of the twelve horizontal sync pulses included in the trailing portion of the vertical interval, and the detection of this selected pulse is effected digitally in accordance with this invention. In addition, the slicer 32, which is provided in other embodiments for descrambling of video signals subjected to square wave sync signal suppression, is replaced in this embodiment by a more accurate digital circuit.

As seen in Figure 4, the divide by N counter 22 is again reset by the output of gate 17, which has one input connected to horizontal sync detector 18 connected to receive the scrambled video. In this embodiment, unlike the embodiment of Figure 3, the gate 17 is controlled by a horizontal sample generator 24, which operates to generate a sample pulse during the vertical interval of the video signal with a tuning which permits only a single selected horizontal sync pulse at the output of detector 18 to pass through gate 17 to reset the counter 22. This single selected horizontal sync pulse may be any one of the twelve sync pulses which appear at the trailing portion of the vertical interval, but is preferably not the first or second of these pulses, so as to avoid the possibility of the circuit responding to a noise pulse or an equalizing pulse.

The horizontal sample generator 24 is a digital circuit which is reset by the vertical sync pulse at the output of detector 20, and then proceeds to count a predetermined number of horizontal sync pulses ^"(preferably the first two) produced at the output of the detector 18. Upon detecting this predetermined count, a sample pulse is supplied to gate 17 to allow the next horizontal sync pulse to pass to the reset input of counter 22, effecting the required synchronizing resetting of this counter in accordance with the basic feature of the present invention. In addition, this pulse output from gate 17 is also applied back to the horizontal sample generator 24 to effect removal of the sample pulse output to gate 17, so that no further horizontal sync pulses are permitted to pass during that field of the video signal. An example of the horizontal sample generator 24 is shown in Figure 5. This circuit essentially consists of a horizontal sync pulse counter 50 and a timing control counter 64. The counter 50 is connected to receive the output pulses of the horizontal sync detector 18 and to produce a sample pulse to enable gate 17 upon reaching a predetermined count. In accordance with this embodiment, any one of the twelve horizontal sync pulses which are present in the vertical interval may be used to generate the sample pulse; however, it is desirable to ignore the first few of these pulses to avoid improper synchronization on an equalizing pulse or other pulse preceding the twelve horizontal sync pulses. For this purpose the counter 50 may produce its output upon reaching a maximum count of two, for example, thus ignoring the first two pulses appearing at the output of the horizontal sync pulse detector 18.

The counter 64 and its associated circuit elements operate to control the timing of the horizontal sample generator 24 so . that it operates during the vertical interval and only in response to the twelve horizontal sync pulses therein. For this purpose, the counter 64 is reset by the output of the vertical sync detector 20 via OR gate 56 upon detection of the vertical sync pulse in each field of the video signal. This counter 64 is a divide by 525 counter which is driven from the 2H output of the counter 22 so as to count at the line rate in each field. When the counter 64 reaches a count representing that point in the vertical interval at which the twelve horizontal sync pulses are to appear, an AND gate 52 will produce an output which acts to set a flip-flop 65. When the counter 64 reaches a count representing the end of the vertical interval, an AND gate 53 will produce an output which acts to reset the flip-flop 65. Thus, the flip-flop 65 will produce a gating pulse having a timing and a pulse width corresponding to the period of the vertical interval during which the twelve horizontal sync pulses appear. The AND gate 54 produces an output at the count of 525 to reset the counter 64 via OR gate 56.

The output of the flip-flop 65 is connected to one input of NAND gate 63, the other input of which is connected to the Q output of a flip-flop 51. The flip-flop 51 will be in a set state prior to the vertical interval as a result of operations during the previous field. Thus, prior to generation of the gating pulse by the flip-flop 65, the NAND gate 63 will maintain the counter 50 in a reset condition. Also, in the absence of the gating pulse from the flip-flop 65, the positive output of the inverter 62 will cause a transistor 61 to be conductive, thereby placing the input to the counter 50 at the ground level. Accordingly, the counter 50 will be inactive except during the vertical interval.

When the gating pulse is produced at the output of flip-flop 65, the transistor is rendered non-conductive and the flip-flop 51 is reset via the inverter 62. As a result, the output of NAND gate 63 goes low, removing the enforced reset state from the counter 50, enabling it to begin its count of horizontal sync pulses received from detector 18. After reaching a count of two, for example, the counter 50 produces a sample pulse output to AND gate 17, allowing the next horizontal sync pulse from detector 18 to pass to the reset' input of the divide by N counter 22. At the same time, this pulse at the output of AND gate 17 will also reset the flip-flop 51, causing the output of NAND gate 63 to go high. Counter 50 is again reset and maintained in that condition until the next field. If for some reason, after the AND gate 17 has been enabled from the output of counter 50, no horizontal sync pulses are provided to the gate 17 from the detector 18, the counter 50 will still be reset at the end of the vertical interval. This results from the fact that, even though the flip-flop 51 may remain reset, when the gating pulse from the output of flip-flop 65 disappears, the output from NAND gate 63 will go high resulting in resetting of the counter 50. At the same time, the output from inverter 62 will drive transistor 61 to conduction, clamping the input to counter 50 to ground. The fact that the flip-flop 51 remains reset during the next field of the video is of no consequence, since it will normally be reset in any event from the output of inverter 62 when the gating signal is produced by output 65 at that time. As can be seen from the foregoing description of the horizontal sample generator 24, a single horizontal sync pulse from the twelve pulses provided at the trailing portion of the vertical interval will be gated to reset the divide by N counter 22, thereby providing the synchronization of the counter 22 necessary to accurately produce a descrambling signal for decoding the received video. Where the scrambled video has been coded using sine wave sync signal suppression, the output of the counter 22 is applied through the horizontal line rate filter 26, wave shaper 27, phase control 28 and amplitude control 29 to produce the sine wave descrambling signal as already described in conjunction with the embodiments of Figures 2 and 3. However, where the scrambling has been accomplished using square wave sync signal suppression, a square wave generator 60 may be provided in place of the previously-proposed slicer 32.

An example of the square wave generator 60 is seen in Figure 6. In this circuit, a counter 66 is driven from an output of the divide by N counter 22 which represents a frequency of approximately one-half the frequency of the crystal oscillator 15. When the counter 66 reaches a first predetermined counter, AND gate 67 produces an output which acts to set a flip-flop 69. When the counter 66 reaches a second predetermined count, AND gate 68 produces an output which acts to reset the flip-flop 69. Thus, the Q output of flip-flop 69 represents a square wave whose width is determined by the difference between the first and second predetermined counts at clock frequency, and this square wave is applied through an amplitude adjuster 75 to the selector switch 90, by means of which it is possible to select between sine wave and square wave descrambling signals.

The synchronization of this square wave produced at the output of flip-flop 69 is effected by a digital phase shifter 71 and a further flip-flop 70. The flip-flop 70 is set in response to the Q output of flip-flop 69 going high and acts to reset the counter 66. The flip-flop 70, in turn, is reset from the output of digital phase shifter 71, which acts to phase shift the 2H signal received on line 73 from the counter 22 in accordance with the horizontal sync pulse produced on line 74 from the AND gate 17. In this way a square wave descrambling signal in synchronism with the selected horizontal sync pulse in the vertical interval is generated and applied to the analog multiplier 10 via the selector switch 90 and vertical interval switch 30.

The selector switch 90 could be provided as a manual switch for selection of sine wave or square wave descrambling. On the other hand, this switch 90 could be controlled by the microprocessor in the video converter on the basis of stored data for each incoming video channel indicating whether the particular video channel is scrambled by sine wave or square wave sync signal suppression. A further embodiment of the present invention, which is based upon the detection of the horizontal sync pulses which are present in the vertical blanking interval, is illustrated in Figure 7. In this embodiment, elements which correspond or are equivalent to elements in the embodiment of Figures 2 through 4 are identified by the same reference numeral in the drawing. Thus, the descrambling of the scrambled video received on line 12 is again accomplished using an analog multiplier 10 receiving a descrambling signal on line 14.

For purposes of generating the required descrambling signal, the scrambled video on line 12 is applied to a hor¬ izontal sync detector 18 and a vertical sync detector 20, both of which are of the type typically provided in a television receiver. The vertical sync detector 20 detects the receipt of the serrated vertical sync signal, producing an output pulse which triggers a vertical interval detector 21, causing a gating pulse to be applied to the horizontal sync detector 18. The gating pulse which is generated by the vertical interval detector 21 has a timing and a pulse width corresponding to the trailing portion of the vertical blanking interval containing the twelve horizontal sync pulses, so that the horizontal sync detector 18 will respond only to these horizontal sync pulses in the vertical blanking interval.

The phase locked loop 25 locks onto the horizontal sync pulses supplied to it from the horizontal sync detector 18 during the vertical blanking interval and freewheels through the following frame, producing a pulse signal at the horizontal line rate synchronized to the horizontal blanking intervals of the video signal. This output pulse signal is applied through the horizontal line rate filter 26, wave shaper 27, phase control 28 and amplitude control 29 to provide a sine wave descrambling signal, which may be converted to a square wave descrambling signal in the same manner described in connection with the embodiment of Figure 2. As in the previous embodiment, the vertical interval switch 30 is responsive to the output of the vertical interval detector 21 to prevent the descrambling signal from being supplied on line 14 to the analog multiplier 10 during the vertical interval.

It will be noted from Figure 7 that the output of the vertical interval detector 21 is also applied to the horizontal phase locked loop 25. In this regard, once the phase locked loop 25 has acquired and locked onto the horizontal sync pulses received from the detector 18, it is possible to switch to a lower time constant to reduce the noise susceptibility of the phase locked loop during the active video portion of the frame. Thus, the output of the vertical interval detector 21 provides a control input to the phase locked loop 25 which is used to identify the time during which horizontal sync pulses are supplied to the loop from the sync detector 18. During that time, the phase locked loop 25 will operate with a higher time constant to acquire and lock onto the horizontal sync pulses. In the absence of the control input from the vertical interval detector 21, the loop 25 will switch to the lower time constant.

It will be noted once again in connection with the embodiment of Figure 7. of the present invention that a decoding signal has been generated at the receiving end of the system by detecting an unmodified portion of the video signal occurring during the vertical blanking interval, namely, the twelve horizontal sync pulses which occur at that time. Thus, no descrambling signal or key need be provided with the scrambled video from the transmission end for decoding purposes, and the decoding is accomplished utilizing relatively simple and inexpensive circuits of the type typically used in video and various control systems.

Figure 8 illustrates an embodiment of the present inven¬ tion which represents a modification of the descrambling circuit of Figure 7. Again, the same reference numerals are used to identify common elements in the respective embodiments.

In Figure 8, the output of the horizontal sync detector 18 is applied to one input of an AND gate 36, which is enabled by the gating signal produced by the vertical interval detector 21 and applied through the inverter 37 to the other input thereof. Thus, the horizontal sync pulses which occur during the verti¬ cal blanking interval are applied from the output of AND gate 36 through OR gate 38 to the phase locked loop 25 in a manner similar to that described in connection with the embodiment of Figure 7. However, the descrambled video provided on the output line 16 from the analog multiplier 10 is^* supplied to a second horizontal sync detector 35, which detects the horizontal sync pulses in the descrambled video and applies these sync pulses to one input of an AND gate 39. The AND gate 39 is disabled during the vertical blanking interval by the output of the vertical interval detector 21, but will supply the horizontal sync pulses from the detector 35 through OR gate 38 to the phase locked loop 25 during the remaining portion of the frame. Thus, with this arrangement, the phase locked loop 25 need not freewheel through the frame after locking onto the horizontal sync pulses supplied from the detector 18 during the vertical blanking interval, but is positively controlled during the active video, thereby avoiding problems relating to frequency drift in the phase locked loop 25 during the frame.

In the foregoing embodiments, a descrambling signal has been generated by detecting unmodified portions of the video signal occurring during the vertical blanking interval. However, it is also possible to utilize other characteristics of the scrambled video signal, such as the 3.58 MHz color burst signal, to generate pulses at the line rate which may be used to produce the required descrambling signal. In this regard, as seen in Figure 9, the horizontal blanking interval comprises a blanking pulse serving as a pedestal on which the horizontal sync pulse is provided along with a burst of 3.58 MHz color subcarrier, which is used to synchronize the color oscillator in the television receiver. In sync signal suppression systems, the color burst signal is reduced in amplitude with the suppression of the horizontal blanking pulse; however, this color burst signal is never eliminated as part of the coding of the video signal. It is therefore possible to detect the color burst signal at the receiving end as an indication of the location of the horizontal blanking intervals. This is accomplished in accordance with the present invention by a descrambling circuit such as illustrated in Figure 10.

In the embodiment of Figure 10, those elements which are the same as or equivalent to the elements of the preceding embodiments are identified by the same reference numerals.

For purposes of generating the descrambling signal in this embodiment, the scrambled video signal received on line 12 is applied to a 3.58 MHz color burst detector 40, which produces an output pulse coincident with the horizontal blanking interval of the video signal based on the detection of this color burst signal. The output of detector 40 is supplied through a wave shaper 42 to the phase locked loop 25 which locks onto these pulses, producing a pulse output signal at the horizontal line rate and in synchronism with the horizontal blanking intervals. This pulse signal from the phase locked loop 25 is supplied through the horizontal line rate filter 25, the wave shaper 27, the phase control 28 and the amplitude control 29 to produce the sine wave descrambling signal in the same manner as the previously described embodiments. Again, the sine wave descrambling signal can be converted to a square wave signal by selection of the slicer 32.

It should be apparent that the various embodiments of the present invention represent simplified means for descrambling a video signal which has been secured against unauthorized reception and use by some form of sync signal suppression, and this decoding is accomplished without the need for transmission of a decoding signal or the modification of the video to pro¬ vide a key to aid in control of the decoding at the receiving end. An additional advantage is also derived from the fact that the decoding circuit of the present invention requires no keying or encoding signal to effect proper decoding of the scrambled signal. This advantage lies in the fact that additional security can be obtained by transmitting with the video or by some other means a false decoding signal which will operate to further scramble the video at the receiving end if used to control the decoding operation. Thus, anyone who is not authorized to receive and use the video transmission and who attempts to obtain such use through conventional decoding methods which rely upon receipt of a decoding signal can be more certainly prevented from such unauthorized use if a false decoding signal is transmitted. The authorized subscriber can still receive and decode the scrambled video using the descrambling circuit of the present invention, which does not rely upon receipt of a decoding or keying signal to control the descrambling operation.

While we have shown and described several embodiments in accordance with the present invention, it is understood that the invention is not limited to the details shown and described herein, but is intended to cover changes and modifications known to those of ordinary skill in the art, and we therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications obvious to those skilled in the art.

Claims

WHAT IS CLAIMED IS;

1. A descrambling circuit for descrambling a video signal which has been scrambled by horizontal sync signal suppression, comprising: first means for detecting an unmodified signal portion within the vertical blanking interval of said scrambled video signal; second means responsive to said first means for generating a decoding signal for descrambling said scrambled video signal; and analog multiplier means connected to said second means for multiplying said scrambled video signal and said decoding signal to produce a descrambled video signal.

2. A descrambling circuit according to claim 1, further comprising switch means connected between said second means and said analog multiplier means for preventing application of said decoding signal to said analog multiplier means during the vertical blanking interval of said video signal.

3. A descrambling circuit according to claim 1, wherein said first means comprises a vertical sync signal detector connected to receive said scrambled video signal, and said second means comprises a highly stable oscillator capable of generating an output signal at a frequency which is an integral number N times the horizontal line rate of said video signal and a divide by N counter connected to receive the output of said oscillator, said counter being connected to said vertical sync detector so as to be periodically reset thereby.

4. A descrambler circuit according to claim 3, wherein said second means further comprises wave shaping means connected to receive the output -of said counter for generating a sine wave decoding signal.

^'5. A descrambler circuit according to claim 3, wherein said second means further comprises wave shaping means connected to receive the output of said counter for generating a square wave decoding signal.

6. A descrambler circuit according to claim 1, wherein said second means comprises a phase locked loop connected to receive the output of said first means.

7. A descrambler circuit according to claim 1, wherein said first means comprises a vertical sync signal detector and a horizontal sync signal detector each connected to receive said scrambled video signal, and vertical interval detector means connected to said vertical sync signal detector for producing a gating pulse during said vertical blanking interval of said video signal and for gating said horizontal sync signal detector with said gating pulse so that it will be enabled to receive said horizontal sync pulses within said vertical blanking interval.

8. A descrambler circuit according to claim 7, wherein said second means comprises a phase locked loop connected to receive the output of said horizontal sync signal detector.

9. A descrambler circuit according to claim 8, wherein said second means further comprises wave shaping means connected to receive the output of said phase locked loop for generating a sine wave decoding signal.

10. A descrambler circuit according to claim 8, wherein said second means further comprises wave shaping means connected to receive the output of said phase locked loop for generating a square wave decoding signal.

11. A descrambler circuit according to claim 1, wherein said first means comprises first horizontal sync signal detector means for detecting the horizontal sync pulses which are present during the vertical blanking interval of said video signal, and said second means comprises a phase locked loop connected to receive horizontal sync pulses from said horizontal sync signal detector means.

12. A descrambler circuit according to claim 11, wherein said first means further includes second horizontal sync signal detector means connected to the output of said analog multiplier means for detecting the horizontal sync pulses in said descrambled video signal and gating means for connecting the output of said first horizontal sync signal detector means to said phase locked loop during the time of said vertical blanking interval and for connecting the output of said second horizontal sync signal detector means to said phase locked loop during the remaining portion of the video frame.

13. A descrambling circuit according to claim 1, wherein said second means comprises means including a highly stable oscillator for generating an output signal at a frequency which is an integral number N times the horizontal line rate of said video signal and a divide-by-N counter connected to receive the output of said oscillator, said divide-by-N counter being connected to said first means so as to be periodically reset by the horizontal sync pulse detected in the vertical blanking interval of said scrambled video signal.

14. A descrambling circuit according to claim 13, wherein said first means comprises a horizontal sync detector and a vertical sync detector each connected to receive said scrambled video signal, and gating means connected to said horizontal sync detector and said vertical sync detector for gating at least one horizontal sync pulse in said vertical blanking interval following receipt of a vertical sync pulse from said vertical sync detector, the output of said gating means being applied to reset said divide-by-N counter.

15. A descrambling circuit according to claim 14, wherein said gating means includes means responsive to said vertical sync detector for generating a gating pulse subsequent to detection of the vertical sync signal in said received video signal and a gate connected between said horizontal sync detector and the reset input of said divide-by-N counter and responsive to said gating pulse for passing at least one horizontal sync pulse which appears in said vertical blanking interval.

16. A descrambling circuit according to claim 15, wherein said gating pulse generating means comprises a one-shot multivibrator.

17. A descrambling circuit according to claim 16, wherein said gating pulse has a width sufficient to cause said gate to pass a plurality of horizontal sync pulses which appear in a single vertical blanking interval.

OMPI

18. A descrambling circuit according to claim 14, wherein said gating means includes horizontal sample generator means connected to said horizontal and vertical sync detectors for sampling a single horizontal sync pulse in said vertical blanking interval following detection of the vertical sync pulse in the received video signal.

19. A descrambling circuit according to claim 18, wherein said horizontal sample generator means includes means' for counting the horizontal sync pulses received following detection of said vertical sync pulse, and wherein said gating means includes means responsive to said counting means for applying to the reset input of said divide-by-N counter a selected horizontal sync pulse other than the first horizontal sync pulse counted by said counting means.

20. A descrambling circuit according to claim 18, wherein said gating means further includes a gate connected between said horizontal sync detector and the reset input of said divide-by-N counter and responsive to said horizontal sample generator means for passing a single horizontal sync pulse which appears in said vertical blanking interval.

21. A descrambling circuit according to claim 20, wherein said horizontal sample generator means includes first means responsive to said vertical sync detector for generating a gating pulse subsequent to detection of the vertical sync signal in said received video signal, second means connected to said horizontal sync detector and responsive to said gating signal for counting horizontal sync pulses and third means connecting said second means to said gate to enable said gate when said second means reaches a predetermined count.

22. A descrambling circuit according to claim 21, wherein said horizontal sample generator means further includes fourth means connected to the output of said gate for blocking application of said gating signal to said second means after a single horizontal sync pulse has passed said gate in each field of the received video signal.

23. A descrambling circuit according to claim 22, wherein said fourth means comprises a flip-flop which is switched to one state by the output of said gate and to a second state by said gating signal.

24. A descrambling circuit for descrambling a video signal which has been scrambled by horizontal sync signal suppression, comprising: first means for detecting the 3.58 MHz color burst carrier in said scrambled video signal; second means responsive to said first means for generating a decoding signal for descrambling said scrambled video signal; and third means connected to said second means for combining said scrambled video signal and said decoding signal to produce a descrambled video signal.

25. A descrambling circuit according to claim 24, wherein said third means comprises an analog multiplier.

26. A descrambling circuit according to claim 25, further comprising switch means connected between said second means and said analog multiplier means for preventing application of said decoding signal to said analog multiplier means during the vertical blanking interval of said video signal.

27. A descrambling circuit according to claim 26, wherein said second means comprises a phase locked loop connected to receive the output of said first means.

28. A descrambler circuit according to claim 27, wherein said second means further comprises wave shaping means connected to receive the output of said phase locked loop for generating a sine wave decoding signal.

29. A descrambler circuit according to claim 27, wherein said second means further comprises wave shaping means connected to receive the output of said phase locked loop for generating a square wave decoding signal.

30. A descrambling circuit according to claim 27, wherein said phase locked loop is capable of operating at first time constant and a second longer time constant, and further including time constant control means for controlling said phase locked loop to operate at said first time constant during the time of the vertical blanking interval of said video signal and to operate at said second time constant during the remainder of the frame time of said video signal.

31. A descrambling circuit for descrambling a video signal which has been scrambled by horizontal sync signal suppression, comprising: first means for detecting the horizontal sync pulses which are present in the vertical blanking interval of said scrambled video signal; second means responsive to said first means for generating a decoding signal for descrambling said scrambled video signal; and third means connected to said second means for combining said scrambled video signal and said decoding signal to produce a descrambled video signal.

32. A descrambling circuit according to claim 31, wherein said third means comprises an analog multiplier.

33. A descrambling circuit according to claim 32, further comprising switch means connected between said second means and said analog multiplier means for preventing application of said decoding signal to said analog multiplier means during the vertical blanking interval of said video signal.

34. A circuit for generating a descrambling signal for decoding a video signal which has been scrambled using horizontal sync signal suppression, comprising: first means connected to receive said scrambled video signal for detecting at least one horizontal sync pulse within the vertical blanking interval of said scrambled video signal; and second means responsive to the horizontal sync pulse detected by said first means for generating a descrambling signal for decoding said scrambled video signal.

OMPI

35. A circuit according to claim 34, wherein said second means comprises means including a highly stable oscillator for generating an output signal at a frequency which is an integra number N times the horizontal line rate of said video signal and a divide-by-N counter connected to receive the output of said oscillator, said divide-by-N counter being connected to said first means so as to be periodically reset by the horizontal sync pulse detected in the vertical blanking interval of said scrambled video signal.

36. A circuit according to claim 35, wherein said first means comprises a horizontal sync detector and a vertical sync detector each connected to receive said scrambled video signal and gating means connected to said horizontal sync detector an said vertical sync detector for gating at least one horizontal sync pulse in said vertical blanking interval following receip of a vertical sync pulse from said vertical sync detector, the output of said gating means being applied to reset said divide-by-N counter.

37. A circuit according to claim 36, wherein said gating means includes means responsive to said vertical sync detector for generating a gating pulse subsequent to detection of the vertical sync signal in said received video signal and a gate connected between said horizontal sync detector and the reset input of said divide-by-N counter and responsive to said gating pulse for passing at least one horizontal sync pulse which appears in said vertical blanking interval.

38. A circuit according to claim 37, wherein said gating pulse generating means comprises a one-shot multivibrator.

39. A circuit according to claim 38, wherein said gating pulse has a width sufficient to cause said gate to pass a plurality of horizontal sync pulses which appear in a single vertical blanking interval.

40. A circuit according to claim 36, wherein said gating means includes horizontal sample generator means connected to said horizontal and vertical sync detectors for sampling a single horizontal sync pulse in said vertical blanking interval following detection of the vertical sync pulse in the received video signal.

41. A circuit according to claim 40, wherein said horizontal sample generator means includes means for counting the horizontal sync pulses received following detection of said vertical sync pulse, and wherein said gating means includes means responsive to said counting means for applying to the reset input of said divide-by-N counter a selected horizontal sync pulse other than the first horizontal sync pulse counted by said counting means.

42. A circuit according to claim 40, wherein said gating means further includes a gate connected between said horizontal sync detector and the reset input of said divide-by-N counter and responsive to said horizontal sample generator means for passing a single horizontal sync pulse which appears in said vertical blanking interval.

43. A circuit according to claim 42, wherein said horizontal sample generator means includes first means responsive to said vertical sync detector for generating a gating pulse subsequent to detection of the vertical sync signal in said received video signal, second means connected to said horizontal sync detector and responsive to said gating signal for counting horizontal sync pulses and third means connecting said second means to said gate to enable said gate when said second means reaches a predetermined count.

44. A circuit according to claim 43, wherein said horizontal sample generator means further includes fourth means connected to the output of said gate for blocking application of said gating signal to said second means after a single horizontal sync pulse has passed said gate in each field of the received video signal.

45. A circuit according to claim 44, wherein said fourth means comprises a flip-flop which is switched to one state by the output of said gate and to a second state by said gating signal.

46. A circuit according to claim 34, wherein said second means comprises a phase locked loop connected to receive the output of said first means.

47. A circuit according to claim 47, wherein said first means comprises a vertical sync signal detector and a horizontal sync signal detector each connected to receive said scrambled video signal, and vertical interval detector means connected to said vertical sync signal detector for producing a gating pulse during said vertical blanking interval of said video signal and for gating said horizontal sync signal detector with said gating pulse so that it will be enabled to receive said horizontal sync pulses within said vertical blanking interval.

48. A circuit according to claim 34, wherein said first means comprises first horizontal sync signal detector means for detecting the horizontal sync pulses which are present during the vertical blanking interval of said video signal, and said second means comprises a phase locked loop connected to receive horizontal sync pulses from said horizontal sync signal detector means.

49. A circuit for generating a descrambling signal for detectong a video signal which has been scrambled using horizontal sync signal suppression, said video signal including a 3.58 MHz color burst carrier at the location of each suppressed horizontal sync signal, comprising first means connected to receive said scrambled video signal for detecting the 3.58 MHz color burst carrier therein; and second means responsive to said first means for generating said descrambling signal.

50. A circuit according to claim 49, wherein said second means comprises a phase-locked loop connected to receive the output of said first means.

51. A circuit according to claim 50, wherein said phase locked loop is capable of operating at first time constant and a second longer time constant, and further including time constant control means for controlling said phase locked loop to operate at said first time constant during the time of the vertical blanking interval of said video signal and to operate at said second time constant during the remainder of the frame time of said video signal.

OMPI

52. A method of securing video signals against unauthorized use, comprising the steps of scrambling said video signal by at least modifying the horizontal blanking intervals thereof so that normal detection of the horizontal sync pulses is prevented; and transmitting said scrambled video signal and a false decoding signal which cannot be used to accurately descramble the scrambled video signal.

53. A method according to claim 52, further comprising the steps of detecting an unmodified signal portion of said scrambled video signal not forming a part of said false decoding signal; generating a decoding signal solely on the basis of said detected unmodified signal portion; and combining said scrambled video signal and said decoding signal to produce an unscrambled video signal.

54. A method according to claim 53, further comprising the step of prohibiting said decoding signal from being combined with said scrambled video signal during the vertical blanking interval of said video signal.