WO1984004197A1 - Vertical d-mos eprom - Google Patents

Vertical d-mos eprom Download PDF

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Publication number
WO1984004197A1
WO1984004197A1 PCT/US1984/000358 US8400358W WO8404197A1 WO 1984004197 A1 WO1984004197 A1 WO 1984004197A1 US 8400358 W US8400358 W US 8400358W WO 8404197 A1 WO8404197 A1 WO 8404197A1
Authority
WO
WIPO (PCT)
Prior art keywords
cell
floating gate
transistor
channel
electrically
Prior art date
Application number
PCT/US1984/000358
Other languages
French (fr)
Inventor
Paul Denham
Original Assignee
Semi Processes Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semi Processes Inc filed Critical Semi Processes Inc
Publication of WO1984004197A1 publication Critical patent/WO1984004197A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM

Definitions

  • This invention relates to electrically program- mable, and erasable, memory.cells utilizing vertical D-MOS transistor technology.
  • the EPROM cell is a simple modification of a conventional n-channel MOS enhancement-mode transistor whose drain connects to a bit line and whose source is grounded.
  • the transistor's gate floats and is controlled by capacitive coupling to a polysilicon word line overlying the gate. Current conducted through the transistor is read as a logical "1", and the absence of current as a "0".
  • the cell is programmed to preserve a nonconducting state by applying high voltages to the word and bit lines simultaneously. Under those conditions, hot electrons are injected from the channel to the floating gate, charging it to a negative voltage. With the gate charged by the trapped electrons, the word line cannot couple enough voltage to it to turn on the transistor during a subsequent read operation. Exposing the cell to ultraviolet light elevates the trapped electrons' energy to the level of the conduction band of the surrounding oxide, and their mutual repulsion then causes them to flow off the gate.
  • a 256-K EPROM is described in an article entitled "E-PROMS graduate to 256-K Density With Scaled N-Channel Process" by M. Van Buskirk et al.. Electronics, February 24, 1983, pp. 89-93.
  • An EPROM which is electrically erasable is called an EEPROM or E 2 PROM.
  • EEPROMs A description of EEPROMs, and the manner in which bit-by-bit erasing is accomplished is described at pp. 220-239, Silicon Integrated Cir ⁇ cuits, edited by Dawson Kahng, Academic Press, 1981.
  • Vertical DMOS or D-MOS integrated circuit are used in high voltage, high-power applications, but have not been thought to be useful for applications such as programmable memory cells.
  • Vertical DMOS devices are described at pp. 45-47, Power FETS and Their Applica ⁇ tion, by Edwin S. Oxner, Prentice-Hall, Inc., 1982.
  • Disclosure of the Invention It is therefore an object of the invention to provide an improved EPROM which is faster, less costly, and smaller in size than conventional EPROMs.
  • Another object of the invention is to provide an improved EEPROM which is faster, less costly, and smaller in size than conventional EEPROMs.
  • DMOS vertical double-diffusion MOS
  • EPROM and EEPROM memory cell exhibit lower impedance than conventional designs. They are also much smaller and as a result they are less costly to fabricate. And because they make use of the short-channel of D-MOS technology they are con ⁇ siderably faster than conventional EPROMs and EEPROMs.
  • Figure 1A is a cross-sectional, schematic view, of a conventional EPROM memory cell ? and Figure 1B is an electrical schematic diagram of such a memory cell in an EPROM array.
  • Figure 2A is a cross-sectional, schematic view, of an EPROM memory cell in accordance with the present invention; and Figure 2B is an electrical schematic diagram of such a memory cell in an EPROM array.
  • Figure 3 is a cross-sectional, schematic view, of an EEPROM memory cell in accordance with the present invention.
  • FIG. 1A illustrates a conventional EPROM memory cell 10, employing N-channel MOS transistor technology, suitable for inclusion in an array of programmable cells.
  • EPROM cell 10 is formed from a p-type substrate 12.
  • a single diffusion forms the N-type source 14 and drain 16.
  • Suitable terminals 18 and 20 are provided to the source 14 and drain 16, respectively,
  • a p+ region defines the channel.
  • a polysilicon gate 22 is embedded in the gate oxide 24, so that it is electrically isolated.
  • a polysilicon word line 26 (a control gate if a single memory cell) connects the gates of memory cells 10 in the memory array.
  • a bit line 27 ( Figure 1A) , which runs perpendicular to the wordline 26, connects the respective drains 16.
  • Figure 1B illustrates schematic ⁇ ally cell 10 as one cell in a memory array.
  • the drain junction 20 is biased to avalanche breakdown. Electrons generated in the avalanche plasma are accelerated in the drain depletion region; some are injected from the silicon substrate 12 into the silicon dioxide 24.
  • ultraviolet light excitation is ordinarily used to remove electrons from the floating gate 22.
  • the package for the memory device 10 has a glass lid (not shown) that is trans ⁇ parent to ultraviolet light. Electrical erasing is difficult with this structure. Electrical erasing can be performed by either neutralization or emitting the negative charge in the floating gate 22, by the addition of further compli ⁇ cated structures.
  • Figure 2B illustrates a vertical DMOS EPROM memory cell 30, in accordance with the present inven ⁇ tion.
  • the n+ substrate underside 32 forms the drain region.
  • the "'body” is equivalent to the sub ⁇ strate 12 of the conventional transistor and is formed by a first, p-type, diffusion 34.
  • a second, n-type, diffusion 36 forms the source, which is connected with a source terminal 38.
  • this is defined by the opening used for the body.
  • the latter also provides a source-to-body connection to define the body 34 potential.
  • a polysilicon floating gate 40 is embedded within oxide 42.
  • the narrow region 44 in the body 34 forms the channel.
  • a polysilicon word line 46 (or control gate for a single cell 30) is formed above the narrow channel region 44.
  • drain current, I passes downwardly to the drain 32.
  • Writing cell 30 is conventionally done. And in the case of an EPROM implementation erasing is accom ⁇ plished by the use of ultraviolet light, as previously described.
  • the electrical schematic for one memory cell 30 in a EPROM array is shown in Figure 2B. Note that bit- line 48 is connected to source 38, instead of to the drain, as in the case of conventional memory cell 10. With a conventional N-channel EPROM device 10, when a positive voltage is placed on the word line 26, a binary "0" appears on the bit-line 27. In the case of the vertical DMOS EPROM 30 the opposite occurs: a positive voltage on word line 46 provides a binary -1" on bit-line 48.
  • Memory cell 30 has significant advantages over the conventional EPROM cell 10. Because of its vertical current path it is smaller, and therefore less expen ⁇ sive to fabricate. Because of its short channel region, it is faster than conventional EPROMS.
  • a second p-type diffusion region 50 is provided, to which a terminal 52 is provided. This region can be diffused during the first diffusion when the body 34 is diffused, or done as a separate diffusion step.
  • region 50 with the other p-type region 34, forms a p-channel MOS device with the n-region forming the channel under gate 40.
  • This EEPROM configuration is faster, smaller, and less expensive than conventional EEPROM designs.
  • electrode 52 is raised to a negative potential relative to electrode 38, while the control gate 46 goes negative. This injects high-energy "holes” through the oxide 42 to gate 40, thereby neutralizing any previously “written” negative charges. In essence. the addition of the p-region 50 creates a conventional p-channel addition to the vertical D-MOS cell 30.
  • cells of the present invention are not re _. »stricted to programmable memory arrays but can be applied to any circuit configuration where programmable elements are required, such as pro ⁇ grammable logic arrays.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Vertical D-MOS technology is utilized to form an EPROM memory cell. An additional diffusion region is added in order to electrically erase the EPROM.

Description

Description VERTICAL D-MOS EPROM
Technical Field
This invention relates to electrically program- mable, and erasable, memory.cells utilizing vertical D-MOS transistor technology.
Background Art
The EPROM cell is a simple modification of a conventional n-channel MOS enhancement-mode transistor whose drain connects to a bit line and whose source is grounded. The transistor's gate floats and is controlled by capacitive coupling to a polysilicon word line overlying the gate. Current conducted through the transistor is read as a logical "1", and the absence of current as a "0".
The cell is programmed to preserve a nonconducting state by applying high voltages to the word and bit lines simultaneously. Under those conditions, hot electrons are injected from the channel to the floating gate, charging it to a negative voltage. With the gate charged by the trapped electrons, the word line cannot couple enough voltage to it to turn on the transistor during a subsequent read operation. Exposing the cell to ultraviolet light elevates the trapped electrons' energy to the level of the conduction band of the surrounding oxide, and their mutual repulsion then causes them to flow off the gate. A 256-K EPROM is described in an article entitled "E-PROMS Graduate to 256-K Density With Scaled N-Channel Process" by M. Van Buskirk et al.. Electronics, February 24, 1983, pp. 89-93.
An EPROM which is electrically erasable is called an EEPROM or E 2 PROM. A description of EEPROMs, and the manner in which bit-by-bit erasing is accomplished is described at pp. 220-239, Silicon Integrated Cir¬ cuits, edited by Dawson Kahng, Academic Press, 1981.
Existing EPROMs and EEPROMs use lateral or planar structures which require large geometries. This results in lower yields, higher costs, slower circuit operation, and comparatively high impedances.
Vertical DMOS or D-MOS integrated circuit are used in high voltage, high-power applications, but have not been thought to be useful for applications such as programmable memory cells. Vertical DMOS devices are described at pp. 45-47, Power FETS and Their Applica¬ tion, by Edwin S. Oxner, Prentice-Hall, Inc., 1982.
Disclosure of the Invention It is therefore an object of the invention to provide an improved EPROM which is faster, less costly, and smaller in size than conventional EPROMs.
Another object of the invention is to provide an improved EEPROM which is faster, less costly, and smaller in size than conventional EEPROMs.
In accordance with the present invention vertical double-diffusion MOS (DMOS) technology is utilized as an EPROM and EEPROM memory cell. Such EPROM and EEPROM cells exhibit lower impedance than conventional designs. They are also much smaller and as a result they are less costly to fabricate. And because they make use of the short-channel of D-MOS technology they are con¬ siderably faster than conventional EPROMs and EEPROMs.
Brief Description of the Drawings Figure 1A is a cross-sectional, schematic view, of a conventional EPROM memory cell? and Figure 1B is an electrical schematic diagram of such a memory cell in an EPROM array. Figure 2A is a cross-sectional, schematic view, of an EPROM memory cell in accordance with the present invention; and Figure 2B is an electrical schematic diagram of such a memory cell in an EPROM array. Figure 3 is a cross-sectional, schematic view, of an EEPROM memory cell in accordance with the present invention.
Best Mode for Carrying Out the Invention
Figure 1A illustrates a conventional EPROM memory cell 10, employing N-channel MOS transistor technology, suitable for inclusion in an array of programmable cells. EPROM cell 10 is formed from a p-type substrate 12. A single diffusion forms the N-type source 14 and drain 16. Suitable terminals 18 and 20 are provided to the source 14 and drain 16, respectively, A p+ region defines the channel.
A polysilicon gate 22 is embedded in the gate oxide 24, so that it is electrically isolated. A polysilicon word line 26 (a control gate if a single memory cell) connects the gates of memory cells 10 in the memory array. A bit line 27 (Figure 1A) , which runs perpendicular to the wordline 26, connects the respective drains 16. Figure 1B illustrates schematic¬ ally cell 10 as one cell in a memory array. To write the EPROM 10, the drain junction 20 is biased to avalanche breakdown. Electrons generated in the avalanche plasma are accelerated in the drain depletion region; some are injected from the silicon substrate 12 into the silicon dioxide 24. These injected electrons are drifted by the field that is induced in the gate oxide by capacitive coupling of the floating gate 22 to the source and drain electrodes 18 and 20. The avalanche-breakdown voltage of the drain 10 junction under the floating gate 22 depends on the floating gate 22 potential. Because the injected electrons charge the floating gate 22 negatively, the avalanche-breakdown voltage increases. Furthermore, the drain 16 reverse bias, VD, pulls the floating gate 22 to a negative potential. This also helps increase the avalanche-breakdown voltage, which decreases the avalanche-injection current and retards the writing operation.
To erase the EPROM memory 10, ultraviolet light excitation is ordinarily used to remove electrons from the floating gate 22. The package for the memory device 10 has a glass lid (not shown) that is trans¬ parent to ultraviolet light. Electrical erasing is difficult with this structure. Electrical erasing can be performed by either neutralization or emitting the negative charge in the floating gate 22, by the addition of further compli¬ cated structures.
Figure 2B illustrates a vertical DMOS EPROM memory cell 30, in accordance with the present inven¬ tion. Here the n+ substrate underside 32 forms the drain region. The "'body" is equivalent to the sub¬ strate 12 of the conventional transistor and is formed by a first, p-type, diffusion 34. A second, n-type, diffusion 36 forms the source, which is connected with a source terminal 38. As in conventional DMOS techno¬ logy this is defined by the opening used for the body. The latter also provides a source-to-body connection to define the body 34 potential. A polysilicon floating gate 40 is embedded within oxide 42. The narrow region 44 in the body 34 forms the channel. A polysilicon word line 46 (or control gate for a single cell 30) is formed above the narrow channel region 44. After passing through the channel 44, drain current, I , passes downwardly to the drain 32. Writing cell 30 is conventionally done. And in the case of an EPROM implementation erasing is accom¬ plished by the use of ultraviolet light, as previously described. The electrical schematic for one memory cell 30 in a EPROM array is shown in Figure 2B. Note that bit- line 48 is connected to source 38, instead of to the drain, as in the case of conventional memory cell 10. With a conventional N-channel EPROM device 10, when a positive voltage is placed on the word line 26, a binary "0" appears on the bit-line 27. In the case of the vertical DMOS EPROM 30 the opposite occurs: a positive voltage on word line 46 provides a binary -1" on bit-line 48. Memory cell 30 has significant advantages over the conventional EPROM cell 10. Because of its vertical current path it is smaller, and therefore less expen¬ sive to fabricate. Because of its short channel region, it is faster than conventional EPROMS. Referring now to Figure 3, to make memory cell 30 electrically erasable a second p-type diffusion region 50 is provided, to which a terminal 52 is provided. This region can be diffused during the first diffusion when the body 34 is diffused, or done as a separate diffusion step. The addition of region 50, with the other p-type region 34, forms a p-channel MOS device with the n-region forming the channel under gate 40. This EEPROM configuration is faster, smaller, and less expensive than conventional EEPROM designs. To erase, electrode 52 is raised to a negative potential relative to electrode 38, while the control gate 46 goes negative. This injects high-energy "holes" through the oxide 42 to gate 40, thereby neutralizing any previously "written" negative charges. In essence. the addition of the p-region 50 creates a conventional p-channel addition to the vertical D-MOS cell 30.
The uses of cells of the present invention are not re _. »stricted to programmable memory arrays but can be applied to any circuit configuration where programmable elements are required, such as pro¬ grammable logic arrays.

Claims

Claims ;
* 1. An electrically programmable transistor cell comprising:
. a D-MOS integrated circuit transistor; said transistor having a drain region formed by the 5 transistor substrate; a channel region formed by a first p-type diffusion, and a source formed by a second N-type diffusion within said first diffusion; and a floating gate extending over and insulated 10 from said channel, said floating gate being electrically isolated.
2. An electrically programmable cell as in Claim 1 including a control gate for programming said cell extending over, and electrically insulated from, said floating gate.
3. An electrically programmable cell as in Claim 2 wherein said control gate is a word line, and having a bit line connected to said source.
4. An electrically programmable cell as in Claim 3 including means for erasing the state of electrical charge on said floating gate.
5. An electrically programmable cell as in Claim 4 wherein said erasing means comprises means for injecting holes to said floating gate.
6. An electrically programmable cell as in Claim 5 wherein said hole injecting means comprises an adjacent p-channel transistor formed by a second p-type diffusion region.
OMP WIP
7. In a matrix array of programmable memory cells, having word lines and bit lines connected to each of the memory cells, wherein the improvement compri *ses an improved memory cell therefore comprising a vertical D-MOS type transistor device having an electrically isolated floating gate, and means for programming the state of said cell.
8. The array of Claim 7 wherein each of said memory cells is provided with means for electrically erasing the state of a programmed memory, cell.
9. The array of Claim 8 wherein said D-MOS type transitor is N-channel and wherein said .erasing means comprises an adjacent p-channel transistor, utilizing a p-type diffusion of said D-MOS transitor, to inject holes, to said floating gate.
PCT/US1984/000358 1983-04-11 1984-03-08 Vertical d-mos eprom WO1984004197A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US48377883A 1983-04-11 1983-04-11

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EP (1) EP0142516A1 (en)
JP (1) JPS60501187A (en)
IT (1) IT1176010B (en)
WO (1) WO1984004197A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831329A (en) * 1993-04-07 1998-11-03 Forschungszentrum Julich Gmbh Layered system with an electrically activatable layer
US7986005B2 (en) * 2007-07-27 2011-07-26 Infineon Technologies Austria Ag Short circuit limiting in power semiconductor devices
WO2021109160A1 (en) * 2019-12-03 2021-06-10 苏州东微半导体有限公司 Method for manufacturing semiconductor power device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4161039A (en) * 1976-12-15 1979-07-10 Siemens Aktiengesellschaft N-Channel storage FET
JPS5567161A (en) * 1978-11-14 1980-05-21 Seiko Epson Corp Semiconductor memory storage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4161039A (en) * 1976-12-15 1979-07-10 Siemens Aktiengesellschaft N-Channel storage FET
JPS5567161A (en) * 1978-11-14 1980-05-21 Seiko Epson Corp Semiconductor memory storage

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Vol. 24, No, 2, issued July 1981, P.C. TIEN, Source Side Decoder for an Earos, pages 942-944 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831329A (en) * 1993-04-07 1998-11-03 Forschungszentrum Julich Gmbh Layered system with an electrically activatable layer
US7986005B2 (en) * 2007-07-27 2011-07-26 Infineon Technologies Austria Ag Short circuit limiting in power semiconductor devices
WO2021109160A1 (en) * 2019-12-03 2021-06-10 苏州东微半导体有限公司 Method for manufacturing semiconductor power device

Also Published As

Publication number Publication date
EP0142516A1 (en) 1985-05-29
JPS60501187A (en) 1985-07-25
IT1176010B (en) 1987-08-12
IT8420489A0 (en) 1984-04-11

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