WO1985002037A2 - Microcomputer - Google Patents

Microcomputer Download PDF

Info

Publication number
WO1985002037A2
WO1985002037A2 PCT/GB1984/000377 GB8400377W WO8502037A2 WO 1985002037 A2 WO1985002037 A2 WO 1985002037A2 GB 8400377 W GB8400377 W GB 8400377W WO 8502037 A2 WO8502037 A2 WO 8502037A2
Authority
WO
WIPO (PCT)
Prior art keywords
register
list
processes
microcomputer
indicates
Prior art date
Application number
PCT/GB1984/000377
Other languages
French (fr)
Other versions
WO1985002037A3 (en
Inventor
Michael David May
Roger Mark Shepherd
Original Assignee
Inmos Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inmos Ltd filed Critical Inmos Ltd
Publication of WO1985002037A2 publication Critical patent/WO1985002037A2/en
Publication of WO1985002037A3 publication Critical patent/WO1985002037A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Abstract

A microcomputer comprising memory (60) and a process is arranged to execute a plurality of concurrent processes and share its time between them. The microcomputer includes a register (51) for indicating a current process as well as a collection of processes awaiting execution. Each process has a memory location (66) to provide an indication of a next process in a linked list of processes. Each process has an allocated priority and a separate linked list is formed for each priority. A register (53) indicates the front of one list and a further register (52) indicates the end of that list.
PCT/GB1984/000377 1983-11-04 1984-11-02 Microcomputer WO1985002037A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB838329509A GB8329509D0 (en) 1983-11-04 1983-11-04 Computer
GB8329509 1983-11-04

Publications (2)

Publication Number Publication Date
WO1985002037A2 true WO1985002037A2 (en) 1985-05-09
WO1985002037A3 WO1985002037A3 (en) 1985-07-18

Family

ID=10551256

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/GB1984/000377 WO1985002037A2 (en) 1983-11-04 1984-11-02 Microcomputer
PCT/GB1984/000378 WO1985002038A2 (en) 1983-11-04 1984-11-02 Microcomputer
PCT/GB1984/000379 WO1985002039A2 (en) 1983-11-04 1984-11-02 Microcomputer

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/GB1984/000378 WO1985002038A2 (en) 1983-11-04 1984-11-02 Microcomputer
PCT/GB1984/000379 WO1985002039A2 (en) 1983-11-04 1984-11-02 Microcomputer

Country Status (6)

Country Link
US (3) US4783734A (en)
EP (3) EP0141660B1 (en)
JP (3) JP2664663B2 (en)
DE (3) DE3481389D1 (en)
GB (1) GB8329509D0 (en)
WO (3) WO1985002037A2 (en)

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US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
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US5379428A (en) * 1993-02-01 1995-01-03 Belobox Systems, Inc. Hardware process scheduler and processor interrupter for parallel processing computer systems
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US7424712B1 (en) * 1999-04-30 2008-09-09 Sun Microsystems Inc System and method for controlling co-scheduling of processes of parallel program
US6442631B1 (en) 1999-05-07 2002-08-27 Compaq Information Technologies Group, L.P. Allocating system resources based upon priority
US7046686B1 (en) * 1999-08-17 2006-05-16 Mindspeed Technologies, Inc. Integrated circuit that processes communication packets with a buffer management engine having a pointer cache
US6559783B1 (en) * 2000-08-16 2003-05-06 Microchip Technology Incorporated Programmable auto-converting analog to digital conversion module
US6772300B1 (en) * 2000-08-30 2004-08-03 Intel Corporation Method and apparatus for managing out of order memory transactions
US6751711B1 (en) * 2000-10-27 2004-06-15 Nortel Networks Limited Methods and systems for process rollback in a shared memory parallel processor computing environment
JP3610915B2 (en) * 2001-03-19 2005-01-19 株式会社デンソー Processing execution apparatus and program
US6874054B2 (en) * 2002-12-19 2005-03-29 Emulex Design & Manufacturing Corporation Direct memory access controller system with message-based programming
EP1820117A2 (en) * 2004-11-11 2007-08-22 International Business Machines Corporation Concurrent flashing of processing units by means of network restructuring
US20060143415A1 (en) * 2004-12-29 2006-06-29 Uday Naik Managing shared memory access
US7386642B2 (en) * 2005-01-28 2008-06-10 Sony Computer Entertainment Inc. IO direct memory access system and method
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JP5079342B2 (en) 2007-01-22 2012-11-21 ルネサスエレクトロニクス株式会社 Multiprocessor device
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Citations (4)

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US3805247A (en) * 1972-05-16 1974-04-16 Burroughs Corp Description driven microprogrammable multiprocessor system
US4172284A (en) * 1976-12-30 1979-10-23 International Business Machines Corporation Priority interrupt apparatus employing a plural stage shift register having separate interrupt mechanisms coupled to the different stages thereof for segregating interrupt requests according to priority levels
WO1984004188A1 (en) * 1983-04-11 1984-10-25 Inmos Ltd Microcomputer with interprocess communication

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US3805247A (en) * 1972-05-16 1974-04-16 Burroughs Corp Description driven microprogrammable multiprocessor system
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WO1984004188A1 (en) * 1983-04-11 1984-10-25 Inmos Ltd Microcomputer with interprocess communication

Also Published As

Publication number Publication date
JPS61500387A (en) 1986-03-06
EP0145244B1 (en) 1990-02-21
WO1985002038A2 (en) 1985-05-09
EP0141660A3 (en) 1985-10-02
US4794526A (en) 1988-12-27
JP2664663B2 (en) 1997-10-15
WO1985002038A3 (en) 1985-07-18
DE3481389D1 (en) 1990-03-29
US4758948A (en) 1988-07-19
WO1985002039A2 (en) 1985-05-09
GB8329509D0 (en) 1983-12-07
JP2664664B2 (en) 1997-10-15
DE3483306D1 (en) 1990-10-31
EP0149311A2 (en) 1985-07-24
EP0145244A2 (en) 1985-06-19
JPS61500385A (en) 1986-03-06
DE3481946D1 (en) 1990-05-17
EP0149311B1 (en) 1990-04-11
EP0145244A3 (en) 1985-09-25
JP2664662B2 (en) 1997-10-15
JPS61500386A (en) 1986-03-06
EP0149311A3 (en) 1985-09-25
EP0141660B1 (en) 1990-09-26
US4783734A (en) 1988-11-08
WO1985002037A3 (en) 1985-07-18
WO1985002039A3 (en) 1985-07-18
EP0141660A2 (en) 1985-05-15

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Legal Events

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Designated state(s): JP US

CR1 Correction of entry in section i

Free format text: IN PAT.BUL.11/85,UNDER PUBLISHED REPLACE THE KIND OF DOCUMENT A1 BY A2

AK Designated states

Designated state(s): JP US