WO1985002038A2 - Microcomputer - Google Patents

Microcomputer Download PDF

Info

Publication number
WO1985002038A2
WO1985002038A2 PCT/GB1984/000378 GB8400378W WO8502038A2 WO 1985002038 A2 WO1985002038 A2 WO 1985002038A2 GB 8400378 W GB8400378 W GB 8400378W WO 8502038 A2 WO8502038 A2 WO 8502038A2
Authority
WO
WIPO (PCT)
Prior art keywords
bytes
pointer
processor
transmitted
data
Prior art date
Application number
PCT/GB1984/000378
Other languages
French (fr)
Other versions
WO1985002038A3 (en
Inventor
Michael David May
Roger Mark Shepherd
Original Assignee
Inmos Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inmos Ltd filed Critical Inmos Ltd
Publication of WO1985002038A2 publication Critical patent/WO1985002038A2/en
Publication of WO1985002038A3 publication Critical patent/WO1985002038A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Abstract

A microcomputer comprises memory and a processor and is arranged to execute a plurality of concurrent processes and to affect message transmission by use of communication channels. Each message consists of one or more bytes and the communication means includes means (111) for indicating the number of bytes to be transmitted and a pointer (112) to the source of the data to be transmitted. The processor also includes a pointer to the destination for data which is input by a process.
PCT/GB1984/000378 1983-11-04 1984-11-02 Microcomputer WO1985002038A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8329509 1983-11-04
GB838329509A GB8329509D0 (en) 1983-11-04 1983-11-04 Computer

Publications (2)

Publication Number Publication Date
WO1985002038A2 true WO1985002038A2 (en) 1985-05-09
WO1985002038A3 WO1985002038A3 (en) 1985-07-18

Family

ID=10551256

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/GB1984/000377 WO1985002037A2 (en) 1983-11-04 1984-11-02 Microcomputer
PCT/GB1984/000378 WO1985002038A2 (en) 1983-11-04 1984-11-02 Microcomputer
PCT/GB1984/000379 WO1985002039A2 (en) 1983-11-04 1984-11-02 Microcomputer

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/GB1984/000377 WO1985002037A2 (en) 1983-11-04 1984-11-02 Microcomputer

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/GB1984/000379 WO1985002039A2 (en) 1983-11-04 1984-11-02 Microcomputer

Country Status (6)

Country Link
US (3) US4758948A (en)
EP (3) EP0145244B1 (en)
JP (3) JP2664663B2 (en)
DE (3) DE3481946D1 (en)
GB (1) GB8329509D0 (en)
WO (3) WO1985002037A2 (en)

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US7424712B1 (en) * 1999-04-30 2008-09-09 Sun Microsystems Inc System and method for controlling co-scheduling of processes of parallel program
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US6754223B1 (en) * 1999-08-17 2004-06-22 Conexant Systems, Inc. Integrated circuit that processes communication packets with co-processor circuitry to determine a prioritized processing order for a core processor
US6559783B1 (en) * 2000-08-16 2003-05-06 Microchip Technology Incorporated Programmable auto-converting analog to digital conversion module
US6772300B1 (en) * 2000-08-30 2004-08-03 Intel Corporation Method and apparatus for managing out of order memory transactions
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Citations (1)

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WO1984004188A1 (en) * 1983-04-11 1984-10-25 Inmos Ltd Microcomputer with interprocess communication

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Publication number Priority date Publication date Assignee Title
WO1984004188A1 (en) * 1983-04-11 1984-10-25 Inmos Ltd Microcomputer with interprocess communication

Also Published As

Publication number Publication date
EP0141660A2 (en) 1985-05-15
JP2664663B2 (en) 1997-10-15
EP0145244A3 (en) 1985-09-25
JP2664664B2 (en) 1997-10-15
JP2664662B2 (en) 1997-10-15
EP0149311A3 (en) 1985-09-25
EP0141660A3 (en) 1985-10-02
EP0149311B1 (en) 1990-04-11
JPS61500386A (en) 1986-03-06
DE3483306D1 (en) 1990-10-31
WO1985002039A2 (en) 1985-05-09
EP0145244A2 (en) 1985-06-19
EP0145244B1 (en) 1990-02-21
US4758948A (en) 1988-07-19
US4783734A (en) 1988-11-08
EP0149311A2 (en) 1985-07-24
US4794526A (en) 1988-12-27
WO1985002038A3 (en) 1985-07-18
WO1985002037A2 (en) 1985-05-09
DE3481946D1 (en) 1990-05-17
WO1985002039A3 (en) 1985-07-18
DE3481389D1 (en) 1990-03-29
GB8329509D0 (en) 1983-12-07
WO1985002037A3 (en) 1985-07-18
JPS61500385A (en) 1986-03-06
JPS61500387A (en) 1986-03-06
EP0141660B1 (en) 1990-09-26

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Legal Events

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AK Designated states

Designated state(s): JP US

CR1 Correction of entry in section i

Free format text: IN PAT.BUL.11/85,UNDER PUBLISHED REPLACE THE KIND OF DOCUMENT A1 BY A2

AK Designated states

Designated state(s): JP US